#include <asm/cpufeature.h>
#include <asm/spec_ctrl.h>
+#include <asm/spec-ctrl.h>
#include <asm/microcode.h>
#define MWAIT_SUBSTATE_MASK 0xf
}
if (ibrs_inuse)
- native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
+ native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default());
__monitor((void *)¤t_thread_info()->flags, 0, 0);
if (!need_resched())
__mwait(eax, ecx);
if (ibrs_inuse)
- native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
+ native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS);
}
current_clr_polling();
}
}
if (ibrs_inuse)
- native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
+ native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default());
__monitor((void *)¤t_thread_info()->flags, 0, 0);
if (!need_resched()) {
__sti_mwait(0, 0);
if (ibrs_inuse)
- native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
+ native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS);
} else {
if (ibrs_inuse)
- native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
+ native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS);
local_irq_enable();
}
trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
#include <asm/i8259.h>
#include <asm/realmode.h>
#include <asm/misc.h>
+#include <asm/spec-ctrl.h>
#include <asm/microcode.h>
/* Number of siblings per CPU package */
tboot_shutdown(TB_SHUTDOWN_WFS);
if (ibrs_inuse)
- native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
+ native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default());
mwait_play_dead(); /* Only returns on failure */
if (cpuidle_play_dead())
hlt_play_dead();
if (ibrs_inuse)
- native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
+ native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS);
}
#else /* ... !CONFIG_HOTPLUG_CPU */
delay = min_t(u64, MWAITX_MAX_LOOPS, loops);
if (ibrs_inuse && (delay > IBRS_DISABLE_THRESHOLD))
- native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
+ native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default());
/*
* Use cpu_tss_rw as a cacheline-aligned, seldomly
__mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
if (ibrs_inuse && (delay > IBRS_DISABLE_THRESHOLD))
- native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
+ native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS);
end = rdtsc_ordered();
#include <asm/nmi.h>
#include <asm/stacktrace.h>
#include <asm/io.h>
+#include <asm/spec-ctrl.h>
#endif
#ifdef CONFIG_SPARC
#include <asm/setup.h>
set_ibrs_disabled();
if (ibrs_supported) {
for_each_online_cpu(cpu)
- wrmsrl_on_cpu(cpu, MSR_IA32_SPEC_CTRL, 0x0);
+ wrmsrl_on_cpu(cpu, MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default());
}
} else if (sysctl_ibrs_enabled == 2) {
/* always set IBRS on, even in user space */
clear_ibrs_disabled();
if (ibrs_supported) {
for_each_online_cpu(cpu)
- wrmsrl_on_cpu(cpu, MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
+ wrmsrl_on_cpu(cpu, MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS);
} else {
sysctl_ibrs_enabled = 0;
}