arch/x86/include/asm/mwait.h

   1 #ifndef _ASM_X86_MWAIT_H
   2 #define _ASM_X86_MWAIT_H
   3
   4 #include <linux/sched.h>
   5 #include <linux/sched/idle.h>
   6
   7 #include <asm/cpufeature.h>
   8 #include <asm/spec_ctrl.h>
   9 #include <asm/spec-ctrl.h>
  10 #include <asm/microcode.h>
  11
  12 #define MWAIT_SUBSTATE_MASK             0xf
  13 #define MWAIT_CSTATE_MASK               0xf
  14 #define MWAIT_SUBSTATE_SIZE             4
  15 #define MWAIT_HINT2CSTATE(hint)         (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
  16 #define MWAIT_HINT2SUBSTATE(hint)       ((hint) & MWAIT_CSTATE_MASK)
  17
  18 #define CPUID_MWAIT_LEAF                5
  19 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
  20 #define CPUID5_ECX_INTERRUPT_BREAK      0x2
  21
  22 #define MWAIT_ECX_INTERRUPT_BREAK       0x1
  23 #define MWAITX_ECX_TIMER_ENABLE         BIT(1)
  24 #define MWAITX_MAX_LOOPS                ((u32)-1)
  25 #define MWAITX_DISABLE_CSTATES          0xf
  26
  27 static inline void __monitor(const void *eax, unsigned long ecx,
  28                              unsigned long edx)
  29 {
  30         /* "monitor %eax, %ecx, %edx;" */
  31         asm volatile(".byte 0x0f, 0x01, 0xc8;"
  32                      :: "a" (eax), "c" (ecx), "d"(edx));
  33 }
  34
  35 static inline void __monitorx(const void *eax, unsigned long ecx,
  36                               unsigned long edx)
  37 {
  38         /* "monitorx %eax, %ecx, %edx;" */
  39         asm volatile(".byte 0x0f, 0x01, 0xfa;"
  40                      :: "a" (eax), "c" (ecx), "d"(edx));
  41 }
  42
  43 static inline void __mwait(unsigned long eax, unsigned long ecx)
  44 {
  45         /* "mwait %eax, %ecx;" */
  46         asm volatile(".byte 0x0f, 0x01, 0xc9;"
  47                      :: "a" (eax), "c" (ecx));
  48 }
  49
  50 /*
  51  * MWAITX allows for a timer expiration to get the core out a wait state in
  52  * addition to the default MWAIT exit condition of a store appearing at a
  53  * monitored virtual address.
  54  *
  55  * Registers:
  56  *
  57  * MWAITX ECX[1]: enable timer if set
  58  * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0
  59  * frequency is the same as the TSC frequency.
  60  *
  61  * Below is a comparison between MWAIT and MWAITX on AMD processors:
  62  *
  63  *                 MWAIT                           MWAITX
  64  * opcode          0f 01 c9           |            0f 01 fb
  65  * ECX[0]                  value of RFLAGS.IF seen by instruction
  66  * ECX[1]          unused/#GP if set  |            enable timer if set
  67  * ECX[31:2]                     unused/#GP if set
  68  * EAX                           unused (reserve for hint)
  69  * EBX[31:0]       unused             |            max wait time (P0 clocks)
  70  *
  71  *                 MONITOR                         MONITORX
  72  * opcode          0f 01 c8           |            0f 01 fa
  73  * EAX                     (logical) address to monitor
  74  * ECX                     #GP if not zero
  75  */
  76 static inline void __mwaitx(unsigned long eax, unsigned long ebx,
  77                             unsigned long ecx)
  78 {
  79         /* "mwaitx %eax, %ebx, %ecx;" */
  80         asm volatile(".byte 0x0f, 0x01, 0xfb;"
  81                      :: "a" (eax), "b" (ebx), "c" (ecx));
  82 }
  83
  84 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
  85 {
  86         trace_hardirqs_on();
  87         /* "mwait %eax, %ecx;" */
  88         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
  89                      :: "a" (eax), "c" (ecx));
  90 }
  91
  92 /*
  93  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
  94  * which can obviate IPI to trigger checking of need_resched.
  95  * We execute MONITOR against need_resched and enter optimized wait state
  96  * through MWAIT. Whenever someone changes need_resched, we would be woken
  97  * up from MWAIT (without an IPI).
  98  *
  99  * New with Core Duo processors, MWAIT can take some hints based on CPU
 100  * capability.
 101  */
 102 static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
 103 {
 104         if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) {
 105                 if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {
 106                         mb();
 107                         clflush((void *)&current_thread_info()->flags);
 108                         mb();
 109                 }
 110
 111                 if (ibrs_inuse)
 112                         native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default());
 113
 114                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 115                 if (!need_resched())
 116                         __mwait(eax, ecx);
 117
 118                 if (ibrs_inuse)
 119                         native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS);
 120         }
 121         current_clr_polling();
 122 }
 123
 124 #endif /* _ASM_X86_MWAIT_H */