ArmPkg/ArmMmuLib ARM: drop memory type check for page tables

We already expect normal memory to be mapped writeback cacheable if
EDK2 itself is to make use of it, so doing an early sanity check on
the memory type of the allocation that the page tables happened to
land in isn't very useful. So let's drop it.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
index a6f44dbd5f21c0bf85962c29858ce654321c4e1c..15e836e75e8eb9144326ded83ea6ab01742302d6 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
@@ -328,7 +328,6 @@ ArmConfigureMmu (
   )\r
 {\r
   VOID                          *TranslationTable;\r
-  ARM_MEMORY_REGION_ATTRIBUTES  TranslationTableAttribute;\r
   UINT32                        TTBRAttributes;\r
 \r
   TranslationTable = AllocateAlignedPages (\r
@@ -353,28 +352,13 @@ ArmConfigureMmu (
   InvalidateDataCacheRange (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);\r
   ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);\r
 \r
-  // By default, mark the translation table as belonging to a uncached region\r
-  TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;\r
   while (MemoryTable->Length != 0) {\r
-    // Find the memory attribute for the Translation Table\r
-    if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {\r
-      TranslationTableAttribute = MemoryTable->Attributes;\r
-    }\r
-\r
     FillTranslationTable (TranslationTable, MemoryTable);\r
     MemoryTable++;\r
   }\r
 \r
-  // Translate the Memory Attributes into Translation Table Register Attributes\r
-  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
-    TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;\r
-  } else {\r
-    // Page tables must reside in memory mapped as write-back cacheable\r
-    ASSERT (0);\r
-    return RETURN_UNSUPPORTED;\r
-  }\r
-\r
+  TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC\r
+                                         : TTBR_WRITE_BACK_ALLOC;\r
   if (TTBRAttributes & TTBR_SHAREABLE) {\r
     if (PreferNonshareableMemory ()) {\r
       TTBRAttributes ^= TTBR_SHAREABLE;\r