BaseTools/GenFw: allow AArch64 tiny and small code model relocations

The AArch64 small C model makes extensive use of ADRP/ADD and
ADRP/{LDR,STR} pairs to emit PC-relative symbol references with
a +/- 4 GB range. Since the relocation pair splits the relative
offset into a relative page offset and an absolute offset into
a 4 KB page, we need to take extra care to ensure that the target
of the relocation preserves its alignment relative to a 4 KB
alignment boundary.

Also, due to a problem with the --emit-relocs GNU ld option, where
it does not recalculate the addends for section relative relocations,
the only way to guarantee correct code is by requiring the relative
section offset to be equal in the ELF and PE/COFF versions of the
binary. This affects both the 'tiny' and 'small' GCC code models.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18197 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 1c0f4a4dc87cc15b042d3e5ab71808be49d4cc19..c758ed9d64a61adeebee644c00fc0b60d921f0a8 100644 (file)
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -740,53 +740,60 @@ WriteSections64 (
           }\r
         } else if (mEhdr->e_machine == EM_AARCH64) {\r
 \r
-          // AARCH64 GCC uses RELA relocation, so all relocations have to be fixed up.\r
-          // As opposed to ARM32 using REL.\r
-\r
           switch (ELF_R_TYPE(Rel->r_info)) {\r
 \r
-          case R_AARCH64_ADR_PREL_LO21:\r
-            if  (Rel->r_addend != 0 ) { /* TODO */\r
-              Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_ADR_PREL_LO21 Need to fixup with addend!.");\r
+          case R_AARCH64_ADR_PREL_PG_HI21:\r
+          case R_AARCH64_ADD_ABS_LO12_NC:\r
+          case R_AARCH64_LDST8_ABS_LO12_NC:\r
+          case R_AARCH64_LDST16_ABS_LO12_NC:\r
+          case R_AARCH64_LDST32_ABS_LO12_NC:\r
+          case R_AARCH64_LDST64_ABS_LO12_NC:\r
+          case R_AARCH64_LDST128_ABS_LO12_NC:\r
+            //\r
+            // AArch64 PG_H21 relocations are typically paired with ABS_LO12\r
+            // relocations, where a PC-relative reference with +/- 4 GB range is\r
+            // split into a relative high part and an absolute low part. Since\r
+            // the absolute low part represents the offset into a 4 KB page, we\r
+            // have to make sure that the 4 KB relative offsets of both the\r
+            // section containing the reference as well as the section to which\r
+            // it refers have not been changed during PE/COFF conversion (i.e.,\r
+            // in ScanSections64() above).\r
+            //\r
+            if (((SecShdr->sh_addr ^ SecOffset) & 0xfff) != 0 ||\r
+                ((SymShdr->sh_addr ^ mCoffSectionsOffset[Sym->st_shndx]) & 0xfff) != 0 ||\r
+                mCoffAlignment < 0x1000) {\r
+              Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s AARCH64 small code model requires 4 KB section alignment.",\r
+                mInImageName);\r
+              break;\r
             }\r
-            break;\r
+            /* fall through */\r
 \r
+          case R_AARCH64_ADR_PREL_LO21:\r
           case R_AARCH64_CONDBR19:\r
-            if  (Rel->r_addend != 0 ) { /* TODO */\r
-              Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_CONDBR19 Need to fixup with addend!.");\r
-            }\r
-            break;\r
-\r
           case R_AARCH64_LD_PREL_LO19:\r
-            if  (Rel->r_addend != 0 ) { /* TODO */\r
-              Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_LD_PREL_LO19 Need to fixup with addend!.");\r
-            }\r
-            break;\r
-\r
           case R_AARCH64_CALL26:\r
           case R_AARCH64_JUMP26:\r
-            if  (Rel->r_addend != 0 ) {\r
-              // Some references to static functions sometime start at the base of .text + addend.\r
-              // It is safe to ignore these relocations because they patch a `BL` instructions that\r
-              // contains an offset from the instruction itself and there is only a single .text section.\r
-              // So we check if the symbol is a "section symbol"\r
-              if (ELF64_ST_TYPE (Sym->st_info) == STT_SECTION) {\r
-                break;\r
-              }\r
-              Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_JUMP26 Need to fixup with addend!.");\r
+            //\r
+            // The GCC toolchains (i.e., binutils) may corrupt section relative\r
+            // relocations when emitting relocation sections into fully linked\r
+            // binaries. More specifically, they tend to fail to take into\r
+            // account the fact that a '.rodata + XXX' relocation needs to have\r
+            // its addend recalculated once .rodata is merged into the .text\r
+            // section, and the relocation emitted into the .rela.text section.\r
+            //\r
+            // We cannot really recover from this loss of information, so the\r
+            // only workaround is to prevent having to recalculate any relative\r
+            // relocations at all, by using a linker script that ensures that\r
+            // the offset between the Place and the Symbol is the same in both\r
+            // the ELF and the PE/COFF versions of the binary.\r
+            //\r
+            if ((SymShdr->sh_addr - SecShdr->sh_addr) !=\r
+                (mCoffSectionsOffset[Sym->st_shndx] - SecOffset)) {\r
+              Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s AARCH64 relative relocations require identical ELF and PE/COFF section offsets",\r
+                mInImageName);\r
             }\r
             break;\r
 \r
-          case R_AARCH64_ADR_PREL_PG_HI21:\r
-            // TODO : AArch64 'small' memory model.\r
-            Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADR_PREL_PG_HI21.", mInImageName);\r
-            break;\r
-\r
-          case R_AARCH64_ADD_ABS_LO12_NC:\r
-            // TODO : AArch64 'small' memory model.\r
-            Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADD_ABS_LO12_NC.", mInImageName);\r
-            break;\r
-\r
           // Absolute relocations.\r
           case R_AARCH64_ABS64:\r
             *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];\r
@@ -851,7 +858,7 @@ WriteRelocations64 (
               Error (NULL, 0, 3000, "Invalid", "%s unsupported ELF EM_X86_64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));\r
             }\r
           } else if (mEhdr->e_machine == EM_AARCH64) {\r
-            // AArch64 GCC uses RELA relocation, so all relocations has to be fixed up. ARM32 uses REL.\r
+\r
             switch (ELF_R_TYPE(Rel->r_info)) {\r
             case R_AARCH64_ADR_PREL_LO21:\r
               break;\r
@@ -869,13 +876,12 @@ WriteRelocations64 (
               break;\r
 \r
             case R_AARCH64_ADR_PREL_PG_HI21:\r
-              // TODO : AArch64 'small' memory model.\r
-              Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADR_PREL_PG_HI21.", mInImageName);\r
-              break;\r
-\r
             case R_AARCH64_ADD_ABS_LO12_NC:\r
-              // TODO : AArch64 'small' memory model.\r
-              Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation R_AARCH64_ADD_ABS_LO12_NC.", mInImageName);\r
+            case R_AARCH64_LDST8_ABS_LO12_NC:\r
+            case R_AARCH64_LDST16_ABS_LO12_NC:\r
+            case R_AARCH64_LDST32_ABS_LO12_NC:\r
+            case R_AARCH64_LDST64_ABS_LO12_NC:\r
+            case R_AARCH64_LDST128_ABS_LO12_NC:\r
               break;\r
 \r
             case R_AARCH64_ABS64:\r