According to SD Host Controller 3.0 spec figure 3-10, we have to wait
1ms before checking DAT[3:0] in voltage switch proc
Cc: Hao Wu <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
\r
SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]);\r
\r
- gBS->Stall (1);\r
+ gBS->Stall (1000);\r
\r
SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r
if (((PresentState >> 20) & 0xF) != 0xF) {\r
\r
SdPeimHcInitClockFreq (Slot->SdHcBase);\r
\r
- MicroSecondDelay (1);\r
+ MicroSecondDelay (1000);\r
\r
SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r
if (((PresentState >> 20) & 0xF) != 0xF) {\r