IntelFsp2Pkg/FspSecCore: LoadMicrocodeDefault() failed with padding in FV.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3017

Platform microcode FV may have padding between each version of microcode
binary, and current FSP-T/LoadMicrocodeDefault() cannot handle this case
and return not_found unexpectedly.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Cosmo Lai <cosmo.lai@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 7934eab6d7ae59dc2c43b405327391d475abc08c..7fd3d6d84315746e6ff12c4fd818a8acb9f04d2a 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -307,10 +307,6 @@ AdvanceFixedSize:
    add   esi, dword  1024\r
 \r
 CheckAddress:\r
-   ; Is valid Microcode start point ?\r
-   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
-   jz    Done\r
-\r
    ; Check UPD header revision\r
    cmp    byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
    jae    Fsp22UpdHeader1\r
@@ -341,6 +337,10 @@ Fsp22UpdHeader1:
    jmp   CheckMainHeader\r
 \r
 LoadMicrocodeDefault4:\r
+   ; Is valid Microcode start point ?\r
+   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
+   jz    Done\r
+\r
 LoadCheck:\r
    ; Get the revision of the current microcode update loaded\r
    mov   ecx, MSR_IA32_BIOS_SIGN_ID\r