Find the highest exclusive >=4GB RAM address, or produce memory resource\r
descriptor HOBs for RAM entries that start at or above 4GB.\r
\r
- @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()\r
+ @param[out] MaxAddress If MaxAddress is NULL, then PlatformScanOrAdd64BitE820Ram()\r
produces memory resource descriptor HOBs for RAM\r
entries that start at or above 4GB.\r
\r
**/\r
STATIC\r
EFI_STATUS\r
-ScanOrAdd64BitE820Ram (\r
+PlatformScanOrAdd64BitE820Ram (\r
IN BOOLEAN AddHighHob,\r
OUT UINT64 *LowMemory OPTIONAL,\r
OUT UINT64 *MaxAddress OPTIONAL\r
return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE);\r
}\r
\r
- Status = ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL);\r
+ Status = PlatformScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL);\r
if ((Status == EFI_SUCCESS) && (LowerMemorySize > 0)) {\r
return (UINT32)LowerMemorySize;\r
}\r
\r
STATIC\r
UINT64\r
-GetSystemMemorySizeAbove4gb (\r
+PlatformGetSystemMemorySizeAbove4gb (\r
)\r
{\r
UINT32 Size;\r
**/\r
STATIC\r
UINT64\r
-GetFirstNonAddress (\r
+PlatformGetFirstNonAddress (\r
IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
FIRMWARE_CONFIG_ITEM FwCfgItem;\r
UINTN FwCfgSize;\r
UINT64 HotPlugMemoryEnd;\r
- RETURN_STATUS PcdStatus;\r
\r
//\r
// set FirstNonAddress to suppress incorrect compiler/analyzer warnings\r
// Otherwise, get the flat size of the memory above 4GB from the CMOS (which\r
// can only express a size smaller than 1TB), and add it to 4GB.\r
//\r
- Status = ScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress);\r
+ Status = PlatformScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress);\r
if (EFI_ERROR (Status)) {\r
- FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r
+ FirstNonAddress = BASE_4GB + PlatformGetSystemMemorySizeAbove4gb ();\r
}\r
\r
//\r
\r
#endif\r
\r
- //\r
- // Otherwise, in order to calculate the highest address plus one, we must\r
- // consider the 64-bit PCI host aperture too. Fetch the default size.\r
- //\r
- PlatformInfoHob->PcdPciMmio64Size = PcdGet64 (PcdPciMmio64Size);\r
-\r
//\r
// See if the user specified the number of megabytes for the 64-bit PCI host\r
// aperture. Accept an aperture size up to 16TB.\r
"%a: disabling 64-bit PCI host aperture\n",\r
__FUNCTION__\r
));\r
- PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
- ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
//\r
//\r
PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE (PlatformInfoHob->PcdPciMmio64Base, GetPowerOfTwo64 (PlatformInfoHob->PcdPciMmio64Size));\r
\r
- if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
- //\r
- // The core PciHostBridgeDxe driver will automatically add this range to\r
- // the GCD memory space map through our PciHostBridgeLib instance; here we\r
- // only need to set the PCDs.\r
- //\r
- PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base);\r
- ASSERT_RETURN_ERROR (PcdStatus);\r
- PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size);\r
- ASSERT_RETURN_ERROR (PcdStatus);\r
-\r
- DEBUG ((\r
- DEBUG_INFO,\r
- "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
- __FUNCTION__,\r
- PlatformInfoHob->PcdPciMmio64Base,\r
- PlatformInfoHob->PcdPciMmio64Size\r
- ));\r
- }\r
-\r
//\r
// The useful address space ends with the 64-bit PCI host aperture.\r
//\r
}\r
\r
/**\r
- Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r
+ Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.\r
**/\r
VOID\r
-AddressWidthInitialization (\r
+EFIAPI\r
+PlatformAddressWidthInitialization (\r
IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
// The DXL IPL keys off of the physical address bits advertized in the CPU\r
// HOB. To conserve memory, we calculate the minimum address width here.\r
//\r
- FirstNonAddress = GetFirstNonAddress (PlatformInfoHob);\r
+ FirstNonAddress = PlatformGetFirstNonAddress (PlatformInfoHob);\r
PhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r
\r
//\r
PlatformInfoHob->PhysMemAddressWidth = PhysMemAddressWidth;\r
}\r
\r
+/**\r
+ Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.\r
+**/\r
+VOID\r
+AddressWidthInitialization (\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
+ )\r
+{\r
+ RETURN_STATUS PcdStatus;\r
+\r
+ PlatformAddressWidthInitialization (PlatformInfoHob);\r
+\r
+ //\r
+ // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r
+ // resources to 32-bit anyway. See DegradeResource() in\r
+ // "PciResourceSupport.c".\r
+ //\r
+ #ifdef MDE_CPU_IA32\r
+ if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
+ return;\r
+ }\r
+\r
+ #endif\r
+\r
+ if (PlatformInfoHob->PcdPciMmio64Size == 0) {\r
+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: disabling 64-bit PCI host aperture\n",\r
+ __FUNCTION__\r
+ ));\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ }\r
+\r
+ return;\r
+ }\r
+\r
+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
+ //\r
+ // The core PciHostBridgeDxe driver will automatically add this range to\r
+ // the GCD memory space map through our PciHostBridgeLib instance; here we\r
+ // only need to set the PCDs.\r
+ //\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
+ __FUNCTION__,\r
+ PlatformInfoHob->PcdPciMmio64Base,\r
+ PlatformInfoHob->PcdPciMmio64Size\r
+ ));\r
+ }\r
+}\r
+\r
/**\r
Calculate the cap for the permanent PEI memory.\r
**/\r
\r
//\r
// Add 64 MB for miscellaneous allocations. Note that for\r
- // mPhysMemAddressWidth values close to 36, the cap will actually be\r
+ // PhysMemAddressWidth values close to 36, the cap will actually be\r
// dominated by this increment.\r
//\r
return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
PeiMemoryCap = GetPeiMemoryCap ();\r
DEBUG ((\r
DEBUG_INFO,\r
- "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
+ "%a: PhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
__FUNCTION__,\r
mPlatformInfoHob.PhysMemAddressWidth,\r
PeiMemoryCap >> 10\r
// entries. Otherwise, create a single memory HOB with the flat >=4GB\r
// memory size read from the CMOS.\r
//\r
- Status = ScanOrAdd64BitE820Ram (TRUE, NULL, NULL);\r
+ Status = PlatformScanOrAdd64BitE820Ram (TRUE, NULL, NULL);\r
if (EFI_ERROR (Status)) {\r
- UpperMemorySize = GetSystemMemorySizeAbove4gb ();\r
+ UpperMemorySize = PlatformGetSystemMemorySizeAbove4gb ();\r
if (UpperMemorySize != 0) {\r
PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r
}\r