ArmPkg: Minor coding style changes

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11993 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/CpuPei/CpuPei.c b/ArmPkg/Drivers/CpuPei/CpuPei.c
index 0a97745fa3a67d2cbe33a5bc804ade262ab00319..bc01f306b928308e583480b3f98cc1cfe9316588 100755 (executable)
--- a/ArmPkg/Drivers/CpuPei/CpuPei.c
+++ b/ArmPkg/Drivers/CpuPei/CpuPei.c
@@ -47,7 +47,7 @@ Abstract:
 #define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
 \r
 EFI_STATUS\r
-FindMainMemory(\r
+FindMainMemory (\r
   OUT UINT32    *PhysicalBase,\r
   OUT UINT32    *Length\r
   )\r
@@ -71,7 +71,9 @@ FindMainMemory(
 }\r
 \r
 VOID\r
-ConfigureMmu ( VOID )\r
+ConfigureMmu (\r
+  VOID\r
+  )\r
 {\r
   EFI_STATUS                 Status;\r
   UINTN                         Idx;\r

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
index 526af02d3ee23caa829f99545eff9beeea7dbf05..c2089fe8466c034c80ab63a01632b56c9cec0038 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
@@ -12,6 +12,7 @@
 *\r
 **/\r
 \r
+#include <Uefi.h>\r
 #include <Library/IoLib.h>\r
 #include <Drivers/PL390Gic.h>\r
 \r
@@ -23,10 +24,10 @@ PL390GicEnableInterruptInterface (
   )\r
 {  \r
   /*\r
-   * Enable the CPU interface in Non-Secure world\r
-   * Note: The ICCICR register is banked when Security extensions are implemented   \r
-   */\r
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);\r
+  * Enable the CPU interface in Non-Secure world\r
+  * Note: The ICCICR register is banked when Security extensions are implemented\r
+  */\r
+  MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);\r
 }\r
 \r
 VOID\r
@@ -35,11 +36,11 @@ PL390GicEnableDistributor (
   IN  INTN          GicDistributorBase\r
   )\r
 {\r
-    /*\r
-     * Enable GIC distributor in Non-Secure world.\r
-     * Note: The ICDDCR register is banked when Security extensions are implemented\r
-     */\r
-    MmioWrite32(GicDistributorBase + GIC_ICDDCR, 0x00000001);\r
+  /*\r
+   * Enable GIC distributor in Non-Secure world.\r
+   * Note: The ICDDCR register is banked when Security extensions are implemented\r
+   */\r
+  MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001);\r
 }\r
 \r
 VOID\r
@@ -50,7 +51,7 @@ PL390GicSendSgiTo (
   IN  INTN          CPUTargetList\r
   )\r
 {\r
-  MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
+  MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
 }\r
 \r
 UINT32\r
@@ -60,18 +61,18 @@ PL390GicAcknowledgeSgiFrom (
   IN  INTN          CoreId\r
   )\r
 {\r
-    INTN            InterruptId;\r
+  INTN            InterruptId;\r
 \r
-    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+  InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR);\r
 \r
-    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
+  // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
   if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
-      //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
-        return 1;\r
-    } else {\r
-        return 0;\r
-    }\r
+    // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+    MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+    return 1;\r
+  } else {\r
+    return 0;\r
+  }\r
 }\r
 \r
 UINT32\r
@@ -82,16 +83,16 @@ PL390GicAcknowledgeSgi2From (
   IN  INTN          SgiId\r
   )\r
 {\r
-    INTN            InterruptId;\r
+  INTN            InterruptId;\r
 \r
-    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+  InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
 \r
-    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
+  // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
   if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
-      //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
-        return 1;\r
-    } else {\r
-        return 0;\r
-    }\r
+    // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+    MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+    return 1;\r
+  } else {\r
+    return 0;\r
+  }\r
 }\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
index c847d89ecac9eb9976e89b4642e4302d832eb2ad..17afbaf3b53ec71300188aa34a5e54f0843ec817 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
@@ -42,6 +42,7 @@
   MdePkg/MdePkg.dec\r
 \r
 [LibraryClasses]\r
+  IoLib\r
   MemoryAllocationLib\r
 \r
 [Protocols]\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf
index e1de26f426cb7aab2bbff7603dbfc8d3393eb356..09c16db42afd422519ee667742f2f8447e3a3b8c 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf
@@ -40,6 +40,7 @@
   MdePkg/MdePkg.dec\r
 \r
 [LibraryClasses]\r
+  IoLib\r
   PrePiLib\r
   \r
 [Protocols]\r

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
index 05c8d362f15f5464420a732aa05b569b54753f3d..d3afed0affe95f3c0df2d98bfc91102aeb63e4aa 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
@@ -36,6 +36,9 @@
   ArmPkg/ArmPkg.dec\r
   MdePkg/MdePkg.dec\r
 \r
+[LibraryClasses]\r
+  IoLib\r
+\r
 [Protocols]\r
   gEfiCpuArchProtocolGuid\r
 \r