MdePkg/BaseLib: Add support for the XSETBV instruction

*v2: refine the coding format.

https://bugzilla.tianocore.org/show_bug.cgi?id=3284

This patch is to support XSETBV instruction so as to support
Extended Control Register(XCR) write.

Extended Control Register(XCR) read has already been supported
by below commit to support XGETBV instruction:
9b3ca509abd4e45439bbdfe2c2fa8780c950320a

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ni Ray <ray.ni@intel.com>
Cc: Yao Jiewen <jiewen.yao@intel.com>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 1171a0ffb51b37fee353d41ac4366790b4e3c7d8..7253997a6f8c36fd69c73dd9fa5f9808495c7e36 100644 (file)
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -2,7 +2,7 @@
   Provides string functions, linked list functions, math functions, synchronization\r
   functions, file path functions, and CPU architecture-specific functions.\r
 \r
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 Copyright (c) Microsoft Corporation.<BR>\r
 Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
@@ -7438,6 +7438,29 @@ AsmXGetBv (
   IN UINT32  Index\r
   );\r
 \r
+/**\r
+  Executes a XSETBV instruction to write a 64-bit value to a Extended Control\r
+  Register(XCR), and returns the value.\r
+\r
+  Writes the 64-bit value specified by Value to the XCR specified by Index. The\r
+  64-bit value written to the XCR is returned. No parameter checking is\r
+  performed on Index or Value, and some of these may cause CPU exceptions. The\r
+  caller must either guarantee that Index and Value are valid, or the caller\r
+  must establish proper exception handlers. This function is only available on\r
+  IA-32 and x64.\r
+\r
+  @param  Index The 32-bit XCR index to write.\r
+  @param  Value The 64-bit value to write to the XCR.\r
+\r
+  @return Value\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmXSetBv (\r
+  IN UINT32  Index,\r
+  IN UINT64  Value\r
+  );\r
 \r
 /**\r
   Executes a VMGEXIT instruction (VMMCALL with a REP prefix)\r

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 3b85c56c3c0398863de99ec4d22a09a3da0eb67d..fe8f68bbcfcf7ca9659acd5623496030f48486bc 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -1,7 +1,7 @@
 ## @file\r
 #  Base Library implementation.\r
 #\r
-#  Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>\r
+#  Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
 #  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 #  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
 #  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
@@ -184,6 +184,7 @@
   Ia32/DisableCache.nasm| GCC\r
   Ia32/RdRand.nasm\r
   Ia32/XGetBv.nasm\r
+  Ia32/XSetBv.nasm\r
   Ia32/VmgExit.nasm\r
 \r
   Ia32/DivS64x64Remainder.c\r
@@ -318,6 +319,7 @@
   X64/DisablePaging64.nasm\r
   X64/RdRand.nasm\r
   X64/XGetBv.nasm\r
+  X64/XSetBv.nasm\r
   X64/VmgExit.nasm\r
   ChkStkGcc.c  | GCC\r
 \r

diff --git a/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm b/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm
new file mode 100644 (file)
index 0000000..cf638d9
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+; Module Name:\r
+;\r
+;   XSetBv.nasm\r
+;\r
+; Abstract:\r
+;\r
+;   AsmXSetBv function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmXSetBv (\r
+;   IN UINT32  Index,\r
+;   IN UINT64  Value\r
+;   );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(AsmXSetBv)\r
+ASM_PFX(AsmXSetBv):\r
+    mov     edx, [esp + 12]\r
+    mov     eax, [esp + 8]\r
+    mov     ecx, [esp + 4]\r
+    xsetbv\r
+    ret\r

diff --git a/MdePkg/Library/BaseLib/X64/XSetBv.nasm b/MdePkg/Library/BaseLib/X64/XSetBv.nasm
new file mode 100644 (file)
index 0000000..c07e9b4
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/XSetBv.nasm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+; Module Name:\r
+;\r
+;   XSetBv.nasm\r
+;\r
+; Abstract:\r
+;\r
+;   AsmXSetBv function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    DEFAULT REL\r
+    SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmXSetBv (\r
+;   IN UINT32  Index,\r
+;   IN UINT64  Value\r
+;   );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(AsmXSetBv)\r
+ASM_PFX(AsmXSetBv):\r
+    mov     rax, rdx                    ; meanwhile, rax <- return value\r
+    shr     rdx, 0x20                    ; edx:eax contains the value to write\r
+    xsetbv\r
+    ret\r