REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1119
Today's implementation reports CPU address size as 36 through CPU
HOB. But when WinHost is running at 64bit, the system memory might
be allocated above 2^36.
It causes system asserts when DxeCore code tries to find the
corresponding GCD entry for a given valid address.
The patch uses 57 as the CPU address size which is maximum linear
address size when 5-level paging is enabled in host OS.
Using 64 seems more proper and a one-time change even 6-level
paging might be invented. But it causes CoreInitializeGcdServices()
assertion on following code:
Entry->EndAddress = LShiftU64 (1, SizeOfMemorySpace) - 1;
Because LShiftU64 expects SizeOfMemorySpace < 64.
So to be practical, I didn't report 64 and change
CoreInitializeGcdServices().
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Cc: Andrew Fish <afish@apple.com>
/*++ @file\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
Portions copyright (c) 2011, Apple Inc. All rights reserved.\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
} while (!EFI_ERROR (Status));\r
\r
//\r
- // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
+ // Build the CPU hob with 57-bit addressing and 16-bits of IO space.\r
//\r
- BuildCpuHob (36, 16);\r
+ BuildCpuHob (57, 16);\r
\r
return Status;\r
}\r