# it has been configured by the CPU DXE\r
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
\r
- # Define if the spin-table mechanism is used by the secondary cores when booting\r
- # Linux (instead of PSCI)\r
- gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033\r
-\r
# Define if the GICv3 controller should use the GICv2 legacy\r
gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
\r
# By default we do not do a transition to non-secure mode\r
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
\r
- # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
- gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
-\r
- # If the fixed FDT address is not available, then it should be loaded below the kernel.\r
- # The recommendation from the Linux kernel is to have the FDT below 16KB.\r
- # (see the kernel doc: Documentation/arm/Booting)\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023\r
- # The FDT blob must be loaded at a 64bit aligned address.\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026\r
-\r
# Non Secure Access Control Register\r
# - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
# - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
# Other modes include using SP0 or switching to Aarch32, but these are\r
# not currently supported.\r
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
- # If the fixed FDT address is not available, then it should be loaded above the kernel.\r
- # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.\r
- # (see the kernel doc: Documentation/arm64/booting.txt)\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023\r
- # The FDT blob must be loaded at a 2MB aligned address.\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r
\r
\r
#\r