--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Shifts a 64-bit integer right between 0 and 63 bits. The high bits are filled\r
+ with the original integer's bit 63. The shifted value is returned.\r
+\r
+ This function shifts the 64-bit value Operand to the right by Count bits. The\r
+ high Count bits are set to bit 63 of Operand. The shifted value is returned.\r
+\r
+ If Count is greater than 63, then ASSERT().\r
+\r
+ @param Operand The 64-bit operand to shift right.\r
+ @param Count The number of bits to shift right.\r
+\r
+ @return Operand >> Count\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+ARShiftU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ ASSERT (Count < 64);\r
+ return InternalMathARShiftU64 (Operand, Count);\r
+}\r
--- /dev/null
+/** @file\r
+ Declaration of internal functions in BaseLib.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __BASE_LIB_INTERNALS__\r
+#define __BASE_LIB_INTERNALS__\r
+\r
+#include <Base.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+//\r
+// Math functions\r
+//\r
+\r
+/**\r
+ Shifts a 64-bit integer left between 0 and 63 bits. The low bits\r
+ are filled with zeros. The shifted value is returned.\r
+\r
+ This function shifts the 64-bit value Operand to the left by Count bits. The\r
+ low Count bits are set to zero. The shifted value is returned.\r
+\r
+ @param Operand The 64-bit operand to shift left.\r
+ @param Count The number of bits to shift left.\r
+\r
+ @return Operand << Count\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathLShiftU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ );\r
+\r
+/**\r
+ Shifts a 64-bit integer right between 0 and 63 bits. The high bits\r
+ are filled with zeros. The shifted value is returned.\r
+\r
+ This function shifts the 64-bit value Operand to the right by Count bits. The\r
+ high Count bits are set to zero. The shifted value is returned.\r
+\r
+ @param Operand The 64-bit operand to shift right.\r
+ @param Count The number of bits to shift right.\r
+\r
+ @return Operand >> Count\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathRShiftU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ );\r
+\r
+/**\r
+ Shifts a 64-bit integer right between 0 and 63 bits. The high bits\r
+ are filled with original integer's bit 63. The shifted value is returned.\r
+\r
+ This function shifts the 64-bit value Operand to the right by Count bits. The\r
+ high Count bits are set to bit 63 of Operand. The shifted value is returned.\r
+\r
+ @param Operand The 64-bit operand to shift right.\r
+ @param Count The number of bits to shift right.\r
+\r
+ @return Operand arithmetically shifted right by Count\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathARShiftU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ );\r
+\r
+/**\r
+ Rotates a 64-bit integer left between 0 and 63 bits, filling\r
+ the low bits with the high bits that were rotated.\r
+\r
+ This function rotates the 64-bit value Operand to the left by Count bits. The\r
+ low Count bits are filled with the high Count bits of Operand. The rotated\r
+ value is returned.\r
+\r
+ @param Operand The 64-bit operand to rotate left.\r
+ @param Count The number of bits to rotate left.\r
+\r
+ @return Operand <<< Count\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathLRotU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ );\r
+\r
+/**\r
+ Rotates a 64-bit integer right between 0 and 63 bits, filling\r
+ the high bits with the high low bits that were rotated.\r
+\r
+ This function rotates the 64-bit value Operand to the right by Count bits.\r
+ The high Count bits are filled with the low Count bits of Operand. The rotated\r
+ value is returned.\r
+\r
+ @param Operand The 64-bit operand to rotate right.\r
+ @param Count The number of bits to rotate right.\r
+\r
+ @return Operand >>> Count\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathRRotU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ );\r
+\r
+/**\r
+ Switches the endianess of a 64-bit integer.\r
+\r
+ This function swaps the bytes in a 64-bit unsigned value to switch the value\r
+ from little endian to big endian or vice versa. The byte swapped value is\r
+ returned.\r
+\r
+ @param Operand A 64-bit unsigned value.\r
+\r
+ @return The byte swapped Operand.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathSwapBytes64 (\r
+ IN UINT64 Operand\r
+ );\r
+\r
+/**\r
+ Multiplies a 64-bit unsigned integer by a 32-bit unsigned integer\r
+ and generates a 64-bit unsigned result.\r
+\r
+ This function multiplies the 64-bit unsigned value Multiplicand by the 32-bit\r
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-\r
+ bit unsigned result is returned.\r
+\r
+ @param Multiplicand A 64-bit unsigned value.\r
+ @param Multiplier A 32-bit unsigned value.\r
+\r
+ @return Multiplicand * Multiplier\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathMultU64x32 (\r
+ IN UINT64 Multiplicand,\r
+ IN UINT32 Multiplier\r
+ );\r
+\r
+/**\r
+ Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer\r
+ and generates a 64-bit unsigned result.\r
+\r
+ This function multiples the 64-bit unsigned value Multiplicand by the 64-bit\r
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-\r
+ bit unsigned result is returned.\r
+\r
+ @param Multiplicand A 64-bit unsigned value.\r
+ @param Multiplier A 64-bit unsigned value.\r
+\r
+ @return Multiplicand * Multiplier\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathMultU64x64 (\r
+ IN UINT64 Multiplicand,\r
+ IN UINT64 Multiplier\r
+ );\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and\r
+ generates a 64-bit unsigned result.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 32-bit\r
+ unsigned value Divisor and generates a 64-bit unsigned quotient. This\r
+ function returns the 64-bit unsigned quotient.\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 32-bit unsigned value.\r
+\r
+ @return Dividend / Divisor\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathDivU64x32 (\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
+ );\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and\r
+ generates a 32-bit unsigned remainder.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 32-bit\r
+ unsigned value Divisor and generates a 32-bit remainder. This function\r
+ returns the 32-bit unsigned remainder.\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 32-bit unsigned value.\r
+\r
+ @return Dividend % Divisor\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalMathModU64x32 (\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
+ );\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and\r
+ generates a 64-bit unsigned result and an optional 32-bit unsigned remainder.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 32-bit\r
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder\r
+ is not NULL, then the 32-bit unsigned remainder is returned in Remainder.\r
+ This function returns the 64-bit unsigned quotient.\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 32-bit unsigned value.\r
+ @param Remainder A pointer to a 32-bit unsigned value. This parameter is\r
+ optional and may be NULL.\r
+\r
+ @return Dividend / Divisor\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathDivRemU64x32 (\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor,\r
+ OUT UINT32 *Remainder OPTIONAL\r
+ );\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 64-bit unsigned integer and\r
+ generates a 64-bit unsigned result and an optional 64-bit unsigned remainder.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 64-bit\r
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder\r
+ is not NULL, then the 64-bit unsigned remainder is returned in Remainder.\r
+ This function returns the 64-bit unsigned quotient.\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 64-bit unsigned value.\r
+ @param Remainder A pointer to a 64-bit unsigned value. This parameter is\r
+ optional and may be NULL.\r
+\r
+ @return Dividend / Divisor\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathDivRemU64x64 (\r
+ IN UINT64 Dividend,\r
+ IN UINT64 Divisor,\r
+ OUT UINT64 *Remainder OPTIONAL\r
+ );\r
+\r
+/**\r
+ Divides a 64-bit signed integer by a 64-bit signed integer and\r
+ generates a 64-bit signed result and an optional 64-bit signed remainder.\r
+\r
+ This function divides the 64-bit signed value Dividend by the 64-bit\r
+ signed value Divisor and generates a 64-bit signed quotient. If Remainder\r
+ is not NULL, then the 64-bit signed remainder is returned in Remainder.\r
+ This function returns the 64-bit signed quotient.\r
+\r
+ @param Dividend A 64-bit signed value.\r
+ @param Divisor A 64-bit signed value.\r
+ @param Remainder A pointer to a 64-bit signed value. This parameter is\r
+ optional and may be NULL.\r
+\r
+ @return Dividend / Divisor\r
+\r
+**/\r
+INT64\r
+EFIAPI\r
+InternalMathDivRemS64x64 (\r
+ IN INT64 Dividend,\r
+ IN INT64 Divisor,\r
+ OUT INT64 *Remainder OPTIONAL\r
+ );\r
+\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the\r
+ new stack specified by NewStack and passing in the parameters specified\r
+ by Context1 and Context2. Context1 and Context2 are optional and may\r
+ be NULL. The function EntryPoint must never return.\r
+ Marker will be ignored on IA-32, x64, and EBC.\r
+ IPF CPUs expect one additional parameter of type VOID * that specifies\r
+ the new backing store pointer.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param Marker VA_LIST marker for the variable argument list.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalSwitchStack (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack,\r
+ IN VA_LIST Marker\r
+ );\r
+\r
+\r
+/**\r
+ Worker function that locates the Node in the List.\r
+\r
+ By searching the List, finds the location of the Node in List. At the same time,\r
+ verifies the validity of this list.\r
+\r
+ If List is NULL, then ASSERT().\r
+ If List->ForwardLink is NULL, then ASSERT().\r
+ If List->backLink is NULL, then ASSERT().\r
+ If Node is NULL, then ASSERT();\r
+ If PcdMaximumLinkedListLenth is not zero, and prior to insertion the number\r
+ of nodes in ListHead, including the ListHead node, is greater than or\r
+ equal to PcdMaximumLinkedListLength, then ASSERT().\r
+\r
+ @param List A pointer to a node in a linked list.\r
+ @param Node A pointer to one nod.\r
+\r
+ @retval TRUE Node is in List.\r
+ @retval FALSE Node isn't in List, or List is invalid.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+IsNodeInList (\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
+ );\r
+\r
+/**\r
+ Worker function that returns a bit field from Operand.\r
+\r
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+\r
+ @return The bit field read.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+BitFieldReadUint (\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ );\r
+\r
+\r
+/**\r
+ Worker function that reads a bit field from Operand, performs a bitwise OR,\r
+ and returns the result.\r
+\r
+ Performs a bitwise OR between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData. All other bits in Operand are\r
+ preserved. The new value is returned.\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ @param OrData The value to OR with the read value from the value\r
+\r
+ @return The new value.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+BitFieldOrUint (\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINTN OrData\r
+ );\r
+\r
+\r
+/**\r
+ Worker function that reads a bit field from Operand, performs a bitwise AND,\r
+ and returns the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData. All other bits in Operand are\r
+ preserved. The new value is returned.\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ @param AndData The value to And with the read value from the value\r
+\r
+ @return The new value.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+BitFieldAndUint (\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINTN AndData\r
+ );\r
+\r
+\r
+/**\r
+ Worker function that checks ASSERT condition for JumpBuffer\r
+\r
+ Checks ASSERT condition for JumpBuffer.\r
+\r
+ If JumpBuffer is NULL, then ASSERT().\r
+ For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+\r
+ @param JumpBuffer A pointer to CPU context buffer.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalAssertJumpBuffer (\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
+ );\r
+\r
+\r
+/**\r
+ Restores the CPU context that was saved with SetJump().\r
+\r
+ Restores the CPU context from the buffer specified by JumpBuffer.\r
+ This function never returns to the caller.\r
+ Instead is resumes execution based on the state of JumpBuffer.\r
+\r
+ @param JumpBuffer A pointer to CPU context buffer.\r
+ @param Value The value to return when the SetJump() context is restored.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalLongJump (\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
+ IN UINTN Value\r
+ );\r
+\r
+\r
+//\r
+// Ia32 and x64 specific functions\r
+//\r
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
+\r
+/**\r
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r
+ function is only available on IA-32 and x64.\r
+\r
+ @param Gdtr The pointer to a GDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86ReadGdtr (\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
+ );\r
+\r
+/**\r
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
+\r
+ Writes and the current GDTR descriptor specified by Gdtr. This function is\r
+ only available on IA-32 and x64.\r
+\r
+ @param Gdtr The pointer to a GDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86WriteGdtr (\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
+ );\r
+\r
+/**\r
+ Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This\r
+ function is only available on IA-32 and x64.\r
+\r
+ @param Idtr The pointer to an IDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86ReadIdtr (\r
+ OUT IA32_DESCRIPTOR *Idtr\r
+ );\r
+\r
+/**\r
+ Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Writes the current IDTR descriptor and returns it in Idtr. This function is\r
+ only available on IA-32 and x64.\r
+\r
+ @param Idtr The pointer to an IDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86WriteIdtr (\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
+ );\r
+\r
+/**\r
+ Save the current floating point/SSE/SSE2 context to a buffer.\r
+\r
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by\r
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only\r
+ available on IA-32 and x64.\r
+\r
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86FxSave (\r
+ OUT IA32_FX_BUFFER *Buffer\r
+ );\r
+\r
+/**\r
+ Restores the current floating point/SSE/SSE2 context from a buffer.\r
+\r
+ Restores the current floating point/SSE/SSE2 state from the buffer specified\r
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is\r
+ only available on IA-32 and x64.\r
+\r
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86FxRestore (\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
+ );\r
+\r
+/**\r
+ Enables the 32-bit paging mode on the CPU.\r
+\r
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r
+ must be properly initialized prior to calling this service. This function\r
+ assumes the current execution mode is 32-bit protected mode. This function is\r
+ only available on IA-32. After the 32-bit paging mode is enabled, control is\r
+ transferred to the function specified by EntryPoint using the new stack\r
+ specified by NewStack and passing in the parameters specified by Context1 and\r
+ Context2. Context1 and Context2 are optional and may be NULL. The function\r
+ EntryPoint must never return.\r
+\r
+ There are a number of constraints that must be followed before calling this\r
+ function:\r
+ 1) Interrupts must be disabled.\r
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This\r
+ means all descriptors must have a base of 0 and a limit of 4GB.\r
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat\r
+ descriptors.\r
+ 4) CR3 must point to valid page tables that will be used once the transition\r
+ is complete, and those page tables must guarantee that the pages for this\r
+ function and the stack are identity mapped.\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack after\r
+ paging is enabled.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function as the first parameter after paging is enabled.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function as the second parameter after paging is enabled.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function after paging is enabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86EnablePaging32 (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack\r
+ );\r
+\r
+/**\r
+ Disables the 32-bit paging mode on the CPU.\r
+\r
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected\r
+ mode. This function assumes the current execution mode is 32-paged protected\r
+ mode. This function is only available on IA-32. After the 32-bit paging mode\r
+ is disabled, control is transferred to the function specified by EntryPoint\r
+ using the new stack specified by NewStack and passing in the parameters\r
+ specified by Context1 and Context2. Context1 and Context2 are optional and\r
+ may be NULL. The function EntryPoint must never return.\r
+\r
+ There are a number of constraints that must be followed before calling this\r
+ function:\r
+ 1) Interrupts must be disabled.\r
+ 2) The caller must be in 32-bit paged mode.\r
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.\r
+ 4) CR3 must point to valid page tables that guarantee that the pages for\r
+ this function and the stack are identity mapped.\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack after\r
+ paging is disabled.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function as the first parameter after paging is disabled.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function as the second parameter after paging is\r
+ disabled.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function after paging is disabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86DisablePaging32 (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack\r
+ );\r
+\r
+/**\r
+ Enables the 64-bit paging mode on the CPU.\r
+\r
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r
+ must be properly initialized prior to calling this service. This function\r
+ assumes the current execution mode is 32-bit protected mode with flat\r
+ descriptors. This function is only available on IA-32. After the 64-bit\r
+ paging mode is enabled, control is transferred to the function specified by\r
+ EntryPoint using the new stack specified by NewStack and passing in the\r
+ parameters specified by Context1 and Context2. Context1 and Context2 are\r
+ optional and may be 0. The function EntryPoint must never return.\r
+\r
+ @param Cs The 16-bit selector to load in the CS before EntryPoint\r
+ is called. The descriptor in the GDT that this selector\r
+ references must be setup for long mode.\r
+ @param EntryPoint The 64-bit virtual address of the function to call with\r
+ the new stack after paging is enabled.\r
+ @param Context1 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the first parameter after\r
+ paging is enabled.\r
+ @param Context2 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the second parameter after\r
+ paging is enabled.\r
+ @param NewStack The 64-bit virtual address of the new stack to use for\r
+ the EntryPoint function after paging is enabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86EnablePaging64 (\r
+ IN UINT16 Cs,\r
+ IN UINT64 EntryPoint,\r
+ IN UINT64 Context1, OPTIONAL\r
+ IN UINT64 Context2, OPTIONAL\r
+ IN UINT64 NewStack\r
+ );\r
+\r
+/**\r
+ Disables the 64-bit paging mode on the CPU.\r
+\r
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r
+ mode. This function assumes the current execution mode is 64-paging mode.\r
+ This function is only available on x64. After the 64-bit paging mode is\r
+ disabled, control is transferred to the function specified by EntryPoint\r
+ using the new stack specified by NewStack and passing in the parameters\r
+ specified by Context1 and Context2. Context1 and Context2 are optional and\r
+ may be 0. The function EntryPoint must never return.\r
+\r
+ @param Cs The 16-bit selector to load in the CS before EntryPoint\r
+ is called. The descriptor in the GDT that this selector\r
+ references must be setup for 32-bit protected mode.\r
+ @param EntryPoint The 64-bit virtual address of the function to call with\r
+ the new stack after paging is disabled.\r
+ @param Context1 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the first parameter after\r
+ paging is disabled.\r
+ @param Context2 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the second parameter after\r
+ paging is disabled.\r
+ @param NewStack The 64-bit virtual address of the new stack to use for\r
+ the EntryPoint function after paging is disabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86DisablePaging64 (\r
+ IN UINT16 Cs,\r
+ IN UINT32 EntryPoint,\r
+ IN UINT32 Context1, OPTIONAL\r
+ IN UINT32 Context2, OPTIONAL\r
+ IN UINT32 NewStack\r
+ );\r
+\r
+\r
+#elif defined (MDE_CPU_IPF)\r
+//\r
+//\r
+// IPF specific functions\r
+//\r
+\r
+/**\r
+ Reads control register DCR.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_DCR.\r
+\r
+ @return The 64-bit control register DCR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterDcr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register ITM.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_ITM.\r
+\r
+ @return The 64-bit control register ITM.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterItm (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IVA.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IVA.\r
+\r
+ @return The 64-bit control register IVA.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIva (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register PTA.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_PTA.\r
+\r
+ @return The 64-bit control register PTA.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterPta (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IPSR.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IPSR.\r
+\r
+ @return The 64-bit control register IPSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIpsr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register ISR.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_ISR.\r
+\r
+ @return The 64-bit control register ISR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIsr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IIP.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IIP.\r
+\r
+ @return The 64-bit control register IIP.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIip (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IFA.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IFA.\r
+\r
+ @return The 64-bit control register IFA.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIfa (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register ITIR.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_ITIR.\r
+\r
+ @return The 64-bit control register ITIR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterItir (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IIPA.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IIPA.\r
+\r
+ @return The 64-bit control register IIPA.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIipa (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IFS.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IFS.\r
+\r
+ @return The 64-bit control register IFS.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIfs (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IIM.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IIM.\r
+\r
+ @return The 64-bit control register IIM.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIim (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IHA.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IHA.\r
+\r
+ @return The 64-bit control register IHA.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIha (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register LID.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_LID.\r
+\r
+ @return The 64-bit control register LID.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterLid (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IVR.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IVR.\r
+\r
+ @return The 64-bit control register IVR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIvr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register TPR.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_TPR.\r
+\r
+ @return The 64-bit control register TPR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterTpr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register EOI.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_EOI.\r
+\r
+ @return The 64-bit control register EOI.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterEoi (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IRR0.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IRR0.\r
+\r
+ @return The 64-bit control register IRR0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIrr0 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IRR1.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IRR1.\r
+\r
+ @return The 64-bit control register IRR1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIrr1 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IRR2.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IRR2.\r
+\r
+ @return The 64-bit control register IRR2.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIrr2 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register IRR3.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_IRR3.\r
+\r
+ @return The 64-bit control register IRR3.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterIrr3 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register ITV.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_ITV.\r
+\r
+ @return The 64-bit control register ITV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterItv (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register PMV.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_PMV.\r
+\r
+ @return The 64-bit control register PMV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterPmv (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register CMCV.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_CMCV.\r
+\r
+ @return The 64-bit control register CMCV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterCmcv (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register LRR0.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_LRR0.\r
+\r
+ @return The 64-bit control register LRR0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterLrr0 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads control register LRR1.\r
+\r
+ This is a worker function for AsmReadControlRegister()\r
+ when its parameter Index is IPF_CONTROL_REGISTER_LRR1.\r
+\r
+ @return The 64-bit control register LRR1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadControlRegisterLrr1 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register K0.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_K0.\r
+\r
+ @return The 64-bit application register K0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterK0 (\r
+ VOID\r
+ );\r
+\r
+\r
+\r
+/**\r
+ Reads application register K1.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_K1.\r
+\r
+ @return The 64-bit application register K1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterK1 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register K2.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_K2.\r
+\r
+ @return The 64-bit application register K2.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterK2 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register K3.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_K3.\r
+\r
+ @return The 64-bit application register K3.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterK3 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register K4.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_K4.\r
+\r
+ @return The 64-bit application register K4.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterK4 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register K5.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_K5.\r
+\r
+ @return The 64-bit application register K5.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterK5 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register K6.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_K6.\r
+\r
+ @return The 64-bit application register K6.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterK6 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register K7.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_K7.\r
+\r
+ @return The 64-bit application register K7.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterK7 (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register RSC.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_RSC.\r
+\r
+ @return The 64-bit application register RSC.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterRsc (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register BSP.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_BSP.\r
+\r
+ @return The 64-bit application register BSP.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterBsp (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register BSPSTORE.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_BSPSTORE.\r
+\r
+ @return The 64-bit application register BSPSTORE.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterBspstore (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register RNAT.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_RNAT.\r
+\r
+ @return The 64-bit application register RNAT.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterRnat (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register FCR.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_FCR.\r
+\r
+ @return The 64-bit application register FCR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterFcr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register EFLAG.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_EFLAG.\r
+\r
+ @return The 64-bit application register EFLAG.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterEflag (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register CSD.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_CSD.\r
+\r
+ @return The 64-bit application register CSD.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterCsd (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register SSD.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_SSD.\r
+\r
+ @return The 64-bit application register SSD.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterSsd (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register CFLG.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_CFLG.\r
+\r
+ @return The 64-bit application register CFLG.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterCflg (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register FSR.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_FSR.\r
+\r
+ @return The 64-bit application register FSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterFsr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register FIR.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_FIR.\r
+\r
+ @return The 64-bit application register FIR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterFir (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register FDR.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_FDR.\r
+\r
+ @return The 64-bit application register FDR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterFdr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register CCV.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_CCV.\r
+\r
+ @return The 64-bit application register CCV.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterCcv (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register UNAT.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_UNAT.\r
+\r
+ @return The 64-bit application register UNAT.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterUnat (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register FPSR.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_FPSR.\r
+\r
+ @return The 64-bit application register FPSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterFpsr (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register ITC.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_ITC.\r
+\r
+ @return The 64-bit application register ITC.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterItc (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register PFS.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_PFS.\r
+\r
+ @return The 64-bit application register PFS.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterPfs (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register LC.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_LC.\r
+\r
+ @return The 64-bit application register LC.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterLc (\r
+ VOID\r
+ );\r
+\r
+\r
+/**\r
+ Reads application register EC.\r
+\r
+ This is a worker function for AsmReadApplicationRegister()\r
+ when its parameter Index is IPF_APPLICATION_REGISTER_EC.\r
+\r
+ @return The 64-bit application register EC.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadApplicationRegisterEc (\r
+ VOID\r
+ );\r
+\r
+\r
+\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the new stack\r
+ specified by NewStack and passing in the parameters specified by Context1 and\r
+ Context2. Context1 and Context2 are optional and may be NULL. The function\r
+ EntryPoint must never return.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param NewBsp A pointer to the new memory location for RSE backing\r
+ store.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmSwitchStackAndBackingStore (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack,\r
+ IN VOID *NewBsp\r
+ );\r
+\r
+/**\r
+ Internal worker function to invalidate a range of instruction cache lines\r
+ in the cache coherency domain of the calling CPU.\r
+\r
+ Internal worker function to invalidate the instruction cache lines specified\r
+ by Address and Length. If Address is not aligned on a cache line boundary,\r
+ then entire instruction cache line containing Address is invalidated. If\r
+ Address + Length is not aligned on a cache line boundary, then the entire\r
+ instruction cache line containing Address + Length -1 is invalidated. This\r
+ function may choose to invalidate the entire instruction cache if that is more\r
+ efficient than invalidating the specified range. If Length is 0, the no instruction\r
+ cache lines are invalidated. Address is returned.\r
+ This function is only available on IPF.\r
+\r
+ @param Address The base address of the instruction cache lines to\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InternalFlushCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ );\r
+\r
+#else\r
+\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Bit field functions of BaseLib.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Worker function that returns a bit field from Operand.\r
+\r
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+\r
+ @return The bit field read.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+InternalBaseLibBitFieldReadUint (\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ //\r
+ // ~((UINTN)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]\r
+ // are 1's while bit[EndBit + 1] thru the most significant bit are 0's.\r
+ //\r
+ return (Operand & ~((UINTN)-2 << EndBit)) >> StartBit;\r
+}\r
+\r
+/**\r
+ Worker function that reads a bit field from Operand, performs a bitwise OR,\r
+ and returns the result.\r
+\r
+ Performs a bitwise OR between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData. All other bits in Operand are\r
+ preserved. The new value is returned.\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ @param OrData The value to OR with the read value from the value.\r
+\r
+ @return The new value.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+InternalBaseLibBitFieldOrUint (\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINTN OrData\r
+ )\r
+{\r
+ //\r
+ // ~((UINTN)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]\r
+ // are 1's while bit[EndBit + 1] thru the most significant bit are 0's.\r
+ //\r
+ return Operand | ((OrData << StartBit) & ~((UINTN) -2 << EndBit));\r
+}\r
+\r
+/**\r
+ Worker function that reads a bit field from Operand, performs a bitwise AND,\r
+ and returns the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData. All other bits in Operand are\r
+ preserved. The new value is returned.\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ @param AndData The value to And with the read value from the value.\r
+\r
+ @return The new value.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+InternalBaseLibBitFieldAndUint (\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINTN AndData\r
+ )\r
+{\r
+ //\r
+ // ~((UINTN)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]\r
+ // are 1's while bit[EndBit + 1] thru the most significant bit are 0's.\r
+ //\r
+ return Operand & ~((~AndData << StartBit) & ~((UINTN)-2 << EndBit));\r
+}\r
+\r
+/**\r
+ Returns a bit field from an 8-bit value.\r
+\r
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.\r
+\r
+ If 8-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+\r
+ @return The bit field read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+BitFieldRead8 (\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ ASSERT (EndBit < 8);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT8)InternalBaseLibBitFieldReadUint (Operand, StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to an 8-bit value, and returns the result.\r
+\r
+ Writes Value to the bit field specified by the StartBit and the EndBit in\r
+ Operand. All other bits in Operand are preserved. The new 8-bit value is\r
+ returned.\r
+\r
+ If 8-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The new 8-bit value.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+BitFieldWrite8 (\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ ASSERT (EndBit < 8);\r
+ ASSERT (StartBit <= EndBit);\r
+ return BitFieldAndThenOr8 (Operand, StartBit, EndBit, 0, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field from an 8-bit value, performs a bitwise OR, and returns the\r
+ result.\r
+\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
+ and EndBit in Operand and the value specified by OrData. All other bits in\r
+ Operand are preserved. The new 8-bit value is returned.\r
+\r
+ If 8-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param OrData The value to OR with the read value from the value.\r
+\r
+ @return The new 8-bit value.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+BitFieldOr8 (\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ ASSERT (EndBit < 8);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT8)InternalBaseLibBitFieldOrUint (Operand, StartBit, EndBit, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field from an 8-bit value, performs a bitwise AND, and returns\r
+ the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData. All other bits in Operand are\r
+ preserved. The new 8-bit value is returned.\r
+\r
+ If 8-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the read value from the value.\r
+\r
+ @return The new 8-bit value.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+BitFieldAnd8 (\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ ASSERT (EndBit < 8);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT8)InternalBaseLibBitFieldAndUint (Operand, StartBit, EndBit, AndData);\r
+}\r
+\r
+/**\r
+ Reads a bit field from an 8-bit value, performs a bitwise AND followed by a\r
+ bitwise OR, and returns the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
+ preserved. The new 8-bit value is returned.\r
+\r
+ If 8-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the read value from the value.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The new 8-bit value.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+BitFieldAndThenOr8 (\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ ASSERT (EndBit < 8);\r
+ ASSERT (StartBit <= EndBit);\r
+ return BitFieldOr8 (\r
+ BitFieldAnd8 (Operand, StartBit, EndBit, AndData),\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Returns a bit field from a 16-bit value.\r
+\r
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.\r
+\r
+ If 16-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+\r
+ @return The bit field read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+BitFieldRead16 (\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ ASSERT (EndBit < 16);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT16)InternalBaseLibBitFieldReadUint (Operand, StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a 16-bit value, and returns the result.\r
+\r
+ Writes Value to the bit field specified by the StartBit and the EndBit in\r
+ Operand. All other bits in Operand are preserved. The new 16-bit value is\r
+ returned.\r
+\r
+ If 16-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The new 16-bit value.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+BitFieldWrite16 (\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT (EndBit < 16);\r
+ ASSERT (StartBit <= EndBit);\r
+ return BitFieldAndThenOr16 (Operand, StartBit, EndBit, 0, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field from a 16-bit value, performs a bitwise OR, and returns the\r
+ result.\r
+\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
+ and EndBit in Operand and the value specified by OrData. All other bits in\r
+ Operand are preserved. The new 16-bit value is returned.\r
+\r
+ If 16-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param OrData The value to OR with the read value from the value.\r
+\r
+ @return The new 16-bit value.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+BitFieldOr16 (\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ ASSERT (EndBit < 16);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT16)InternalBaseLibBitFieldOrUint (Operand, StartBit, EndBit, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field from a 16-bit value, performs a bitwise AND, and returns\r
+ the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData. All other bits in Operand are\r
+ preserved. The new 16-bit value is returned.\r
+\r
+ If 16-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the read value from the value.\r
+\r
+ @return The new 16-bit value.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+BitFieldAnd16 (\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ ASSERT (EndBit < 16);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT16)InternalBaseLibBitFieldAndUint (Operand, StartBit, EndBit, AndData);\r
+}\r
+\r
+/**\r
+ Reads a bit field from a 16-bit value, performs a bitwise AND followed by a\r
+ bitwise OR, and returns the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
+ preserved. The new 16-bit value is returned.\r
+\r
+ If 16-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the read value from the value.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The new 16-bit value.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+BitFieldAndThenOr16 (\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ ASSERT (EndBit < 16);\r
+ ASSERT (StartBit <= EndBit);\r
+ return BitFieldOr16 (\r
+ BitFieldAnd16 (Operand, StartBit, EndBit, AndData),\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Returns a bit field from a 32-bit value.\r
+\r
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.\r
+\r
+ If 32-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+\r
+ @return The bit field read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+BitFieldRead32 (\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ ASSERT (EndBit < 32);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT32)InternalBaseLibBitFieldReadUint (Operand, StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a 32-bit value, and returns the result.\r
+\r
+ Writes Value to the bit field specified by the StartBit and the EndBit in\r
+ Operand. All other bits in Operand are preserved. The new 32-bit value is\r
+ returned.\r
+\r
+ If 32-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The new 32-bit value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+BitFieldWrite32 (\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT (EndBit < 32);\r
+ ASSERT (StartBit <= EndBit);\r
+ return BitFieldAndThenOr32 (Operand, StartBit, EndBit, 0, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field from a 32-bit value, performs a bitwise OR, and returns the\r
+ result.\r
+\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
+ and EndBit in Operand and the value specified by OrData. All other bits in\r
+ Operand are preserved. The new 32-bit value is returned.\r
+\r
+ If 32-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param OrData The value to OR with the read value from the value.\r
+\r
+ @return The new 32-bit value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+BitFieldOr32 (\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ ASSERT (EndBit < 32);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT32)InternalBaseLibBitFieldOrUint (Operand, StartBit, EndBit, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field from a 32-bit value, performs a bitwise AND, and returns\r
+ the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData. All other bits in Operand are\r
+ preserved. The new 32-bit value is returned.\r
+\r
+ If 32-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the read value from the value.\r
+\r
+ @return The new 32-bit value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+BitFieldAnd32 (\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ ASSERT (EndBit < 32);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT32)InternalBaseLibBitFieldAndUint (Operand, StartBit, EndBit, AndData);\r
+}\r
+\r
+/**\r
+ Reads a bit field from a 32-bit value, performs a bitwise AND followed by a\r
+ bitwise OR, and returns the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
+ preserved. The new 32-bit value is returned.\r
+\r
+ If 32-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the read value from the value.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The new 32-bit value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+BitFieldAndThenOr32 (\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ ASSERT (EndBit < 32);\r
+ ASSERT (StartBit <= EndBit);\r
+ return BitFieldOr32 (\r
+ BitFieldAnd32 (Operand, StartBit, EndBit, AndData),\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Returns a bit field from a 64-bit value.\r
+\r
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.\r
+\r
+ If 64-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+\r
+ @return The bit field read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+BitFieldRead64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ ASSERT (EndBit < 64);\r
+ ASSERT (StartBit <= EndBit);\r
+ return RShiftU64 (Operand & ~LShiftU64 ((UINT64)-2, EndBit), StartBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a 64-bit value, and returns the result.\r
+\r
+ Writes Value to the bit field specified by the StartBit and the EndBit in\r
+ Operand. All other bits in Operand are preserved. The new 64-bit value is\r
+ returned.\r
+\r
+ If 64-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The new 64-bit value.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+BitFieldWrite64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ ASSERT (EndBit < 64);\r
+ ASSERT (StartBit <= EndBit);\r
+ return BitFieldAndThenOr64 (Operand, StartBit, EndBit, 0, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the\r
+ result.\r
+\r
+ Performs a bitwise OR between the bit field specified by StartBit\r
+ and EndBit in Operand and the value specified by OrData. All other bits in\r
+ Operand are preserved. The new 64-bit value is returned.\r
+\r
+ If 64-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param OrData The value to OR with the read value from the value\r
+\r
+ @return The new 64-bit value.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+BitFieldOr64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ UINT64 Value1;\r
+ UINT64 Value2;\r
+\r
+ ASSERT (EndBit < 64);\r
+ ASSERT (StartBit <= EndBit);\r
+\r
+ Value1 = LShiftU64 (OrData, StartBit);\r
+ Value2 = LShiftU64 ((UINT64) - 2, EndBit);\r
+\r
+ return Operand | (Value1 & ~Value2);\r
+}\r
+\r
+/**\r
+ Reads a bit field from a 64-bit value, performs a bitwise AND, and returns\r
+ the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData. All other bits in Operand are\r
+ preserved. The new 64-bit value is returned.\r
+\r
+ If 64-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param AndData The value to AND with the read value from the value.\r
+\r
+ @return The new 64-bit value.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+BitFieldAnd64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
+ )\r
+{\r
+ UINT64 Value1;\r
+ UINT64 Value2;\r
+ \r
+ ASSERT (EndBit < 64);\r
+ ASSERT (StartBit <= EndBit);\r
+\r
+ Value1 = LShiftU64 (~AndData, StartBit);\r
+ Value2 = LShiftU64 ((UINT64)-2, EndBit);\r
+\r
+ return Operand & ~(Value1 & ~Value2);\r
+}\r
+\r
+/**\r
+ Reads a bit field from a 64-bit value, performs a bitwise AND followed by a\r
+ bitwise OR, and returns the result.\r
+\r
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit\r
+ in Operand and the value specified by AndData, followed by a bitwise \r
+ OR with value specified by OrData. All other bits in Operand are\r
+ preserved. The new 64-bit value is returned.\r
+\r
+ If 64-bit operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Operand Operand on which to perform the bitfield operation.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param AndData The value to AND with the read value from the value.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The new 64-bit value.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+BitFieldAndThenOr64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ ASSERT (EndBit < 64);\r
+ ASSERT (StartBit <= EndBit);\r
+ return BitFieldOr64 (\r
+ BitFieldAnd64 (Operand, StartBit, EndBit, AndData),\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
+}\r
--- /dev/null
+/** @file\r
+ Utility functions to generate checksum based on 2's complement\r
+ algorithm.\r
+\r
+ Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Returns the sum of all elements in a buffer in unit of UINT8.\r
+ During calculation, the carry bits are dropped.\r
+\r
+ This function calculates the sum of all elements in a buffer\r
+ in unit of UINT8. The carry bits in result of addition are dropped.\r
+ The result is returned as UINT8. If Length is Zero, then Zero is\r
+ returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the sum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Sum The sum of Buffer with carry bits dropped during additions.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+CalculateSum8 (\r
+ IN CONST UINT8 *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINT8 Sum;\r
+ UINTN Count;\r
+\r
+ ASSERT (Buffer != NULL);\r
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));\r
+\r
+ for (Sum = 0, Count = 0; Count < Length; Count++) {\r
+ Sum = (UINT8) (Sum + *(Buffer + Count));\r
+ }\r
+ \r
+ return Sum;\r
+}\r
+\r
+\r
+/**\r
+ Returns the two's complement checksum of all elements in a buffer\r
+ of 8-bit values.\r
+\r
+ This function first calculates the sum of the 8-bit values in the\r
+ buffer specified by Buffer and Length. The carry bits in the result\r
+ of addition are dropped. Then, the two's complement of the sum is\r
+ returned. If Length is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the checksum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Checksum The 2's complement checksum of Buffer.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+CalculateCheckSum8 (\r
+ IN CONST UINT8 *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINT8 CheckSum;\r
+\r
+ CheckSum = CalculateSum8 (Buffer, Length);\r
+\r
+ //\r
+ // Return the checksum based on 2's complement.\r
+ //\r
+ return (UINT8) (0x100 - CheckSum);\r
+}\r
+\r
+/**\r
+ Returns the sum of all elements in a buffer of 16-bit values. During\r
+ calculation, the carry bits are dropped.\r
+\r
+ This function calculates the sum of the 16-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in result of addition are dropped.\r
+ The 16-bit result is returned. If Length is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the sum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Sum The sum of Buffer with carry bits dropped during additions.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+CalculateSum16 (\r
+ IN CONST UINT16 *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINT16 Sum;\r
+ UINTN Count;\r
+ UINTN Total;\r
+\r
+ ASSERT (Buffer != NULL);\r
+ ASSERT (((UINTN) Buffer & 0x1) == 0);\r
+ ASSERT ((Length & 0x1) == 0);\r
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));\r
+\r
+ Total = Length / sizeof (*Buffer);\r
+ for (Sum = 0, Count = 0; Count < Total; Count++) {\r
+ Sum = (UINT16) (Sum + *(Buffer + Count));\r
+ }\r
+ \r
+ return Sum;\r
+}\r
+\r
+\r
+/**\r
+ Returns the two's complement checksum of all elements in a buffer of\r
+ 16-bit values.\r
+\r
+ This function first calculates the sum of the 16-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in the result of addition\r
+ are dropped. Then, the two's complement of the sum is returned. If Length\r
+ is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the checksum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Checksum The 2's complement checksum of Buffer.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+CalculateCheckSum16 (\r
+ IN CONST UINT16 *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINT16 CheckSum;\r
+\r
+ CheckSum = CalculateSum16 (Buffer, Length);\r
+\r
+ //\r
+ // Return the checksum based on 2's complement.\r
+ //\r
+ return (UINT16) (0x10000 - CheckSum);\r
+}\r
+\r
+\r
+/**\r
+ Returns the sum of all elements in a buffer of 32-bit values. During\r
+ calculation, the carry bits are dropped.\r
+\r
+ This function calculates the sum of the 32-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in result of addition are dropped.\r
+ The 32-bit result is returned. If Length is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 32-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the sum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Sum The sum of Buffer with carry bits dropped during additions.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+CalculateSum32 (\r
+ IN CONST UINT32 *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINT32 Sum;\r
+ UINTN Count;\r
+ UINTN Total;\r
+\r
+ ASSERT (Buffer != NULL);\r
+ ASSERT (((UINTN) Buffer & 0x3) == 0);\r
+ ASSERT ((Length & 0x3) == 0);\r
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));\r
+\r
+ Total = Length / sizeof (*Buffer);\r
+ for (Sum = 0, Count = 0; Count < Total; Count++) {\r
+ Sum = Sum + *(Buffer + Count);\r
+ }\r
+ \r
+ return Sum;\r
+}\r
+\r
+\r
+/**\r
+ Returns the two's complement checksum of all elements in a buffer of\r
+ 32-bit values.\r
+\r
+ This function first calculates the sum of the 32-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in the result of addition\r
+ are dropped. Then, the two's complement of the sum is returned. If Length\r
+ is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 32-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the checksum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Checksum The 2's complement checksum of Buffer.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+CalculateCheckSum32 (\r
+ IN CONST UINT32 *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINT32 CheckSum;\r
+\r
+ CheckSum = CalculateSum32 (Buffer, Length);\r
+\r
+ //\r
+ // Return the checksum based on 2's complement.\r
+ //\r
+ return (UINT32) ((UINT32)(-1) - CheckSum + 1);\r
+}\r
+\r
+\r
+/**\r
+ Returns the sum of all elements in a buffer of 64-bit values. During\r
+ calculation, the carry bits are dropped.\r
+\r
+ This function calculates the sum of the 64-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in result of addition are dropped.\r
+ The 64-bit result is returned. If Length is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 64-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the sum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Sum The sum of Buffer with carry bits dropped during additions.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+CalculateSum64 (\r
+ IN CONST UINT64 *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINT64 Sum;\r
+ UINTN Count;\r
+ UINTN Total;\r
+\r
+ ASSERT (Buffer != NULL);\r
+ ASSERT (((UINTN) Buffer & 0x7) == 0);\r
+ ASSERT ((Length & 0x7) == 0);\r
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));\r
+\r
+ Total = Length / sizeof (*Buffer);\r
+ for (Sum = 0, Count = 0; Count < Total; Count++) {\r
+ Sum = Sum + *(Buffer + Count);\r
+ }\r
+ \r
+ return Sum;\r
+}\r
+\r
+\r
+/**\r
+ Returns the two's complement checksum of all elements in a buffer of\r
+ 64-bit values.\r
+\r
+ This function first calculates the sum of the 64-bit values in the buffer\r
+ specified by Buffer and Length. The carry bits in the result of addition\r
+ are dropped. Then, the two's complement of the sum is returned. If Length\r
+ is 0, then 0 is returned.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().\r
+ If Length is not aligned on a 64-bit boundary, then ASSERT().\r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ @param Buffer The pointer to the buffer to carry out the checksum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Checksum The 2's complement checksum of Buffer.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+CalculateCheckSum64 (\r
+ IN CONST UINT64 *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINT64 CheckSum;\r
+\r
+ CheckSum = CalculateSum64 (Buffer, Length);\r
+\r
+ //\r
+ // Return the checksum based on 2's complement.\r
+ //\r
+ return (UINT64) ((UINT64)(-1) - CheckSum + 1);\r
+}\r
+\r
+\r
--- /dev/null
+/** @file\r
+ Provides hack function for passng GCC build.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Hack function for passing GCC build.\r
+**/\r
+VOID \r
+__chkstk() \r
+{\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ Base Library CPU Functions for all architectures.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+\r
+/**\r
+ Disables CPU interrupts and returns the interrupt state prior to the disable\r
+ operation.\r
+\r
+ @retval TRUE CPU interrupts were enabled on entry to this call.\r
+ @retval FALSE CPU interrupts were disabled on entry to this call.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SaveAndDisableInterrupts (\r
+ VOID\r
+ )\r
+{\r
+ BOOLEAN InterruptState;\r
+\r
+ InterruptState = GetInterruptState ();\r
+ DisableInterrupts ();\r
+ return InterruptState;\r
+}\r
+\r
+/**\r
+ Set the current CPU interrupt state.\r
+\r
+ Sets the current CPU interrupt state to the state specified by\r
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If\r
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is\r
+ returned.\r
+\r
+ @param InterruptState TRUE if interrupts should be enabled. FALSE if\r
+ interrupts should be disabled.\r
+\r
+ @return InterruptState\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SetInterruptState (\r
+ IN BOOLEAN InterruptState\r
+ )\r
+{\r
+ if (InterruptState) {\r
+ EnableInterrupts ();\r
+ } else {\r
+ DisableInterrupts ();\r
+ }\r
+ return InterruptState;\r
+}\r
--- /dev/null
+/** @file\r
+ Base Library CPU Functions for all architectures.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+#include <Base.h>\r
+#include <Library/BaseLib.h>\r
+\r
+/**\r
+ Executes an infinite loop.\r
+\r
+ Forces the CPU to execute an infinite loop. A debugger may be used to skip\r
+ past the loop and the code that follows the loop must execute properly. This\r
+ implies that the infinite loop must not cause the code that follow it to be\r
+ optimized away.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuDeadLoop (\r
+ VOID\r
+ )\r
+{\r
+ volatile UINTN Index;\r
+\r
+ for (Index = 0; Index == 0;);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Divides a 64-bit signed integer by a 64-bit signed integer and generates a\r
+ 64-bit signed result and a optional 64-bit signed remainder.\r
+\r
+ This function divides the 64-bit signed value Dividend by the 64-bit signed\r
+ value Divisor and generates a 64-bit signed quotient. If Remainder is not\r
+ NULL, then the 64-bit signed remainder is returned in Remainder. This\r
+ function returns the 64-bit signed quotient.\r
+\r
+ It is the caller's responsibility to not call this function with a Divisor of 0.\r
+ If Divisor is 0, then the quotient and remainder should be assumed to be \r
+ the largest negative integer.\r
+\r
+ If Divisor is 0, then ASSERT().\r
+\r
+ @param Dividend A 64-bit signed value.\r
+ @param Divisor A 64-bit signed value.\r
+ @param Remainder A pointer to a 64-bit signed value. This parameter is\r
+ optional and may be NULL.\r
+\r
+ @return Dividend / Divisor\r
+\r
+**/\r
+INT64\r
+EFIAPI\r
+DivS64x64Remainder (\r
+ IN INT64 Dividend,\r
+ IN INT64 Divisor,\r
+ OUT INT64 *Remainder OPTIONAL\r
+ )\r
+{\r
+ ASSERT (Divisor != 0);\r
+ return InternalMathDivRemS64x64 (Dividend, Divisor, Remainder);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates\r
+ a 64-bit unsigned result.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 32-bit\r
+ unsigned value Divisor and generates a 64-bit unsigned quotient. This\r
+ function returns the 64-bit unsigned quotient.\r
+\r
+ If Divisor is 0, then ASSERT().\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 32-bit unsigned value.\r
+\r
+ @return Dividend / Divisor\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+DivU64x32 (\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
+ )\r
+{\r
+ ASSERT (Divisor != 0);\r
+ return InternalMathDivU64x32 (Dividend, Divisor);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates\r
+ a 64-bit unsigned result and an optional 32-bit unsigned remainder.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 32-bit\r
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder\r
+ is not NULL, then the 32-bit unsigned remainder is returned in Remainder.\r
+ This function returns the 64-bit unsigned quotient.\r
+\r
+ If Divisor is 0, then ASSERT().\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 32-bit unsigned value.\r
+ @param Remainder A pointer to a 32-bit unsigned value. This parameter is\r
+ optional and may be NULL.\r
+\r
+ @return Dividend / Divisor\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+DivU64x32Remainder (\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor,\r
+ OUT UINT32 *Remainder OPTIONAL\r
+ )\r
+{\r
+ ASSERT (Divisor != 0);\r
+ return InternalMathDivRemU64x32 (Dividend, Divisor, Remainder);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 64-bit unsigned integer and generates\r
+ a 64-bit unsigned result and an optional 64-bit unsigned remainder.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 64-bit\r
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder\r
+ is not NULL, then the 64-bit unsigned remainder is returned in Remainder.\r
+ This function returns the 64-bit unsigned quotient.\r
+\r
+ If Divisor is 0, then ASSERT().\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 64-bit unsigned value.\r
+ @param Remainder A pointer to a 64-bit unsigned value. This parameter is\r
+ optional and may be NULL.\r
+\r
+ @return Dividend / Divisor\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+DivU64x64Remainder (\r
+ IN UINT64 Dividend,\r
+ IN UINT64 Divisor,\r
+ OUT UINT64 *Remainder OPTIONAL\r
+ )\r
+{\r
+ ASSERT (Divisor != 0);\r
+ return InternalMathDivRemU64x64 (Dividend, Divisor, Remainder);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Returns the value of the highest bit set in a 32-bit value. Equivalent to\r
+ 1 << log2(x).\r
+\r
+ This function computes the value of the highest bit set in the 32-bit value\r
+ specified by Operand. If Operand is zero, then zero is returned.\r
+\r
+ @param Operand The 32-bit operand to evaluate.\r
+\r
+ @return 1 << HighBitSet32(Operand)\r
+ @retval 0 Operand is zero.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+GetPowerOfTwo32 (\r
+ IN UINT32 Operand\r
+ )\r
+{\r
+ if (0 == Operand) {\r
+ return 0;\r
+ }\r
+\r
+ return 1ul << HighBitSet32 (Operand);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Returns the value of the highest bit set in a 64-bit value. Equivalent to\r
+ 1 << log2(x).\r
+\r
+ This function computes the value of the highest bit set in the 64-bit value\r
+ specified by Operand. If Operand is zero, then zero is returned.\r
+\r
+ @param Operand The 64-bit operand to evaluate.\r
+\r
+ @return 1 << HighBitSet64(Operand)\r
+ @retval 0 Operand is zero.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+GetPowerOfTwo64 (\r
+ IN UINT64 Operand\r
+ )\r
+{\r
+ if (Operand == 0) {\r
+ return 0;\r
+ }\r
+\r
+ return LShiftU64 (1, HighBitSet64 (Operand));\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Returns the bit position of the highest bit set in a 32-bit value. Equivalent\r
+ to log2(x).\r
+\r
+ This function computes the bit position of the highest bit set in the 32-bit\r
+ value specified by Operand. If Operand is zero, then -1 is returned.\r
+ Otherwise, a value between 0 and 31 is returned.\r
+\r
+ @param Operand The 32-bit operand to evaluate.\r
+\r
+ @retval 0..31 Position of the highest bit set in Operand if found.\r
+ @retval -1 Operand is zero.\r
+\r
+**/\r
+INTN\r
+EFIAPI\r
+HighBitSet32 (\r
+ IN UINT32 Operand\r
+ )\r
+{\r
+ INTN BitIndex;\r
+\r
+ if (Operand == 0) {\r
+ return - 1;\r
+ }\r
+ for (BitIndex = 31; (INT32)Operand > 0; BitIndex--, Operand <<= 1);\r
+ return BitIndex;\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Returns the bit position of the highest bit set in a 64-bit value. Equivalent\r
+ to log2(x).\r
+\r
+ This function computes the bit position of the highest bit set in the 64-bit\r
+ value specified by Operand. If Operand is zero, then -1 is returned.\r
+ Otherwise, a value between 0 and 63 is returned.\r
+\r
+ @param Operand The 64-bit operand to evaluate.\r
+\r
+ @retval 0..63 Position of the highest bit set in Operand if found.\r
+ @retval -1 Operand is zero.\r
+\r
+**/\r
+INTN\r
+EFIAPI\r
+HighBitSet64 (\r
+ IN UINT64 Operand\r
+ )\r
+{\r
+ if (Operand == (UINT32)Operand) {\r
+ //\r
+ // Operand is just a 32-bit integer\r
+ //\r
+ return HighBitSet32 ((UINT32)Operand);\r
+ }\r
+\r
+ //\r
+ // Operand is really a 64-bit integer\r
+ //\r
+ if (sizeof (UINTN) == sizeof (UINT32)) {\r
+ return HighBitSet32 (((UINT32*)&Operand)[1]) + 32;\r
+ } else {\r
+ return HighBitSet32 ((UINT32)RShiftU64 (Operand, 32)) + 32;\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Rotates a 32-bit integer left between 0 and 31 bits, filling the low bits\r
+ with the high bits that were rotated.\r
+\r
+ This function rotates the 32-bit value Operand to the left by Count bits. The\r
+ low Count bits are fill with the high Count bits of Operand. The rotated\r
+ value is returned.\r
+\r
+ If Count is greater than 31, then ASSERT().\r
+\r
+ @param Operand The 32-bit operand to rotate left.\r
+ @param Count The number of bits to rotate left.\r
+\r
+ @return Operand << Count\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+LRotU32 (\r
+ IN UINT32 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ ASSERT (Count < 32);\r
+ return (Operand << Count) | (Operand >> (32 - Count));\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Rotates a 64-bit integer left between 0 and 63 bits, filling the low bits\r
+ with the high bits that were rotated.\r
+\r
+ This function rotates the 64-bit value Operand to the left by Count bits. The\r
+ low Count bits are fill with the high Count bits of Operand. The rotated\r
+ value is returned.\r
+\r
+ If Count is greater than 63, then ASSERT().\r
+\r
+ @param Operand The 64-bit operand to rotate left.\r
+ @param Count The number of bits to rotate left.\r
+\r
+ @return Operand << Count\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+LRotU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ ASSERT (Count < 64);\r
+ return InternalMathLRotU64 (Operand, Count);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Shifts a 64-bit integer left between 0 and 63 bits. The low bits are filled\r
+ with zeros. The shifted value is returned.\r
+\r
+ This function shifts the 64-bit value Operand to the left by Count bits. The\r
+ low Count bits are set to zero. The shifted value is returned.\r
+\r
+ If Count is greater than 63, then ASSERT().\r
+\r
+ @param Operand The 64-bit operand to shift left.\r
+ @param Count The number of bits to shift left.\r
+\r
+ @return Operand << Count.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+LShiftU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ ASSERT (Count < 64);\r
+ return InternalMathLShiftU64 (Operand, Count);\r
+}\r
--- /dev/null
+/** @file\r
+ Linked List Library Functions.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Worker function that locates the Node in the List.\r
+\r
+ By searching the List, finds the location of the Node in List. At the same time,\r
+ verifies the validity of this list.\r
+\r
+ If List is NULL, then ASSERT().\r
+ If List->ForwardLink is NULL, then ASSERT().\r
+ If List->backLink is NULL, then ASSERT().\r
+ If Node is NULL, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and DoMembershipCheck is TRUE and Node \r
+ is in not a member of List, then return FALSE\r
+ If PcdMaximumLinkedListLenth is not zero, and List contains more than\r
+ PcdMaximumLinkedListLenth nodes, then ASSERT().\r
+\r
+ @param List A pointer to a node in a linked list.\r
+ @param Node A pointer to a node in a linked list.\r
+ @param VerifyNodeInList TRUE if a check should be made to see if Node is a \r
+ member of List. FALSE if no membership test should \r
+ be performed.\r
+\r
+ @retval TRUE if PcdVerifyNodeInList is FALSE\r
+ @retval TRUE if DoMembershipCheck is FALSE\r
+ @retval TRUE if PcdVerifyNodeInList is TRUE and DoMembershipCheck is TRUE \r
+ and Node is a member of List.\r
+ @retval FALSE if PcdVerifyNodeInList is TRUE and DoMembershipCheck is TRUE \r
+ and Node is in not a member of List.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+InternalBaseLibIsNodeInList (\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node,\r
+ IN BOOLEAN VerifyNodeInList\r
+ )\r
+{\r
+ UINTN Count;\r
+ CONST LIST_ENTRY *Ptr;\r
+\r
+ //\r
+ // Test the validity of List and Node\r
+ //\r
+ ASSERT (List != NULL);\r
+ ASSERT (List->ForwardLink != NULL);\r
+ ASSERT (List->BackLink != NULL);\r
+ ASSERT (Node != NULL);\r
+\r
+ Count = 0;\r
+ Ptr = List;\r
+\r
+ if (FeaturePcdGet (PcdVerifyNodeInList) && VerifyNodeInList) {\r
+ //\r
+ // Check to see if Node is a member of List. \r
+ // Exit early if the number of nodes in List >= PcdMaximumLinkedListLength\r
+ //\r
+ do {\r
+ Ptr = Ptr->ForwardLink;\r
+ if (PcdGet32 (PcdMaximumLinkedListLength) > 0) {\r
+ Count++;\r
+ //\r
+ // ASSERT() if the linked list is too long\r
+ //\r
+ ASSERT (Count < PcdGet32 (PcdMaximumLinkedListLength));\r
+\r
+ //\r
+ // Return if the linked list is too long\r
+ //\r
+ if (Count >= PcdGet32 (PcdMaximumLinkedListLength)) {\r
+ return (BOOLEAN)(Ptr == Node);\r
+ }\r
+ }\r
+ } while ((Ptr != List) && (Ptr != Node)); \r
+\r
+ if (Ptr != Node) {\r
+ return FALSE;\r
+ }\r
+ }\r
+\r
+ if (PcdGet32 (PcdMaximumLinkedListLength) > 0) {\r
+ //\r
+ // Count the total number of nodes in List.\r
+ // Exit early if the number of nodes in List >= PcdMaximumLinkedListLength\r
+ //\r
+ do {\r
+ Ptr = Ptr->ForwardLink;\r
+ Count++;\r
+ } while ((Ptr != List) && (Count < PcdGet32 (PcdMaximumLinkedListLength)));\r
+\r
+ //\r
+ // ASSERT() if the linked list is too long\r
+ //\r
+ ASSERT (Count < PcdGet32 (PcdMaximumLinkedListLength));\r
+ }\r
+\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+ Initializes the head node of a doubly-linked list, and returns the pointer to\r
+ the head node of the doubly-linked list.\r
+\r
+ Initializes the forward and backward links of a new linked list. After\r
+ initializing a linked list with this function, the other linked list\r
+ functions may be used to add and remove nodes from the linked list. It is up\r
+ to the caller of this function to allocate the memory for ListHead.\r
+\r
+ If ListHead is NULL, then ASSERT().\r
+\r
+ @param ListHead A pointer to the head node of a new doubly-linked list.\r
+\r
+ @return ListHead\r
+\r
+**/\r
+LIST_ENTRY *\r
+EFIAPI\r
+InitializeListHead (\r
+ IN OUT LIST_ENTRY *ListHead\r
+ )\r
+\r
+{\r
+ ASSERT (ListHead != NULL);\r
+\r
+ ListHead->ForwardLink = ListHead;\r
+ ListHead->BackLink = ListHead;\r
+ return ListHead;\r
+}\r
+\r
+/**\r
+ Adds a node to the beginning of a doubly-linked list, and returns the pointer\r
+ to the head node of the doubly-linked list.\r
+\r
+ Adds the node Entry at the beginning of the doubly-linked list denoted by\r
+ ListHead, and returns ListHead.\r
+\r
+ If ListHead is NULL, then ASSERT().\r
+ If Entry is NULL, then ASSERT().\r
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or\r
+ InitializeListHead(), then ASSERT().\r
+ If PcdMaximumLinkedListLenth is not zero, and prior to insertion the number\r
+ of nodes in ListHead, including the ListHead node, is greater than or\r
+ equal to PcdMaximumLinkedListLength, then ASSERT().\r
+\r
+ @param ListHead A pointer to the head node of a doubly-linked list.\r
+ @param Entry A pointer to a node that is to be inserted at the beginning\r
+ of a doubly-linked list.\r
+\r
+ @return ListHead\r
+\r
+**/\r
+LIST_ENTRY *\r
+EFIAPI\r
+InsertHeadList (\r
+ IN OUT LIST_ENTRY *ListHead,\r
+ IN OUT LIST_ENTRY *Entry\r
+ )\r
+{\r
+ //\r
+ // ASSERT List not too long and Entry is not one of the nodes of List\r
+ //\r
+ ASSERT (InternalBaseLibIsNodeInList (ListHead, Entry, FALSE));\r
+ \r
+ Entry->ForwardLink = ListHead->ForwardLink;\r
+ Entry->BackLink = ListHead;\r
+ Entry->ForwardLink->BackLink = Entry;\r
+ ListHead->ForwardLink = Entry;\r
+ return ListHead;\r
+}\r
+\r
+/**\r
+ Adds a node to the end of a doubly-linked list, and returns the pointer to\r
+ the head node of the doubly-linked list.\r
+\r
+ Adds the node Entry to the end of the doubly-linked list denoted by ListHead,\r
+ and returns ListHead.\r
+\r
+ If ListHead is NULL, then ASSERT().\r
+ If Entry is NULL, then ASSERT().\r
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ InitializeListHead(), then ASSERT().\r
+ If PcdMaximumLinkedListLenth is not zero, and prior to insertion the number\r
+ of nodes in ListHead, including the ListHead node, is greater than or\r
+ equal to PcdMaximumLinkedListLength, then ASSERT().\r
+\r
+ @param ListHead A pointer to the head node of a doubly-linked list.\r
+ @param Entry A pointer to a node that is to be added at the end of the\r
+ doubly-linked list.\r
+\r
+ @return ListHead\r
+\r
+**/\r
+LIST_ENTRY *\r
+EFIAPI\r
+InsertTailList (\r
+ IN OUT LIST_ENTRY *ListHead,\r
+ IN OUT LIST_ENTRY *Entry\r
+ )\r
+{\r
+ //\r
+ // ASSERT List not too long and Entry is not one of the nodes of List\r
+ //\r
+ ASSERT (InternalBaseLibIsNodeInList (ListHead, Entry, FALSE));\r
+ \r
+ Entry->ForwardLink = ListHead;\r
+ Entry->BackLink = ListHead->BackLink;\r
+ Entry->BackLink->ForwardLink = Entry;\r
+ ListHead->BackLink = Entry;\r
+ return ListHead;\r
+}\r
+\r
+/**\r
+ Retrieves the first node of a doubly-linked list.\r
+\r
+ Returns the first node of a doubly-linked list. List must have been \r
+ initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().\r
+ If List is empty, then List is returned.\r
+\r
+ If List is NULL, then ASSERT().\r
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ InitializeListHead(), then ASSERT().\r
+ If PcdMaximumLinkedListLenth is not zero, and the number of nodes\r
+ in List, including the List node, is greater than or equal to\r
+ PcdMaximumLinkedListLength, then ASSERT().\r
+\r
+ @param List A pointer to the head node of a doubly-linked list.\r
+\r
+ @return The first node of a doubly-linked list.\r
+ @retval NULL The list is empty.\r
+\r
+**/\r
+LIST_ENTRY *\r
+EFIAPI\r
+GetFirstNode (\r
+ IN CONST LIST_ENTRY *List\r
+ )\r
+{\r
+ //\r
+ // ASSERT List not too long\r
+ //\r
+ ASSERT (InternalBaseLibIsNodeInList (List, List, FALSE));\r
+\r
+ return List->ForwardLink;\r
+}\r
+\r
+/**\r
+ Retrieves the next node of a doubly-linked list.\r
+\r
+ Returns the node of a doubly-linked list that follows Node. \r
+ List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()\r
+ or InitializeListHead(). If List is empty, then List is returned.\r
+\r
+ If List is NULL, then ASSERT().\r
+ If Node is NULL, then ASSERT().\r
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ InitializeListHead(), then ASSERT().\r
+ If PcdMaximumLinkedListLenth is not zero, and List contains more than\r
+ PcdMaximumLinkedListLenth nodes, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().\r
+\r
+ @param List A pointer to the head node of a doubly-linked list.\r
+ @param Node A pointer to a node in the doubly-linked list.\r
+\r
+ @return A pointer to the next node if one exists. Otherwise List is returned.\r
+\r
+**/\r
+LIST_ENTRY *\r
+EFIAPI\r
+GetNextNode (\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
+ )\r
+{\r
+ //\r
+ // ASSERT List not too long and Node is one of the nodes of List\r
+ //\r
+ ASSERT (InternalBaseLibIsNodeInList (List, Node, TRUE));\r
+\r
+ return Node->ForwardLink;\r
+}\r
+\r
+/**\r
+ Retrieves the previous node of a doubly-linked list.\r
+ \r
+ Returns the node of a doubly-linked list that precedes Node. \r
+ List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()\r
+ or InitializeListHead(). If List is empty, then List is returned.\r
+ \r
+ If List is NULL, then ASSERT().\r
+ If Node is NULL, then ASSERT().\r
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ InitializeListHead(), then ASSERT().\r
+ If PcdMaximumLinkedListLenth is not zero, and List contains more than\r
+ PcdMaximumLinkedListLenth nodes, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().\r
+ \r
+ @param List A pointer to the head node of a doubly-linked list.\r
+ @param Node A pointer to a node in the doubly-linked list.\r
+ \r
+ @return A pointer to the previous node if one exists. Otherwise List is returned.\r
+ \r
+**/\r
+LIST_ENTRY *\r
+EFIAPI\r
+GetPreviousNode (\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
+ )\r
+{\r
+ //\r
+ // ASSERT List not too long and Node is one of the nodes of List\r
+ //\r
+ ASSERT (InternalBaseLibIsNodeInList (List, Node, TRUE));\r
+ \r
+ return Node->BackLink;\r
+}\r
+\r
+/**\r
+ Checks to see if a doubly-linked list is empty or not.\r
+\r
+ Checks to see if the doubly-linked list is empty. If the linked list contains\r
+ zero nodes, this function returns TRUE. Otherwise, it returns FALSE.\r
+\r
+ If ListHead is NULL, then ASSERT().\r
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or \r
+ InitializeListHead(), then ASSERT().\r
+ If PcdMaximumLinkedListLenth is not zero, and the number of nodes\r
+ in List, including the List node, is greater than or equal to\r
+ PcdMaximumLinkedListLength, then ASSERT().\r
+\r
+ @param ListHead A pointer to the head node of a doubly-linked list.\r
+\r
+ @retval TRUE The linked list is empty.\r
+ @retval FALSE The linked list is not empty.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+IsListEmpty (\r
+ IN CONST LIST_ENTRY *ListHead\r
+ )\r
+{\r
+ //\r
+ // ASSERT List not too long\r
+ //\r
+ ASSERT (InternalBaseLibIsNodeInList (ListHead, ListHead, FALSE));\r
+ \r
+ return (BOOLEAN)(ListHead->ForwardLink == ListHead);\r
+}\r
+\r
+/**\r
+ Determines if a node in a doubly-linked list is the head node of a the same\r
+ doubly-linked list. This function is typically used to terminate a loop that\r
+ traverses all the nodes in a doubly-linked list starting with the head node.\r
+\r
+ Returns TRUE if Node is equal to List. Returns FALSE if Node is one of the\r
+ nodes in the doubly-linked list specified by List. List must have been\r
+ initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().\r
+\r
+ If List is NULL, then ASSERT().\r
+ If Node is NULL, then ASSERT().\r
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(), \r
+ then ASSERT().\r
+ If PcdMaximumLinkedListLenth is not zero, and the number of nodes\r
+ in List, including the List node, is greater than or equal to\r
+ PcdMaximumLinkedListLength, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List and Node is not \r
+ equal to List, then ASSERT().\r
+\r
+ @param List A pointer to the head node of a doubly-linked list.\r
+ @param Node A pointer to a node in the doubly-linked list.\r
+\r
+ @retval TRUE Node is one of the nodes in the doubly-linked list.\r
+ @retval FALSE Node is not one of the nodes in the doubly-linked list.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+IsNull (\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
+ )\r
+{\r
+ //\r
+ // ASSERT List not too long and Node is one of the nodes of List\r
+ //\r
+ ASSERT (InternalBaseLibIsNodeInList (List, Node, TRUE));\r
+ \r
+ return (BOOLEAN)(Node == List);\r
+}\r
+\r
+/**\r
+ Determines if a node the last node in a doubly-linked list.\r
+\r
+ Returns TRUE if Node is the last node in the doubly-linked list specified by\r
+ List. Otherwise, FALSE is returned. List must have been initialized with\r
+ INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().\r
+\r
+ If List is NULL, then ASSERT().\r
+ If Node is NULL, then ASSERT().\r
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or\r
+ InitializeListHead(), then ASSERT().\r
+ If PcdMaximumLinkedListLenth is not zero, and the number of nodes\r
+ in List, including the List node, is greater than or equal to\r
+ PcdMaximumLinkedListLength, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().\r
+\r
+ @param List A pointer to the head node of a doubly-linked list.\r
+ @param Node A pointer to a node in the doubly-linked list.\r
+\r
+ @retval TRUE Node is the last node in the linked list.\r
+ @retval FALSE Node is not the last node in the linked list.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+IsNodeAtEnd (\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
+ )\r
+{\r
+ //\r
+ // ASSERT List not too long and Node is one of the nodes of List\r
+ //\r
+ ASSERT (InternalBaseLibIsNodeInList (List, Node, TRUE));\r
+ \r
+ return (BOOLEAN)(!IsNull (List, Node) && List->BackLink == Node);\r
+}\r
+\r
+/**\r
+ Swaps the location of two nodes in a doubly-linked list, and returns the\r
+ first node after the swap.\r
+\r
+ If FirstEntry is identical to SecondEntry, then SecondEntry is returned.\r
+ Otherwise, the location of the FirstEntry node is swapped with the location\r
+ of the SecondEntry node in a doubly-linked list. SecondEntry must be in the\r
+ same double linked list as FirstEntry and that double linked list must have\r
+ been initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(). \r
+ SecondEntry is returned after the nodes are swapped.\r
+\r
+ If FirstEntry is NULL, then ASSERT().\r
+ If SecondEntry is NULL, then ASSERT().\r
+ If PcdVerifyNodeInList is TRUE and SecondEntry and FirstEntry are not in the \r
+ same linked list, then ASSERT().\r
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes in the\r
+ linked list containing the FirstEntry and SecondEntry nodes, including\r
+ the FirstEntry and SecondEntry nodes, is greater than or equal to\r
+ PcdMaximumLinkedListLength, then ASSERT().\r
+\r
+ @param FirstEntry A pointer to a node in a linked list.\r
+ @param SecondEntry A pointer to another node in the same linked list.\r
+ \r
+ @return SecondEntry.\r
+\r
+**/\r
+LIST_ENTRY *\r
+EFIAPI\r
+SwapListEntries (\r
+ IN OUT LIST_ENTRY *FirstEntry,\r
+ IN OUT LIST_ENTRY *SecondEntry\r
+ )\r
+{\r
+ LIST_ENTRY *Ptr;\r
+\r
+ if (FirstEntry == SecondEntry) {\r
+ return SecondEntry;\r
+ }\r
+\r
+ //\r
+ // ASSERT Entry1 and Entry2 are in the same linked list\r
+ //\r
+ ASSERT (InternalBaseLibIsNodeInList (FirstEntry, SecondEntry, TRUE));\r
+ \r
+ //\r
+ // Ptr is the node pointed to by FirstEntry->ForwardLink\r
+ //\r
+ Ptr = RemoveEntryList (FirstEntry);\r
+\r
+ //\r
+ // If FirstEntry immediately follows SecondEntry, FirstEntry will be placed\r
+ // immediately in front of SecondEntry\r
+ //\r
+ if (Ptr->BackLink == SecondEntry) {\r
+ return InsertTailList (SecondEntry, FirstEntry);\r
+ }\r
+\r
+ //\r
+ // Ptr == SecondEntry means SecondEntry immediately follows FirstEntry,\r
+ // then there are no further steps necessary\r
+ //\r
+ if (Ptr == InsertHeadList (SecondEntry, FirstEntry)) {\r
+ return Ptr;\r
+ }\r
+\r
+ //\r
+ // Move SecondEntry to the front of Ptr\r
+ //\r
+ RemoveEntryList (SecondEntry);\r
+ InsertTailList (Ptr, SecondEntry);\r
+ return SecondEntry;\r
+}\r
+\r
+/**\r
+ Removes a node from a doubly-linked list, and returns the node that follows\r
+ the removed node.\r
+\r
+ Removes the node Entry from a doubly-linked list. It is up to the caller of\r
+ this function to release the memory used by this node if that is required. On\r
+ exit, the node following Entry in the doubly-linked list is returned. If\r
+ Entry is the only node in the linked list, then the head node of the linked\r
+ list is returned.\r
+\r
+ If Entry is NULL, then ASSERT().\r
+ If Entry is the head node of an empty list, then ASSERT().\r
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes in the\r
+ linked list containing Entry, including the Entry node, is greater than\r
+ or equal to PcdMaximumLinkedListLength, then ASSERT().\r
+\r
+ @param Entry A pointer to a node in a linked list.\r
+\r
+ @return Entry.\r
+\r
+**/\r
+LIST_ENTRY *\r
+EFIAPI\r
+RemoveEntryList (\r
+ IN CONST LIST_ENTRY *Entry\r
+ )\r
+{\r
+ ASSERT (!IsListEmpty (Entry));\r
+ \r
+ Entry->ForwardLink->BackLink = Entry->BackLink;\r
+ Entry->BackLink->ForwardLink = Entry->ForwardLink;\r
+ return Entry->ForwardLink;\r
+}\r
--- /dev/null
+/** @file\r
+ Long Jump functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Restores the CPU context that was saved with SetJump().\r
+\r
+ Restores the CPU context from the buffer specified by JumpBuffer. This\r
+ function never returns to the caller. Instead is resumes execution based on\r
+ the state of JumpBuffer.\r
+\r
+ If JumpBuffer is NULL, then ASSERT().\r
+ For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ If Value is 0, then ASSERT().\r
+\r
+ @param JumpBuffer A pointer to CPU context buffer.\r
+ @param Value The value to return when the SetJump() context is\r
+ restored and must be non-zero.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+LongJump (\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
+ IN UINTN Value\r
+ )\r
+{\r
+ InternalAssertJumpBuffer (JumpBuffer);\r
+ ASSERT (Value != 0);\r
+\r
+ InternalLongJump (JumpBuffer, Value);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Returns the bit position of the lowest bit set in a 32-bit value.\r
+\r
+ This function computes the bit position of the lowest bit set in the 32-bit\r
+ value specified by Operand. If Operand is zero, then -1 is returned.\r
+ Otherwise, a value between 0 and 31 is returned.\r
+\r
+ @param Operand The 32-bit operand to evaluate.\r
+\r
+ @retval 0..31 The lowest bit set in Operand was found.\r
+ @retval -1 Operand is zero.\r
+\r
+**/\r
+INTN\r
+EFIAPI\r
+LowBitSet32 (\r
+ IN UINT32 Operand\r
+ )\r
+{\r
+ INTN BitIndex;\r
+\r
+ if (Operand == 0) {\r
+ return -1;\r
+ }\r
+\r
+ for (BitIndex = 0; 0 == (Operand & 1); BitIndex++, Operand >>= 1);\r
+ return BitIndex;\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Returns the bit position of the lowest bit set in a 64-bit value.\r
+\r
+ This function computes the bit position of the lowest bit set in the 64-bit\r
+ value specified by Operand. If Operand is zero, then -1 is returned.\r
+ Otherwise, a value between 0 and 63 is returned.\r
+\r
+ @param Operand The 64-bit operand to evaluate.\r
+\r
+ @retval 0..63 The lowest bit set in Operand was found.\r
+ @retval -1 Operand is zero.\r
+\r
+\r
+**/\r
+INTN\r
+EFIAPI\r
+LowBitSet64 (\r
+ IN UINT64 Operand\r
+ )\r
+{\r
+ INTN BitIndex;\r
+\r
+ if (Operand == 0) {\r
+ return -1;\r
+ }\r
+\r
+ for (BitIndex = 0;\r
+ (Operand & 1) == 0;\r
+ BitIndex++, Operand = RShiftU64 (Operand, 1));\r
+ return BitIndex;\r
+}\r
--- /dev/null
+/** @file\r
+ Leaf math worker functions that require 64-bit arithmetic support from the\r
+ compiler.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Shifts a 64-bit integer left between 0 and 63 bits. The low bits\r
+ are filled with zeros. The shifted value is returned.\r
+\r
+ This function shifts the 64-bit value Operand to the left by Count bits. The\r
+ low Count bits are set to zero. The shifted value is returned.\r
+\r
+ @param Operand The 64-bit operand to shift left.\r
+ @param Count The number of bits to shift left.\r
+\r
+ @return Operand << Count.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathLShiftU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ return Operand << Count;\r
+}\r
+\r
+/**\r
+ Shifts a 64-bit integer right between 0 and 63 bits. This high bits\r
+ are filled with zeros. The shifted value is returned.\r
+\r
+ This function shifts the 64-bit value Operand to the right by Count bits. The\r
+ high Count bits are set to zero. The shifted value is returned.\r
+\r
+ @param Operand The 64-bit operand to shift right.\r
+ @param Count The number of bits to shift right.\r
+\r
+ @return Operand >> Count.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathRShiftU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ return Operand >> Count;\r
+}\r
+\r
+/**\r
+ Shifts a 64-bit integer right between 0 and 63 bits. The high bits\r
+ are filled with original integer's bit 63. The shifted value is returned.\r
+\r
+ This function shifts the 64-bit value Operand to the right by Count bits. The\r
+ high Count bits are set to bit 63 of Operand. The shifted value is returned.\r
+\r
+ @param Operand The 64-bit operand to shift right.\r
+ @param Count The number of bits to shift right.\r
+\r
+ @return Operand arithmetically shifted right by Count.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathARShiftU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ INTN TestValue;\r
+\r
+ //\r
+ // Test if this compiler supports arithmetic shift\r
+ //\r
+ TestValue = (((-1) << (sizeof (-1) * 8 - 1)) >> (sizeof (-1) * 8 - 1));\r
+ if (TestValue == -1) {\r
+ //\r
+ // Arithmetic shift is supported\r
+ //\r
+ return (UINT64)((INT64)Operand >> Count);\r
+ }\r
+\r
+ //\r
+ // Arithmetic is not supported\r
+ //\r
+ return (Operand >> Count) |\r
+ ((INTN)Operand < 0 ? ~((UINTN)-1 >> Count) : 0);\r
+}\r
+\r
+\r
+/**\r
+ Rotates a 64-bit integer left between 0 and 63 bits, filling\r
+ the low bits with the high bits that were rotated.\r
+\r
+ This function rotates the 64-bit value Operand to the left by Count bits. The\r
+ low Count bits are fill with the high Count bits of Operand. The rotated\r
+ value is returned.\r
+\r
+ @param Operand The 64-bit operand to rotate left.\r
+ @param Count The number of bits to rotate left.\r
+\r
+ @return Operand <<< Count.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathLRotU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ return (Operand << Count) | (Operand >> (64 - Count));\r
+}\r
+\r
+/**\r
+ Rotates a 64-bit integer right between 0 and 63 bits, filling\r
+ the high bits with the high low bits that were rotated.\r
+\r
+ This function rotates the 64-bit value Operand to the right by Count bits.\r
+ The high Count bits are fill with the low Count bits of Operand. The rotated\r
+ value is returned.\r
+\r
+ @param Operand The 64-bit operand to rotate right.\r
+ @param Count The number of bits to rotate right.\r
+\r
+ @return Operand >>> Count.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathRRotU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ return (Operand >> Count) | (Operand << (64 - Count));\r
+}\r
+\r
+/**\r
+ Switches the endianess of a 64-bit integer.\r
+\r
+ This function swaps the bytes in a 64-bit unsigned value to switch the value\r
+ from little endian to big endian or vice versa. The byte swapped value is\r
+ returned.\r
+\r
+ @param Operand A 64-bit unsigned value.\r
+\r
+ @return The byte swapped Operand.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathSwapBytes64 (\r
+ IN UINT64 Operand\r
+ )\r
+{\r
+ UINT64 LowerBytes;\r
+ UINT64 HigherBytes;\r
+\r
+ LowerBytes = (UINT64) SwapBytes32 ((UINT32) Operand);\r
+ HigherBytes = (UINT64) SwapBytes32 ((UINT32) (Operand >> 32));\r
+\r
+ return (LowerBytes << 32 | HigherBytes);\r
+}\r
+\r
+/**\r
+ Multiplies a 64-bit unsigned integer by a 32-bit unsigned integer\r
+ and generates a 64-bit unsigned result.\r
+\r
+ This function multiplies the 64-bit unsigned value Multiplicand by the 32-bit\r
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-\r
+ bit unsigned result is returned.\r
+\r
+ @param Multiplicand A 64-bit unsigned value.\r
+ @param Multiplier A 32-bit unsigned value.\r
+\r
+ @return Multiplicand * Multiplier\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathMultU64x32 (\r
+ IN UINT64 Multiplicand,\r
+ IN UINT32 Multiplier\r
+ )\r
+{\r
+ return Multiplicand * Multiplier;\r
+}\r
+\r
+\r
+/**\r
+ Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer\r
+ and generates a 64-bit unsigned result.\r
+\r
+ This function multiplies the 64-bit unsigned value Multiplicand by the 64-bit\r
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-\r
+ bit unsigned result is returned.\r
+\r
+ @param Multiplicand A 64-bit unsigned value.\r
+ @param Multiplier A 64-bit unsigned value.\r
+\r
+ @return Multiplicand * Multiplier.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathMultU64x64 (\r
+ IN UINT64 Multiplicand,\r
+ IN UINT64 Multiplier\r
+ )\r
+{\r
+ return Multiplicand * Multiplier;\r
+}\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and\r
+ generates a 64-bit unsigned result.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 32-bit\r
+ unsigned value Divisor and generates a 64-bit unsigned quotient. This\r
+ function returns the 64-bit unsigned quotient.\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 32-bit unsigned value.\r
+\r
+ @return Dividend / Divisor.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathDivU64x32 (\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
+ )\r
+{\r
+ return Dividend / Divisor;\r
+}\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and\r
+ generates a 32-bit unsigned remainder.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 32-bit\r
+ unsigned value Divisor and generates a 32-bit remainder. This function\r
+ returns the 32-bit unsigned remainder.\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 32-bit unsigned value.\r
+\r
+ @return Dividend % Divisor.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+InternalMathModU64x32 (\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
+ )\r
+{\r
+ return (UINT32)(Dividend % Divisor);\r
+}\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and\r
+ generates a 64-bit unsigned result and an optional 32-bit unsigned remainder.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 32-bit\r
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder\r
+ is not NULL, then the 32-bit unsigned remainder is returned in Remainder.\r
+ This function returns the 64-bit unsigned quotient.\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 32-bit unsigned value.\r
+ @param Remainder A pointer to a 32-bit unsigned value. This parameter is\r
+ optional and may be NULL.\r
+\r
+ @return Dividend / Divisor.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathDivRemU64x32 (\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor,\r
+ OUT UINT32 *Remainder OPTIONAL\r
+ )\r
+{\r
+ if (Remainder != NULL) {\r
+ *Remainder = (UINT32)(Dividend % Divisor);\r
+ }\r
+ return Dividend / Divisor;\r
+}\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 64-bit unsigned integer and\r
+ generates a 64-bit unsigned result and an optional 64-bit unsigned remainder.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 64-bit\r
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder\r
+ is not NULL, then the 64-bit unsigned remainder is returned in Remainder.\r
+ This function returns the 64-bit unsigned quotient.\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 64-bit unsigned value.\r
+ @param Remainder A pointer to a 64-bit unsigned value. This parameter is\r
+ optional and may be NULL.\r
+\r
+ @return Dividend / Divisor\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+InternalMathDivRemU64x64 (\r
+ IN UINT64 Dividend,\r
+ IN UINT64 Divisor,\r
+ OUT UINT64 *Remainder OPTIONAL\r
+ )\r
+{\r
+ if (Remainder != NULL) {\r
+ *Remainder = Dividend % Divisor;\r
+ }\r
+ return Dividend / Divisor;\r
+}\r
+\r
+/**\r
+ Divides a 64-bit signed integer by a 64-bit signed integer and\r
+ generates a 64-bit signed result and an optional 64-bit signed remainder.\r
+\r
+ This function divides the 64-bit signed value Dividend by the 64-bit\r
+ signed value Divisor and generates a 64-bit signed quotient. If Remainder\r
+ is not NULL, then the 64-bit signed remainder is returned in Remainder.\r
+ This function returns the 64-bit signed quotient.\r
+\r
+ @param Dividend A 64-bit signed value.\r
+ @param Divisor A 64-bit signed value.\r
+ @param Remainder A pointer to a 64-bit signed value. This parameter is\r
+ optional and may be NULL.\r
+\r
+ @return Dividend / Divisor.\r
+\r
+**/\r
+INT64\r
+EFIAPI\r
+InternalMathDivRemS64x64 (\r
+ IN INT64 Dividend,\r
+ IN INT64 Divisor,\r
+ OUT INT64 *Remainder OPTIONAL\r
+ )\r
+{\r
+ if (Remainder != NULL) {\r
+ *Remainder = Dividend % Divisor;\r
+ }\r
+ return Dividend / Divisor;\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates\r
+ a 32-bit unsigned remainder.\r
+\r
+ This function divides the 64-bit unsigned value Dividend by the 32-bit\r
+ unsigned value Divisor and generates a 32-bit remainder. This function\r
+ returns the 32-bit unsigned remainder.\r
+\r
+ If Divisor is 0, then ASSERT().\r
+\r
+ @param Dividend A 64-bit unsigned value.\r
+ @param Divisor A 32-bit unsigned value.\r
+\r
+ @return Dividend % Divisor.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+ModU64x32 (\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
+ )\r
+{\r
+ ASSERT (Divisor != 0);\r
+ return InternalMathModU64x32 (Dividend, Divisor);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Multiplies a 64-bit signed integer by a 64-bit signed integer and generates a\r
+ 64-bit signed result.\r
+\r
+ This function multiplies the 64-bit signed value Multiplicand by the 64-bit\r
+ signed value Multiplier and generates a 64-bit signed result. This 64-bit\r
+ signed result is returned.\r
+\r
+ @param Multiplicand A 64-bit signed value.\r
+ @param Multiplier A 64-bit signed value.\r
+\r
+ @return Multiplicand * Multiplier.\r
+\r
+**/\r
+INT64\r
+EFIAPI\r
+MultS64x64 (\r
+ IN INT64 Multiplicand,\r
+ IN INT64 Multiplier\r
+ )\r
+{\r
+ return (INT64)MultU64x64 (Multiplicand, Multiplier);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Multiplies a 64-bit unsigned integer by a 32-bit unsigned integer and\r
+ generates a 64-bit unsigned result.\r
+\r
+ This function multiplies the 64-bit unsigned value Multiplicand by the 32-bit\r
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-\r
+ bit unsigned result is returned.\r
+\r
+ @param Multiplicand A 64-bit unsigned value.\r
+ @param Multiplier A 32-bit unsigned value.\r
+\r
+ @return Multiplicand * Multiplier.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MultU64x32 (\r
+ IN UINT64 Multiplicand,\r
+ IN UINT32 Multiplier\r
+ )\r
+{\r
+ UINT64 Result;\r
+\r
+ Result = InternalMathMultU64x32 (Multiplicand, Multiplier);\r
+\r
+ return Result;\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer and\r
+ generates a 64-bit unsigned result.\r
+\r
+ This function multiplies the 64-bit unsigned value Multiplicand by the 64-bit\r
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-\r
+ bit unsigned result is returned.\r
+\r
+ @param Multiplicand A 64-bit unsigned value.\r
+ @param Multiplier A 64-bit unsigned value.\r
+\r
+ @return Multiplicand * Multiplier.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MultU64x64 (\r
+ IN UINT64 Multiplicand,\r
+ IN UINT64 Multiplier\r
+ )\r
+{\r
+ UINT64 Result;\r
+\r
+ Result = InternalMathMultU64x64 (Multiplicand, Multiplier);\r
+\r
+ return Result;\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Rotates a 32-bit integer right between 0 and 31 bits, filling the high bits\r
+ with the low bits that were rotated.\r
+\r
+ This function rotates the 32-bit value Operand to the right by Count bits.\r
+ The high Count bits are fill with the low Count bits of Operand. The rotated\r
+ value is returned.\r
+\r
+ If Count is greater than 31, then ASSERT().\r
+\r
+ @param Operand The 32-bit operand to rotate right.\r
+ @param Count The number of bits to rotate right.\r
+\r
+ @return Operand >> Count.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+RRotU32 (\r
+ IN UINT32 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ ASSERT (Count < 32);\r
+ return (Operand >> Count) | (Operand << (32 - Count));\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Rotates a 64-bit integer right between 0 and 63 bits, filling the high bits\r
+ with the high low bits that were rotated.\r
+\r
+ This function rotates the 64-bit value Operand to the right by Count bits.\r
+ The high Count bits are fill with the low Count bits of Operand. The rotated\r
+ value is returned.\r
+\r
+ If Count is greater than 63, then ASSERT().\r
+\r
+ @param Operand The 64-bit operand to rotate right.\r
+ @param Count The number of bits to rotate right.\r
+\r
+ @return Operand >> Count.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+RRotU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ ASSERT (Count < 64);\r
+ return InternalMathRRotU64 (Operand, Count);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Shifts a 64-bit integer right between 0 and 63 bits. This high bits are\r
+ filled with zeros. The shifted value is returned.\r
+\r
+ This function shifts the 64-bit value Operand to the right by Count bits. The\r
+ high Count bits are set to zero. The shifted value is returned.\r
+\r
+ If Count is greater than 63, then ASSERT().\r
+\r
+ @param Operand The 64-bit operand to shift right.\r
+ @param Count The number of bits to shift right.\r
+\r
+ @return Operand >> Count.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+RShiftU64 (\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ ASSERT (Count < 64);\r
+ return InternalMathRShiftU64 (Operand, Count);\r
+}\r
--- /dev/null
+/** @file\r
+ Internal ASSERT () functions for SetJump.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Worker function that checks ASSERT condition for JumpBuffer\r
+\r
+ Checks ASSERT condition for JumpBuffer.\r
+\r
+ If JumpBuffer is NULL, then ASSERT().\r
+ For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().\r
+\r
+ @param JumpBuffer A pointer to CPU context buffer.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalAssertJumpBuffer (\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
+ )\r
+{\r
+ ASSERT (JumpBuffer != NULL);\r
+\r
+ ASSERT (((UINTN)JumpBuffer & (BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT - 1)) == 0);\r
+}\r
--- /dev/null
+/** @file\r
+ Unicode and ASCII string primatives.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+#define QUOTIENT_MAX_UINTN_DIVIDED_BY_10 ((UINTN) -1 / 10)\r
+#define REMAINDER_MAX_UINTN_DIVIDED_BY_10 ((UINTN) -1 % 10)\r
+\r
+#define QUOTIENT_MAX_UINTN_DIVIDED_BY_16 ((UINTN) -1 / 16)\r
+#define REMAINDER_MAX_UINTN_DIVIDED_BY_16 ((UINTN) -1 % 16)\r
+\r
+#define QUOTIENT_MAX_UINT64_DIVIDED_BY_10 ((UINT64) -1 / 10)\r
+#define REMAINDER_MAX_UINT64_DIVIDED_BY_10 ((UINT64) -1 % 10)\r
+\r
+#define QUOTIENT_MAX_UINT64_DIVIDED_BY_16 ((UINT64) -1 / 16)\r
+#define REMAINDER_MAX_UINT64_DIVIDED_BY_16 ((UINT64) -1 % 16)\r
+\r
+/**\r
+ Copies one Null-terminated Unicode string to another Null-terminated Unicode\r
+ string and returns the new Unicode string.\r
+\r
+ This function copies the contents of the Unicode string Source to the Unicode\r
+ string Destination, and returns Destination. If Source and Destination\r
+ overlap, then the results are undefined.\r
+\r
+ If Destination is NULL, then ASSERT().\r
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Source is NULL, then ASSERT().\r
+ If Source is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+\r
+ @param Destination A pointer to a Null-terminated Unicode string.\r
+ @param Source A pointer to a Null-terminated Unicode string.\r
+\r
+ @return Destination.\r
+\r
+**/\r
+CHAR16 *\r
+EFIAPI\r
+StrCpy (\r
+ OUT CHAR16 *Destination,\r
+ IN CONST CHAR16 *Source\r
+ )\r
+{\r
+ CHAR16 *ReturnValue;\r
+\r
+ //\r
+ // Destination cannot be NULL\r
+ //\r
+ ASSERT (Destination != NULL);\r
+ ASSERT (((UINTN) Destination & BIT0) == 0);\r
+\r
+ //\r
+ // Destination and source cannot overlap\r
+ //\r
+ ASSERT ((UINTN)(Destination - Source) > StrLen (Source));\r
+ ASSERT ((UINTN)(Source - Destination) > StrLen (Source));\r
+\r
+ ReturnValue = Destination;\r
+ while (*Source != 0) {\r
+ *(Destination++) = *(Source++);\r
+ }\r
+ *Destination = 0;\r
+ return ReturnValue;\r
+}\r
+\r
+/**\r
+ Copies up to a specified length from one Null-terminated Unicode string to \r
+ another Null-terminated Unicode string and returns the new Unicode string.\r
+\r
+ This function copies the contents of the Unicode string Source to the Unicode\r
+ string Destination, and returns Destination. At most, Length Unicode\r
+ characters are copied from Source to Destination. If Length is 0, then\r
+ Destination is returned unmodified. If Length is greater that the number of\r
+ Unicode characters in Source, then Destination is padded with Null Unicode\r
+ characters. If Source and Destination overlap, then the results are\r
+ undefined.\r
+\r
+ If Length > 0 and Destination is NULL, then ASSERT().\r
+ If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length > 0 and Source is NULL, then ASSERT().\r
+ If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than \r
+ PcdMaximumUnicodeStringLength, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param Destination A pointer to a Null-terminated Unicode string.\r
+ @param Source A pointer to a Null-terminated Unicode string.\r
+ @param Length The maximum number of Unicode characters to copy.\r
+\r
+ @return Destination.\r
+\r
+**/\r
+CHAR16 *\r
+EFIAPI\r
+StrnCpy (\r
+ OUT CHAR16 *Destination,\r
+ IN CONST CHAR16 *Source,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ CHAR16 *ReturnValue;\r
+\r
+ if (Length == 0) {\r
+ return Destination;\r
+ }\r
+\r
+ //\r
+ // Destination cannot be NULL if Length is not zero\r
+ //\r
+ ASSERT (Destination != NULL);\r
+ ASSERT (((UINTN) Destination & BIT0) == 0);\r
+\r
+ //\r
+ // Destination and source cannot overlap\r
+ //\r
+ ASSERT ((UINTN)(Destination - Source) > StrLen (Source));\r
+ ASSERT ((UINTN)(Source - Destination) >= Length);\r
+\r
+ if (PcdGet32 (PcdMaximumUnicodeStringLength) != 0) {\r
+ ASSERT (Length <= PcdGet32 (PcdMaximumUnicodeStringLength));\r
+ }\r
+\r
+ ReturnValue = Destination;\r
+\r
+ while ((*Source != L'\0') && (Length > 0)) {\r
+ *(Destination++) = *(Source++);\r
+ Length--;\r
+ }\r
+\r
+ ZeroMem (Destination, Length * sizeof (*Destination));\r
+ return ReturnValue;\r
+}\r
+\r
+/**\r
+ Returns the length of a Null-terminated Unicode string.\r
+\r
+ This function returns the number of Unicode characters in the Null-terminated\r
+ Unicode string specified by String.\r
+\r
+ If String is NULL, then ASSERT().\r
+ If String is not aligned on a 16-bit boundary, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated Unicode string.\r
+\r
+ @return The length of String.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+StrLen (\r
+ IN CONST CHAR16 *String\r
+ )\r
+{\r
+ UINTN Length;\r
+\r
+ ASSERT (String != NULL);\r
+ ASSERT (((UINTN) String & BIT0) == 0);\r
+\r
+ for (Length = 0; *String != L'\0'; String++, Length++) {\r
+ //\r
+ // If PcdMaximumUnicodeStringLength is not zero,\r
+ // length should not more than PcdMaximumUnicodeStringLength\r
+ //\r
+ if (PcdGet32 (PcdMaximumUnicodeStringLength) != 0) {\r
+ ASSERT (Length < PcdGet32 (PcdMaximumUnicodeStringLength));\r
+ }\r
+ }\r
+ return Length;\r
+}\r
+\r
+/**\r
+ Returns the size of a Null-terminated Unicode string in bytes, including the\r
+ Null terminator.\r
+\r
+ This function returns the size, in bytes, of the Null-terminated Unicode string \r
+ specified by String.\r
+\r
+ If String is NULL, then ASSERT().\r
+ If String is not aligned on a 16-bit boundary, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated Unicode string.\r
+\r
+ @return The size of String.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+StrSize (\r
+ IN CONST CHAR16 *String\r
+ )\r
+{\r
+ return (StrLen (String) + 1) * sizeof (*String);\r
+}\r
+\r
+/**\r
+ Compares two Null-terminated Unicode strings, and returns the difference\r
+ between the first mismatched Unicode characters.\r
+\r
+ This function compares the Null-terminated Unicode string FirstString to the\r
+ Null-terminated Unicode string SecondString. If FirstString is identical to\r
+ SecondString, then 0 is returned. Otherwise, the value returned is the first\r
+ mismatched Unicode character in SecondString subtracted from the first\r
+ mismatched Unicode character in FirstString.\r
+\r
+ If FirstString is NULL, then ASSERT().\r
+ If FirstString is not aligned on a 16-bit boundary, then ASSERT().\r
+ If SecondString is NULL, then ASSERT().\r
+ If SecondString is not aligned on a 16-bit boundary, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more\r
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more\r
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+\r
+ @param FirstString A pointer to a Null-terminated Unicode string.\r
+ @param SecondString A pointer to a Null-terminated Unicode string.\r
+\r
+ @retval 0 FirstString is identical to SecondString.\r
+ @return others FirstString is not identical to SecondString.\r
+\r
+**/\r
+INTN\r
+EFIAPI\r
+StrCmp (\r
+ IN CONST CHAR16 *FirstString,\r
+ IN CONST CHAR16 *SecondString\r
+ )\r
+{\r
+ //\r
+ // ASSERT both strings are less long than PcdMaximumUnicodeStringLength\r
+ //\r
+ ASSERT (StrSize (FirstString) != 0);\r
+ ASSERT (StrSize (SecondString) != 0);\r
+\r
+ while ((*FirstString != L'\0') && (*FirstString == *SecondString)) {\r
+ FirstString++;\r
+ SecondString++;\r
+ }\r
+ return *FirstString - *SecondString;\r
+}\r
+\r
+/**\r
+ Compares up to a specified length the contents of two Null-terminated Unicode strings,\r
+ and returns the difference between the first mismatched Unicode characters.\r
+ \r
+ This function compares the Null-terminated Unicode string FirstString to the\r
+ Null-terminated Unicode string SecondString. At most, Length Unicode\r
+ characters will be compared. If Length is 0, then 0 is returned. If\r
+ FirstString is identical to SecondString, then 0 is returned. Otherwise, the\r
+ value returned is the first mismatched Unicode character in SecondString\r
+ subtracted from the first mismatched Unicode character in FirstString.\r
+\r
+ If Length > 0 and FirstString is NULL, then ASSERT().\r
+ If Length > 0 and FirstString is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length > 0 and SecondString is NULL, then ASSERT().\r
+ If Length > 0 and SecondString is not aligned on a 16-bit boundary, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than\r
+ PcdMaximumUnicodeStringLength, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param FirstString A pointer to a Null-terminated Unicode string.\r
+ @param SecondString A pointer to a Null-terminated Unicode string.\r
+ @param Length The maximum number of Unicode characters to compare.\r
+\r
+ @retval 0 FirstString is identical to SecondString.\r
+ @return others FirstString is not identical to SecondString.\r
+\r
+**/\r
+INTN\r
+EFIAPI\r
+StrnCmp (\r
+ IN CONST CHAR16 *FirstString,\r
+ IN CONST CHAR16 *SecondString,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ if (Length == 0) {\r
+ return 0;\r
+ }\r
+\r
+ //\r
+ // ASSERT both strings are less long than PcdMaximumUnicodeStringLength.\r
+ // Length tests are performed inside StrLen().\r
+ //\r
+ ASSERT (StrSize (FirstString) != 0);\r
+ ASSERT (StrSize (SecondString) != 0);\r
+\r
+ if (PcdGet32 (PcdMaximumUnicodeStringLength) != 0) {\r
+ ASSERT (Length <= PcdGet32 (PcdMaximumUnicodeStringLength));\r
+ }\r
+\r
+ while ((*FirstString != L'\0') &&\r
+ (*FirstString == *SecondString) &&\r
+ (Length > 1)) {\r
+ FirstString++;\r
+ SecondString++;\r
+ Length--;\r
+ }\r
+\r
+ return *FirstString - *SecondString;\r
+}\r
+\r
+/**\r
+ Concatenates one Null-terminated Unicode string to another Null-terminated\r
+ Unicode string, and returns the concatenated Unicode string.\r
+\r
+ This function concatenates two Null-terminated Unicode strings. The contents\r
+ of Null-terminated Unicode string Source are concatenated to the end of\r
+ Null-terminated Unicode string Destination. The Null-terminated concatenated\r
+ Unicode String is returned. If Source and Destination overlap, then the\r
+ results are undefined.\r
+\r
+ If Destination is NULL, then ASSERT().\r
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Source is NULL, then ASSERT().\r
+ If Source is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Destination contains more\r
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and concatenating Destination\r
+ and Source results in a Unicode string with more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+\r
+ @param Destination A pointer to a Null-terminated Unicode string.\r
+ @param Source A pointer to a Null-terminated Unicode string.\r
+\r
+ @return Destination.\r
+\r
+**/\r
+CHAR16 *\r
+EFIAPI\r
+StrCat (\r
+ IN OUT CHAR16 *Destination,\r
+ IN CONST CHAR16 *Source\r
+ )\r
+{\r
+ StrCpy (Destination + StrLen (Destination), Source);\r
+\r
+ //\r
+ // Size of the resulting string should never be zero.\r
+ // PcdMaximumUnicodeStringLength is tested inside StrLen().\r
+ //\r
+ ASSERT (StrSize (Destination) != 0);\r
+ return Destination;\r
+}\r
+\r
+/**\r
+ Concatenates up to a specified length one Null-terminated Unicode to the end \r
+ of another Null-terminated Unicode string, and returns the concatenated \r
+ Unicode string.\r
+\r
+ This function concatenates two Null-terminated Unicode strings. The contents\r
+ of Null-terminated Unicode string Source are concatenated to the end of\r
+ Null-terminated Unicode string Destination, and Destination is returned. At\r
+ most, Length Unicode characters are concatenated from Source to the end of\r
+ Destination, and Destination is always Null-terminated. If Length is 0, then\r
+ Destination is returned unmodified. If Source and Destination overlap, then\r
+ the results are undefined.\r
+\r
+ If Destination is NULL, then ASSERT().\r
+ If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Length > 0 and Source is NULL, then ASSERT().\r
+ If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than \r
+ PcdMaximumUnicodeStringLength, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Destination contains more\r
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and concatenating Destination\r
+ and Source results in a Unicode string with more than PcdMaximumUnicodeStringLength\r
+ Unicode characters, not including the Null-terminator, then ASSERT().\r
+\r
+ @param Destination A pointer to a Null-terminated Unicode string.\r
+ @param Source A pointer to a Null-terminated Unicode string.\r
+ @param Length The maximum number of Unicode characters to concatenate from\r
+ Source.\r
+\r
+ @return Destination.\r
+\r
+**/\r
+CHAR16 *\r
+EFIAPI\r
+StrnCat (\r
+ IN OUT CHAR16 *Destination,\r
+ IN CONST CHAR16 *Source,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINTN DestinationLen;\r
+\r
+ DestinationLen = StrLen (Destination);\r
+ StrnCpy (Destination + DestinationLen, Source, Length);\r
+ Destination[DestinationLen + Length] = L'\0';\r
+\r
+ //\r
+ // Size of the resulting string should never be zero.\r
+ // PcdMaximumUnicodeStringLength is tested inside StrLen().\r
+ //\r
+ ASSERT (StrSize (Destination) != 0);\r
+ return Destination;\r
+}\r
+\r
+/**\r
+ Returns the first occurrence of a Null-terminated Unicode sub-string\r
+ in a Null-terminated Unicode string.\r
+\r
+ This function scans the contents of the Null-terminated Unicode string\r
+ specified by String and returns the first occurrence of SearchString.\r
+ If SearchString is not found in String, then NULL is returned. If\r
+ the length of SearchString is zero, then String is\r
+ returned.\r
+\r
+ If String is NULL, then ASSERT().\r
+ If String is not aligned on a 16-bit boundary, then ASSERT().\r
+ If SearchString is NULL, then ASSERT().\r
+ If SearchString is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ If PcdMaximumUnicodeStringLength is not zero, and SearchString\r
+ or String contains more than PcdMaximumUnicodeStringLength Unicode\r
+ characters, not including the Null-terminator, then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated Unicode string.\r
+ @param SearchString A pointer to a Null-terminated Unicode string to search for.\r
+\r
+ @retval NULL If the SearchString does not appear in String.\r
+ @return others If there is a match.\r
+\r
+**/\r
+CHAR16 *\r
+EFIAPI\r
+StrStr (\r
+ IN CONST CHAR16 *String,\r
+ IN CONST CHAR16 *SearchString\r
+ )\r
+{\r
+ CONST CHAR16 *FirstMatch;\r
+ CONST CHAR16 *SearchStringTmp;\r
+\r
+ //\r
+ // ASSERT both strings are less long than PcdMaximumUnicodeStringLength.\r
+ // Length tests are performed inside StrLen().\r
+ //\r
+ ASSERT (StrSize (String) != 0);\r
+ ASSERT (StrSize (SearchString) != 0);\r
+\r
+ if (*SearchString == L'\0') {\r
+ return (CHAR16 *) String;\r
+ }\r
+\r
+ while (*String != L'\0') {\r
+ SearchStringTmp = SearchString;\r
+ FirstMatch = String;\r
+ \r
+ while ((*String == *SearchStringTmp) \r
+ && (*String != L'\0')) {\r
+ String++;\r
+ SearchStringTmp++;\r
+ } \r
+ \r
+ if (*SearchStringTmp == L'\0') {\r
+ return (CHAR16 *) FirstMatch;\r
+ }\r
+\r
+ if (*String == L'\0') {\r
+ return NULL;\r
+ }\r
+\r
+ String = FirstMatch + 1;\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ Check if a Unicode character is a decimal character.\r
+\r
+ This internal function checks if a Unicode character is a \r
+ decimal character. The valid decimal character is from\r
+ L'0' to L'9'.\r
+\r
+ @param Char The character to check against.\r
+\r
+ @retval TRUE If the Char is a decmial character.\r
+ @retval FALSE If the Char is not a decmial character.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+InternalIsDecimalDigitCharacter (\r
+ IN CHAR16 Char\r
+ )\r
+{\r
+ return (BOOLEAN) (Char >= L'0' && Char <= L'9');\r
+}\r
+\r
+/**\r
+ Convert a Unicode character to upper case only if \r
+ it maps to a valid small-case ASCII character.\r
+\r
+ This internal function only deal with Unicode character\r
+ which maps to a valid small-case ASCII character, i.e.\r
+ L'a' to L'z'. For other Unicode character, the input character\r
+ is returned directly.\r
+\r
+ @param Char The character to convert.\r
+\r
+ @retval LowerCharacter If the Char is with range L'a' to L'z'.\r
+ @retval Unchanged Otherwise.\r
+\r
+**/\r
+CHAR16\r
+EFIAPI\r
+InternalCharToUpper (\r
+ IN CHAR16 Char\r
+ )\r
+{\r
+ if (Char >= L'a' && Char <= L'z') {\r
+ return (CHAR16) (Char - (L'a' - L'A'));\r
+ }\r
+\r
+ return Char;\r
+}\r
+\r
+/**\r
+ Convert a Unicode character to numerical value.\r
+\r
+ This internal function only deal with Unicode character\r
+ which maps to a valid hexadecimal ASII character, i.e.\r
+ L'0' to L'9', L'a' to L'f' or L'A' to L'F'. For other \r
+ Unicode character, the value returned does not make sense.\r
+\r
+ @param Char The character to convert.\r
+\r
+ @return The numerical value converted.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+InternalHexCharToUintn (\r
+ IN CHAR16 Char\r
+ )\r
+{\r
+ if (InternalIsDecimalDigitCharacter (Char)) {\r
+ return Char - L'0';\r
+ }\r
+\r
+ return (UINTN) (10 + InternalCharToUpper (Char) - L'A');\r
+}\r
+\r
+/**\r
+ Check if a Unicode character is a hexadecimal character.\r
+\r
+ This internal function checks if a Unicode character is a \r
+ decimal character. The valid hexadecimal character is \r
+ L'0' to L'9', L'a' to L'f', or L'A' to L'F'.\r
+\r
+\r
+ @param Char The character to check against.\r
+\r
+ @retval TRUE If the Char is a hexadecmial character.\r
+ @retval FALSE If the Char is not a hexadecmial character.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+InternalIsHexaDecimalDigitCharacter (\r
+ IN CHAR16 Char\r
+ )\r
+{\r
+\r
+ return (BOOLEAN) (InternalIsDecimalDigitCharacter (Char) ||\r
+ (Char >= L'A' && Char <= L'F') ||\r
+ (Char >= L'a' && Char <= L'f'));\r
+}\r
+\r
+/**\r
+ Convert a Null-terminated Unicode decimal string to a value of\r
+ type UINTN.\r
+\r
+ This function returns a value of type UINTN by interpreting the contents\r
+ of the Unicode string specified by String as a decimal number. The format\r
+ of the input Unicode string String is:\r
+\r
+ [spaces] [decimal digits].\r
+\r
+ The valid decimal digit character is in the range [0-9]. The\r
+ function will ignore the pad space, which includes spaces or\r
+ tab characters, before [decimal digits]. The running zero in the\r
+ beginning of [decimal digits] will be ignored. Then, the function\r
+ stops at the first character that is a not a valid decimal character\r
+ or a Null-terminator, whichever one comes first.\r
+\r
+ If String is NULL, then ASSERT().\r
+ If String is not aligned in a 16-bit boundary, then ASSERT().\r
+ If String has only pad spaces, then 0 is returned.\r
+ If String has no pad spaces or valid decimal digits,\r
+ then 0 is returned.\r
+ If the number represented by String overflows according\r
+ to the range defined by UINTN, then ASSERT().\r
+\r
+ If PcdMaximumUnicodeStringLength is not zero, and String contains\r
+ more than PcdMaximumUnicodeStringLength Unicode characters, not including\r
+ the Null-terminator, then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated Unicode string.\r
+\r
+ @retval Value translated from String.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+StrDecimalToUintn (\r
+ IN CONST CHAR16 *String\r
+ )\r
+{\r
+ UINTN Result;\r
+ \r
+ //\r
+ // ASSERT String is less long than PcdMaximumUnicodeStringLength.\r
+ // Length tests are performed inside StrLen().\r
+ //\r
+ ASSERT (StrSize (String) != 0);\r
+\r
+ //\r
+ // Ignore the pad spaces (space or tab)\r
+ //\r
+ while ((*String == L' ') || (*String == L'\t')) {\r
+ String++;\r
+ }\r
+\r
+ //\r
+ // Ignore leading Zeros after the spaces\r
+ //\r
+ while (*String == L'0') {\r
+ String++;\r
+ }\r
+\r
+ Result = 0;\r
+\r
+ while (InternalIsDecimalDigitCharacter (*String)) {\r
+ //\r
+ // If the number represented by String overflows according \r
+ // to the range defined by UINTN, then ASSERT().\r
+ //\r
+ ASSERT ((Result < QUOTIENT_MAX_UINTN_DIVIDED_BY_10) ||\r
+ ((Result == QUOTIENT_MAX_UINTN_DIVIDED_BY_10) &&\r
+ (*String - L'0') <= REMAINDER_MAX_UINTN_DIVIDED_BY_10)\r
+ );\r
+\r
+ Result = Result * 10 + (*String - L'0');\r
+ String++;\r
+ }\r
+ \r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ Convert a Null-terminated Unicode decimal string to a value of\r
+ type UINT64.\r
+\r
+ This function returns a value of type UINT64 by interpreting the contents\r
+ of the Unicode string specified by String as a decimal number. The format\r
+ of the input Unicode string String is:\r
+\r
+ [spaces] [decimal digits].\r
+\r
+ The valid decimal digit character is in the range [0-9]. The\r
+ function will ignore the pad space, which includes spaces or\r
+ tab characters, before [decimal digits]. The running zero in the\r
+ beginning of [decimal digits] will be ignored. Then, the function\r
+ stops at the first character that is a not a valid decimal character\r
+ or a Null-terminator, whichever one comes first.\r
+\r
+ If String is NULL, then ASSERT().\r
+ If String is not aligned in a 16-bit boundary, then ASSERT().\r
+ If String has only pad spaces, then 0 is returned.\r
+ If String has no pad spaces or valid decimal digits,\r
+ then 0 is returned.\r
+ If the number represented by String overflows according\r
+ to the range defined by UINT64, then ASSERT().\r
+\r
+ If PcdMaximumUnicodeStringLength is not zero, and String contains\r
+ more than PcdMaximumUnicodeStringLength Unicode characters, not including\r
+ the Null-terminator, then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated Unicode string.\r
+\r
+ @retval Value translated from String.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+StrDecimalToUint64 (\r
+ IN CONST CHAR16 *String\r
+ )\r
+{\r
+ UINT64 Result;\r
+ \r
+ //\r
+ // ASSERT String is less long than PcdMaximumUnicodeStringLength.\r
+ // Length tests are performed inside StrLen().\r
+ //\r
+ ASSERT (StrSize (String) != 0);\r
+\r
+ //\r
+ // Ignore the pad spaces (space or tab)\r
+ //\r
+ while ((*String == L' ') || (*String == L'\t')) {\r
+ String++;\r
+ }\r
+\r
+ //\r
+ // Ignore leading Zeros after the spaces\r
+ //\r
+ while (*String == L'0') {\r
+ String++;\r
+ }\r
+\r
+ Result = 0;\r
+\r
+ while (InternalIsDecimalDigitCharacter (*String)) {\r
+ //\r
+ // If the number represented by String overflows according \r
+ // to the range defined by UINTN, then ASSERT().\r
+ //\r
+ ASSERT ((Result < QUOTIENT_MAX_UINT64_DIVIDED_BY_10) || \r
+ ((Result == QUOTIENT_MAX_UINT64_DIVIDED_BY_10) && \r
+ (*String - L'0') <= REMAINDER_MAX_UINT64_DIVIDED_BY_10)\r
+ );\r
+\r
+ Result = MultU64x32 (Result, 10) + (*String - L'0');\r
+ String++;\r
+ }\r
+ \r
+ return Result;\r
+}\r
+\r
+/**\r
+ Convert a Null-terminated Unicode hexadecimal string to a value of type UINTN.\r
+\r
+ This function returns a value of type UINTN by interpreting the contents\r
+ of the Unicode string specified by String as a hexadecimal number.\r
+ The format of the input Unicode string String is:\r
+\r
+ [spaces][zeros][x][hexadecimal digits].\r
+\r
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].\r
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix.\r
+ If "x" appears in the input string, it must be prefixed with at least one 0.\r
+ The function will ignore the pad space, which includes spaces or tab characters,\r
+ before [zeros], [x] or [hexadecimal digit]. The running zero before [x] or\r
+ [hexadecimal digit] will be ignored. Then, the decoding starts after [x] or the\r
+ first valid hexadecimal digit. Then, the function stops at the first character that is\r
+ a not a valid hexadecimal character or NULL, whichever one comes first.\r
+\r
+ If String is NULL, then ASSERT().\r
+ If String is not aligned in a 16-bit boundary, then ASSERT().\r
+ If String has only pad spaces, then zero is returned.\r
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits,\r
+ then zero is returned.\r
+ If the number represented by String overflows according to the range defined by\r
+ UINTN, then ASSERT().\r
+\r
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated Unicode string.\r
+\r
+ @retval Value translated from String.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+StrHexToUintn (\r
+ IN CONST CHAR16 *String\r
+ )\r
+{\r
+ UINTN Result;\r
+\r
+ //\r
+ // ASSERT String is less long than PcdMaximumUnicodeStringLength.\r
+ // Length tests are performed inside StrLen().\r
+ //\r
+ ASSERT (StrSize (String) != 0);\r
+ \r
+ //\r
+ // Ignore the pad spaces (space or tab) \r
+ //\r
+ while ((*String == L' ') || (*String == L'\t')) {\r
+ String++;\r
+ }\r
+\r
+ //\r
+ // Ignore leading Zeros after the spaces\r
+ //\r
+ while (*String == L'0') {\r
+ String++;\r
+ }\r
+\r
+ if (InternalCharToUpper (*String) == L'X') {\r
+ if (*(String - 1) != L'0') {\r
+ return 0;\r
+ }\r
+ //\r
+ // Skip the 'X'\r
+ //\r
+ String++;\r
+ }\r
+\r
+ Result = 0;\r
+ \r
+ while (InternalIsHexaDecimalDigitCharacter (*String)) {\r
+ //\r
+ // If the Hex Number represented by String overflows according \r
+ // to the range defined by UINTN, then ASSERT().\r
+ //\r
+ ASSERT ((Result < QUOTIENT_MAX_UINTN_DIVIDED_BY_16) ||\r
+ ((Result == QUOTIENT_MAX_UINTN_DIVIDED_BY_16) && \r
+ (InternalHexCharToUintn (*String) <= REMAINDER_MAX_UINTN_DIVIDED_BY_16))\r
+ );\r
+\r
+ Result = (Result << 4) + InternalHexCharToUintn (*String);\r
+ String++;\r
+ }\r
+\r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ Convert a Null-terminated Unicode hexadecimal string to a value of type UINT64.\r
+\r
+ This function returns a value of type UINT64 by interpreting the contents\r
+ of the Unicode string specified by String as a hexadecimal number.\r
+ The format of the input Unicode string String is\r
+\r
+ [spaces][zeros][x][hexadecimal digits].\r
+\r
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].\r
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix.\r
+ If "x" appears in the input string, it must be prefixed with at least one 0.\r
+ The function will ignore the pad space, which includes spaces or tab characters,\r
+ before [zeros], [x] or [hexadecimal digit]. The running zero before [x] or\r
+ [hexadecimal digit] will be ignored. Then, the decoding starts after [x] or the\r
+ first valid hexadecimal digit. Then, the function stops at the first character that is\r
+ a not a valid hexadecimal character or NULL, whichever one comes first.\r
+\r
+ If String is NULL, then ASSERT().\r
+ If String is not aligned in a 16-bit boundary, then ASSERT().\r
+ If String has only pad spaces, then zero is returned.\r
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits,\r
+ then zero is returned.\r
+ If the number represented by String overflows according to the range defined by\r
+ UINT64, then ASSERT().\r
+\r
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than\r
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated Unicode string.\r
+\r
+ @retval Value translated from String.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+StrHexToUint64 (\r
+ IN CONST CHAR16 *String\r
+ )\r
+{\r
+ UINT64 Result;\r
+\r
+ //\r
+ // ASSERT String is less long than PcdMaximumUnicodeStringLength.\r
+ // Length tests are performed inside StrLen().\r
+ //\r
+ ASSERT (StrSize (String) != 0);\r
+ \r
+ //\r
+ // Ignore the pad spaces (space or tab) \r
+ //\r
+ while ((*String == L' ') || (*String == L'\t')) {\r
+ String++;\r
+ }\r
+\r
+ //\r
+ // Ignore leading Zeros after the spaces\r
+ //\r
+ while (*String == L'0') {\r
+ String++;\r
+ }\r
+\r
+ if (InternalCharToUpper (*String) == L'X') {\r
+ ASSERT (*(String - 1) == L'0');\r
+ if (*(String - 1) != L'0') {\r
+ return 0;\r
+ }\r
+ //\r
+ // Skip the 'X'\r
+ //\r
+ String++;\r
+ }\r
+\r
+ Result = 0;\r
+ \r
+ while (InternalIsHexaDecimalDigitCharacter (*String)) {\r
+ //\r
+ // If the Hex Number represented by String overflows according \r
+ // to the range defined by UINTN, then ASSERT().\r
+ //\r
+ ASSERT ((Result < QUOTIENT_MAX_UINT64_DIVIDED_BY_16)|| \r
+ ((Result == QUOTIENT_MAX_UINT64_DIVIDED_BY_16) && \r
+ (InternalHexCharToUintn (*String) <= REMAINDER_MAX_UINT64_DIVIDED_BY_16))\r
+ );\r
+\r
+ Result = LShiftU64 (Result, 4);\r
+ Result = Result + InternalHexCharToUintn (*String);\r
+ String++;\r
+ }\r
+\r
+ return Result;\r
+}\r
+\r
+/**\r
+ Check if a ASCII character is a decimal character.\r
+\r
+ This internal function checks if a Unicode character is a \r
+ decimal character. The valid decimal character is from\r
+ '0' to '9'.\r
+\r
+ @param Char The character to check against.\r
+\r
+ @retval TRUE If the Char is a decmial character.\r
+ @retval FALSE If the Char is not a decmial character.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+InternalAsciiIsDecimalDigitCharacter (\r
+ IN CHAR8 Char\r
+ )\r
+{\r
+ return (BOOLEAN) (Char >= '0' && Char <= '9');\r
+}\r
+\r
+/**\r
+ Check if a ASCII character is a hexadecimal character.\r
+\r
+ This internal function checks if a ASCII character is a \r
+ decimal character. The valid hexadecimal character is \r
+ L'0' to L'9', L'a' to L'f', or L'A' to L'F'.\r
+\r
+\r
+ @param Char The character to check against.\r
+\r
+ @retval TRUE If the Char is a hexadecmial character.\r
+ @retval FALSE If the Char is not a hexadecmial character.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+InternalAsciiIsHexaDecimalDigitCharacter (\r
+ IN CHAR8 Char\r
+ )\r
+{\r
+\r
+ return (BOOLEAN) (InternalAsciiIsDecimalDigitCharacter (Char) ||\r
+ (Char >= 'A' && Char <= 'F') ||\r
+ (Char >= 'a' && Char <= 'f'));\r
+}\r
+\r
+/**\r
+ Convert a Null-terminated Unicode string to a Null-terminated\r
+ ASCII string and returns the ASCII string.\r
+\r
+ This function converts the content of the Unicode string Source\r
+ to the ASCII string Destination by copying the lower 8 bits of\r
+ each Unicode character. It returns Destination.\r
+\r
+ If any Unicode characters in Source contain non-zero value in\r
+ the upper 8 bits, then ASSERT().\r
+\r
+ If Destination is NULL, then ASSERT().\r
+ If Source is NULL, then ASSERT().\r
+ If Source is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Source and Destination overlap, then ASSERT().\r
+\r
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains\r
+ more than PcdMaximumUnicodeStringLength Unicode characters, not including\r
+ the Null-terminator, then ASSERT().\r
+\r
+ If PcdMaximumAsciiStringLength is not zero, and Source contains more\r
+ than PcdMaximumAsciiStringLength Unicode characters, not including the\r
+ Null-terminator, then ASSERT().\r
+\r
+ @param Source A pointer to a Null-terminated Unicode string.\r
+ @param Destination A pointer to a Null-terminated ASCII string.\r
+\r
+ @return Destination.\r
+\r
+**/\r
+CHAR8 *\r
+EFIAPI\r
+UnicodeStrToAsciiStr (\r
+ IN CONST CHAR16 *Source,\r
+ OUT CHAR8 *Destination\r
+ )\r
+{\r
+ CHAR8 *ReturnValue;\r
+\r
+ ASSERT (Destination != NULL);\r
+\r
+ //\r
+ // ASSERT if Source is long than PcdMaximumUnicodeStringLength.\r
+ // Length tests are performed inside StrLen().\r
+ //\r
+ ASSERT (StrSize (Source) != 0);\r
+\r
+ //\r
+ // Source and Destination should not overlap\r
+ //\r
+ ASSERT ((UINTN) ((CHAR16 *) Destination - Source) > StrLen (Source));\r
+ ASSERT ((UINTN) ((CHAR8 *) Source - Destination) > StrLen (Source));\r
+\r
+\r
+ ReturnValue = Destination;\r
+ while (*Source != '\0') {\r
+ //\r
+ // If any Unicode characters in Source contain \r
+ // non-zero value in the upper 8 bits, then ASSERT().\r
+ //\r
+ ASSERT (*Source < 0x100);\r
+ *(Destination++) = (CHAR8) *(Source++);\r
+ }\r
+\r
+ *Destination = '\0';\r
+\r
+ //\r
+ // ASSERT Original Destination is less long than PcdMaximumAsciiStringLength.\r
+ // Length tests are performed inside AsciiStrLen().\r
+ //\r
+ ASSERT (AsciiStrSize (ReturnValue) != 0);\r
+\r
+ return ReturnValue;\r
+}\r
+\r
+\r
+/**\r
+ Copies one Null-terminated ASCII string to another Null-terminated ASCII\r
+ string and returns the new ASCII string.\r
+\r
+ This function copies the contents of the ASCII string Source to the ASCII\r
+ string Destination, and returns Destination. If Source and Destination\r
+ overlap, then the results are undefined.\r
+\r
+ If Destination is NULL, then ASSERT().\r
+ If Source is NULL, then ASSERT().\r
+ If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero and Source contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param Destination A pointer to a Null-terminated ASCII string.\r
+ @param Source A pointer to a Null-terminated ASCII string.\r
+\r
+ @return Destination\r
+\r
+**/\r
+CHAR8 *\r
+EFIAPI\r
+AsciiStrCpy (\r
+ OUT CHAR8 *Destination,\r
+ IN CONST CHAR8 *Source\r
+ )\r
+{\r
+ CHAR8 *ReturnValue;\r
+\r
+ //\r
+ // Destination cannot be NULL\r
+ //\r
+ ASSERT (Destination != NULL);\r
+\r
+ //\r
+ // Destination and source cannot overlap\r
+ //\r
+ ASSERT ((UINTN)(Destination - Source) > AsciiStrLen (Source));\r
+ ASSERT ((UINTN)(Source - Destination) > AsciiStrLen (Source));\r
+\r
+ ReturnValue = Destination;\r
+ while (*Source != 0) {\r
+ *(Destination++) = *(Source++);\r
+ }\r
+ *Destination = 0;\r
+ return ReturnValue;\r
+}\r
+\r
+/**\r
+ Copies up to a specified length one Null-terminated ASCII string to another \r
+ Null-terminated ASCII string and returns the new ASCII string.\r
+\r
+ This function copies the contents of the ASCII string Source to the ASCII\r
+ string Destination, and returns Destination. At most, Length ASCII characters\r
+ are copied from Source to Destination. If Length is 0, then Destination is\r
+ returned unmodified. If Length is greater that the number of ASCII characters\r
+ in Source, then Destination is padded with Null ASCII characters. If Source\r
+ and Destination overlap, then the results are undefined.\r
+\r
+ If Destination is NULL, then ASSERT().\r
+ If Source is NULL, then ASSERT().\r
+ If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than \r
+ PcdMaximumAsciiStringLength, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Source contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param Destination A pointer to a Null-terminated ASCII string.\r
+ @param Source A pointer to a Null-terminated ASCII string.\r
+ @param Length The maximum number of ASCII characters to copy.\r
+\r
+ @return Destination\r
+\r
+**/\r
+CHAR8 *\r
+EFIAPI\r
+AsciiStrnCpy (\r
+ OUT CHAR8 *Destination,\r
+ IN CONST CHAR8 *Source,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ CHAR8 *ReturnValue;\r
+\r
+ if (Length == 0) {\r
+ return Destination;\r
+ }\r
+\r
+ //\r
+ // Destination cannot be NULL\r
+ //\r
+ ASSERT (Destination != NULL);\r
+\r
+ //\r
+ // Destination and source cannot overlap\r
+ //\r
+ ASSERT ((UINTN)(Destination - Source) > AsciiStrLen (Source));\r
+ ASSERT ((UINTN)(Source - Destination) >= Length);\r
+\r
+ if (PcdGet32 (PcdMaximumAsciiStringLength) != 0) {\r
+ ASSERT (Length <= PcdGet32 (PcdMaximumAsciiStringLength));\r
+ }\r
+\r
+ ReturnValue = Destination;\r
+\r
+ while (*Source != 0 && Length > 0) {\r
+ *(Destination++) = *(Source++);\r
+ Length--;\r
+ }\r
+\r
+ ZeroMem (Destination, Length * sizeof (*Destination));\r
+ return ReturnValue;\r
+}\r
+\r
+/**\r
+ Returns the length of a Null-terminated ASCII string.\r
+\r
+ This function returns the number of ASCII characters in the Null-terminated\r
+ ASCII string specified by String.\r
+\r
+ If Length > 0 and Destination is NULL, then ASSERT().\r
+ If Length > 0 and Source is NULL, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero and String contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated ASCII string.\r
+\r
+ @return The length of String.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsciiStrLen (\r
+ IN CONST CHAR8 *String\r
+ )\r
+{\r
+ UINTN Length;\r
+\r
+ ASSERT (String != NULL);\r
+\r
+ for (Length = 0; *String != '\0'; String++, Length++) {\r
+ //\r
+ // If PcdMaximumUnicodeStringLength is not zero,\r
+ // length should not more than PcdMaximumUnicodeStringLength\r
+ //\r
+ if (PcdGet32 (PcdMaximumAsciiStringLength) != 0) {\r
+ ASSERT (Length < PcdGet32 (PcdMaximumAsciiStringLength));\r
+ }\r
+ }\r
+ return Length;\r
+}\r
+\r
+/**\r
+ Returns the size of a Null-terminated ASCII string in bytes, including the\r
+ Null terminator.\r
+\r
+ This function returns the size, in bytes, of the Null-terminated ASCII string\r
+ specified by String.\r
+\r
+ If String is NULL, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero and String contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated ASCII string.\r
+\r
+ @return The size of String.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsciiStrSize (\r
+ IN CONST CHAR8 *String\r
+ )\r
+{\r
+ return (AsciiStrLen (String) + 1) * sizeof (*String);\r
+}\r
+\r
+/**\r
+ Compares two Null-terminated ASCII strings, and returns the difference\r
+ between the first mismatched ASCII characters.\r
+\r
+ This function compares the Null-terminated ASCII string FirstString to the\r
+ Null-terminated ASCII string SecondString. If FirstString is identical to\r
+ SecondString, then 0 is returned. Otherwise, the value returned is the first\r
+ mismatched ASCII character in SecondString subtracted from the first\r
+ mismatched ASCII character in FirstString.\r
+\r
+ If FirstString is NULL, then ASSERT().\r
+ If SecondString is NULL, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero and FirstString contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero and SecondString contains more\r
+ than PcdMaximumAsciiStringLength ASCII characters, not including the\r
+ Null-terminator, then ASSERT().\r
+\r
+ @param FirstString A pointer to a Null-terminated ASCII string.\r
+ @param SecondString A pointer to a Null-terminated ASCII string.\r
+\r
+ @retval ==0 FirstString is identical to SecondString.\r
+ @retval !=0 FirstString is not identical to SecondString.\r
+\r
+**/\r
+INTN\r
+EFIAPI\r
+AsciiStrCmp (\r
+ IN CONST CHAR8 *FirstString,\r
+ IN CONST CHAR8 *SecondString\r
+ )\r
+{\r
+ //\r
+ // ASSERT both strings are less long than PcdMaximumAsciiStringLength\r
+ //\r
+ ASSERT (AsciiStrSize (FirstString));\r
+ ASSERT (AsciiStrSize (SecondString));\r
+\r
+ while ((*FirstString != '\0') && (*FirstString == *SecondString)) {\r
+ FirstString++;\r
+ SecondString++;\r
+ }\r
+\r
+ return *FirstString - *SecondString;\r
+}\r
+\r
+/**\r
+ Converts a lowercase Ascii character to upper one.\r
+\r
+ If Chr is lowercase Ascii character, then converts it to upper one.\r
+\r
+ If Value >= 0xA0, then ASSERT().\r
+ If (Value & 0x0F) >= 0x0A, then ASSERT().\r
+\r
+ @param Chr one Ascii character\r
+\r
+ @return The uppercase value of Ascii character \r
+\r
+**/\r
+CHAR8\r
+EFIAPI\r
+InternalBaseLibAsciiToUpper (\r
+ IN CHAR8 Chr\r
+ )\r
+{\r
+ return (UINT8) ((Chr >= 'a' && Chr <= 'z') ? Chr - ('a' - 'A') : Chr);\r
+}\r
+\r
+/**\r
+ Convert a ASCII character to numerical value.\r
+\r
+ This internal function only deal with Unicode character\r
+ which maps to a valid hexadecimal ASII character, i.e.\r
+ '0' to '9', 'a' to 'f' or 'A' to 'F'. For other \r
+ ASCII character, the value returned does not make sense.\r
+\r
+ @param Char The character to convert.\r
+\r
+ @return The numerical value converted.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+InternalAsciiHexCharToUintn (\r
+ IN CHAR8 Char\r
+ )\r
+{\r
+ if (InternalIsDecimalDigitCharacter (Char)) {\r
+ return Char - '0';\r
+ }\r
+\r
+ return (UINTN) (10 + InternalBaseLibAsciiToUpper (Char) - 'A');\r
+}\r
+\r
+\r
+/**\r
+ Performs a case insensitive comparison of two Null-terminated ASCII strings,\r
+ and returns the difference between the first mismatched ASCII characters.\r
+\r
+ This function performs a case insensitive comparison of the Null-terminated\r
+ ASCII string FirstString to the Null-terminated ASCII string SecondString. If\r
+ FirstString is identical to SecondString, then 0 is returned. Otherwise, the\r
+ value returned is the first mismatched lower case ASCII character in\r
+ SecondString subtracted from the first mismatched lower case ASCII character\r
+ in FirstString.\r
+\r
+ If FirstString is NULL, then ASSERT().\r
+ If SecondString is NULL, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero and FirstString contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero and SecondString contains more\r
+ than PcdMaximumAsciiStringLength ASCII characters, not including the\r
+ Null-terminator, then ASSERT().\r
+\r
+ @param FirstString A pointer to a Null-terminated ASCII string.\r
+ @param SecondString A pointer to a Null-terminated ASCII string.\r
+\r
+ @retval ==0 FirstString is identical to SecondString using case insensitive\r
+ comparisons.\r
+ @retval !=0 FirstString is not identical to SecondString using case\r
+ insensitive comparisons.\r
+\r
+**/\r
+INTN\r
+EFIAPI\r
+AsciiStriCmp (\r
+ IN CONST CHAR8 *FirstString,\r
+ IN CONST CHAR8 *SecondString\r
+ )\r
+{\r
+ CHAR8 UpperFirstString;\r
+ CHAR8 UpperSecondString;\r
+\r
+ //\r
+ // ASSERT both strings are less long than PcdMaximumAsciiStringLength\r
+ //\r
+ ASSERT (AsciiStrSize (FirstString));\r
+ ASSERT (AsciiStrSize (SecondString));\r
+\r
+ UpperFirstString = InternalBaseLibAsciiToUpper (*FirstString);\r
+ UpperSecondString = InternalBaseLibAsciiToUpper (*SecondString);\r
+ while ((*FirstString != '\0') && (UpperFirstString == UpperSecondString)) {\r
+ FirstString++;\r
+ SecondString++;\r
+ UpperFirstString = InternalBaseLibAsciiToUpper (*FirstString);\r
+ UpperSecondString = InternalBaseLibAsciiToUpper (*SecondString);\r
+ }\r
+\r
+ return UpperFirstString - UpperSecondString;\r
+}\r
+\r
+/**\r
+ Compares two Null-terminated ASCII strings with maximum lengths, and returns\r
+ the difference between the first mismatched ASCII characters.\r
+\r
+ This function compares the Null-terminated ASCII string FirstString to the\r
+ Null-terminated ASCII string SecondString. At most, Length ASCII characters\r
+ will be compared. If Length is 0, then 0 is returned. If FirstString is\r
+ identical to SecondString, then 0 is returned. Otherwise, the value returned\r
+ is the first mismatched ASCII character in SecondString subtracted from the\r
+ first mismatched ASCII character in FirstString.\r
+\r
+ If Length > 0 and FirstString is NULL, then ASSERT().\r
+ If Length > 0 and SecondString is NULL, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than \r
+ PcdMaximumAsciiStringLength, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and FirstString contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and SecondString contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param FirstString A pointer to a Null-terminated ASCII string.\r
+ @param SecondString A pointer to a Null-terminated ASCII string.\r
+ @param Length The maximum number of ASCII characters for compare.\r
+ \r
+ @retval ==0 FirstString is identical to SecondString.\r
+ @retval !=0 FirstString is not identical to SecondString.\r
+\r
+**/\r
+INTN\r
+EFIAPI\r
+AsciiStrnCmp (\r
+ IN CONST CHAR8 *FirstString,\r
+ IN CONST CHAR8 *SecondString,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ if (Length == 0) {\r
+ return 0;\r
+ }\r
+\r
+ //\r
+ // ASSERT both strings are less long than PcdMaximumAsciiStringLength\r
+ //\r
+ ASSERT (AsciiStrSize (FirstString));\r
+ ASSERT (AsciiStrSize (SecondString));\r
+\r
+ if (PcdGet32 (PcdMaximumAsciiStringLength) != 0) {\r
+ ASSERT (Length <= PcdGet32 (PcdMaximumAsciiStringLength));\r
+ }\r
+\r
+ while ((*FirstString != '\0') &&\r
+ (*FirstString == *SecondString) &&\r
+ (Length > 1)) {\r
+ FirstString++;\r
+ SecondString++;\r
+ Length--;\r
+ }\r
+ return *FirstString - *SecondString;\r
+}\r
+\r
+/**\r
+ Concatenates one Null-terminated ASCII string to another Null-terminated\r
+ ASCII string, and returns the concatenated ASCII string.\r
+\r
+ This function concatenates two Null-terminated ASCII strings. The contents of\r
+ Null-terminated ASCII string Source are concatenated to the end of Null-\r
+ terminated ASCII string Destination. The Null-terminated concatenated ASCII\r
+ String is returned.\r
+\r
+ If Destination is NULL, then ASSERT().\r
+ If Source is NULL, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero and Destination contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero and Source contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero and concatenating Destination and\r
+ Source results in a ASCII string with more than PcdMaximumAsciiStringLength\r
+ ASCII characters, then ASSERT().\r
+\r
+ @param Destination A pointer to a Null-terminated ASCII string.\r
+ @param Source A pointer to a Null-terminated ASCII string.\r
+\r
+ @return Destination\r
+\r
+**/\r
+CHAR8 *\r
+EFIAPI\r
+AsciiStrCat (\r
+ IN OUT CHAR8 *Destination,\r
+ IN CONST CHAR8 *Source\r
+ )\r
+{\r
+ AsciiStrCpy (Destination + AsciiStrLen (Destination), Source);\r
+\r
+ //\r
+ // Size of the resulting string should never be zero.\r
+ // PcdMaximumUnicodeStringLength is tested inside StrLen().\r
+ //\r
+ ASSERT (AsciiStrSize (Destination) != 0);\r
+ return Destination;\r
+}\r
+\r
+/**\r
+ Concatenates up to a specified length one Null-terminated ASCII string to \r
+ the end of another Null-terminated ASCII string, and returns the \r
+ concatenated ASCII string.\r
+\r
+ This function concatenates two Null-terminated ASCII strings. The contents\r
+ of Null-terminated ASCII string Source are concatenated to the end of Null-\r
+ terminated ASCII string Destination, and Destination is returned. At most,\r
+ Length ASCII characters are concatenated from Source to the end of\r
+ Destination, and Destination is always Null-terminated. If Length is 0, then\r
+ Destination is returned unmodified. If Source and Destination overlap, then\r
+ the results are undefined.\r
+\r
+ If Length > 0 and Destination is NULL, then ASSERT().\r
+ If Length > 0 and Source is NULL, then ASSERT().\r
+ If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than\r
+ PcdMaximumAsciiStringLength, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Destination contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Source contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and concatenating Destination and\r
+ Source results in a ASCII string with more than PcdMaximumAsciiStringLength\r
+ ASCII characters, not including the Null-terminator, then ASSERT().\r
+\r
+ @param Destination A pointer to a Null-terminated ASCII string.\r
+ @param Source A pointer to a Null-terminated ASCII string.\r
+ @param Length The maximum number of ASCII characters to concatenate from\r
+ Source.\r
+\r
+ @return Destination\r
+\r
+**/\r
+CHAR8 *\r
+EFIAPI\r
+AsciiStrnCat (\r
+ IN OUT CHAR8 *Destination,\r
+ IN CONST CHAR8 *Source,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINTN DestinationLen;\r
+\r
+ DestinationLen = AsciiStrLen (Destination);\r
+ AsciiStrnCpy (Destination + DestinationLen, Source, Length);\r
+ Destination[DestinationLen + Length] = '\0';\r
+\r
+ //\r
+ // Size of the resulting string should never be zero.\r
+ // PcdMaximumUnicodeStringLength is tested inside StrLen().\r
+ //\r
+ ASSERT (AsciiStrSize (Destination) != 0);\r
+ return Destination;\r
+}\r
+\r
+/**\r
+ Returns the first occurrence of a Null-terminated ASCII sub-string\r
+ in a Null-terminated ASCII string.\r
+\r
+ This function scans the contents of the ASCII string specified by String\r
+ and returns the first occurrence of SearchString. If SearchString is not\r
+ found in String, then NULL is returned. If the length of SearchString is zero,\r
+ then String is returned.\r
+\r
+ If String is NULL, then ASSERT().\r
+ If SearchString is NULL, then ASSERT().\r
+\r
+ If PcdMaximumAsciiStringLength is not zero, and SearchString or\r
+ String contains more than PcdMaximumAsciiStringLength Unicode characters\r
+ not including the Null-terminator, then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated ASCII string.\r
+ @param SearchString A pointer to a Null-terminated ASCII string to search for.\r
+\r
+ @retval NULL If the SearchString does not appear in String.\r
+ @retval others If there is a match return the first occurrence of SearchingString.\r
+ If the length of SearchString is zero,return String.\r
+\r
+**/\r
+CHAR8 *\r
+EFIAPI\r
+AsciiStrStr (\r
+ IN CONST CHAR8 *String,\r
+ IN CONST CHAR8 *SearchString\r
+ )\r
+{\r
+ CONST CHAR8 *FirstMatch;\r
+ CONST CHAR8 *SearchStringTmp;\r
+\r
+ //\r
+ // ASSERT both strings are less long than PcdMaximumAsciiStringLength\r
+ //\r
+ ASSERT (AsciiStrSize (String) != 0);\r
+ ASSERT (AsciiStrSize (SearchString) != 0);\r
+\r
+ if (*SearchString == '\0') {\r
+ return (CHAR8 *) String;\r
+ }\r
+\r
+ while (*String != '\0') {\r
+ SearchStringTmp = SearchString;\r
+ FirstMatch = String;\r
+ \r
+ while ((*String == *SearchStringTmp) \r
+ && (*String != '\0')) {\r
+ String++;\r
+ SearchStringTmp++;\r
+ } \r
+ \r
+ if (*SearchStringTmp == '\0') {\r
+ return (CHAR8 *) FirstMatch;\r
+ }\r
+\r
+ if (*String == '\0') {\r
+ return NULL;\r
+ }\r
+\r
+ String = FirstMatch + 1;\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ Convert a Null-terminated ASCII decimal string to a value of type\r
+ UINTN.\r
+\r
+ This function returns a value of type UINTN by interpreting the contents\r
+ of the ASCII string String as a decimal number. The format of the input\r
+ ASCII string String is:\r
+\r
+ [spaces] [decimal digits].\r
+\r
+ The valid decimal digit character is in the range [0-9]. The function will\r
+ ignore the pad space, which includes spaces or tab characters, before the digits.\r
+ The running zero in the beginning of [decimal digits] will be ignored. Then, the\r
+ function stops at the first character that is a not a valid decimal character or\r
+ Null-terminator, whichever on comes first.\r
+\r
+ If String has only pad spaces, then 0 is returned.\r
+ If String has no pad spaces or valid decimal digits, then 0 is returned.\r
+ If the number represented by String overflows according to the range defined by\r
+ UINTN, then ASSERT().\r
+ If String is NULL, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and String contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated ASCII string.\r
+\r
+ @retval Value translated from String.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsciiStrDecimalToUintn (\r
+ IN CONST CHAR8 *String\r
+ )\r
+{\r
+ UINTN Result;\r
+ \r
+ //\r
+ // ASSERT Strings is less long than PcdMaximumAsciiStringLength\r
+ //\r
+ ASSERT (AsciiStrSize (String) != 0);\r
+\r
+ //\r
+ // Ignore the pad spaces (space or tab)\r
+ //\r
+ while ((*String == ' ') || (*String == '\t' )) {\r
+ String++;\r
+ }\r
+\r
+ //\r
+ // Ignore leading Zeros after the spaces\r
+ //\r
+ while (*String == '0') {\r
+ String++;\r
+ }\r
+\r
+ Result = 0;\r
+\r
+ while (InternalAsciiIsDecimalDigitCharacter (*String)) {\r
+ //\r
+ // If the number represented by String overflows according \r
+ // to the range defined by UINTN, then ASSERT().\r
+ //\r
+ ASSERT ((Result < QUOTIENT_MAX_UINTN_DIVIDED_BY_10) ||\r
+ ((Result == QUOTIENT_MAX_UINTN_DIVIDED_BY_10) && \r
+ (*String - '0') <= REMAINDER_MAX_UINTN_DIVIDED_BY_10)\r
+ );\r
+\r
+ Result = Result * 10 + (*String - '0');\r
+ String++;\r
+ }\r
+ \r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ Convert a Null-terminated ASCII decimal string to a value of type\r
+ UINT64.\r
+\r
+ This function returns a value of type UINT64 by interpreting the contents\r
+ of the ASCII string String as a decimal number. The format of the input\r
+ ASCII string String is:\r
+\r
+ [spaces] [decimal digits].\r
+\r
+ The valid decimal digit character is in the range [0-9]. The function will\r
+ ignore the pad space, which includes spaces or tab characters, before the digits.\r
+ The running zero in the beginning of [decimal digits] will be ignored. Then, the\r
+ function stops at the first character that is a not a valid decimal character or\r
+ Null-terminator, whichever on comes first.\r
+\r
+ If String has only pad spaces, then 0 is returned.\r
+ If String has no pad spaces or valid decimal digits, then 0 is returned.\r
+ If the number represented by String overflows according to the range defined by\r
+ UINT64, then ASSERT().\r
+ If String is NULL, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and String contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated ASCII string.\r
+\r
+ @retval Value translated from String.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsciiStrDecimalToUint64 (\r
+ IN CONST CHAR8 *String\r
+ )\r
+{\r
+ UINT64 Result;\r
+ \r
+ //\r
+ // ASSERT Strings is less long than PcdMaximumAsciiStringLength\r
+ //\r
+ ASSERT (AsciiStrSize (String) != 0);\r
+\r
+ //\r
+ // Ignore the pad spaces (space or tab)\r
+ //\r
+ while ((*String == ' ') || (*String == '\t' )) {\r
+ String++;\r
+ }\r
+\r
+ //\r
+ // Ignore leading Zeros after the spaces\r
+ //\r
+ while (*String == '0') {\r
+ String++;\r
+ }\r
+\r
+ Result = 0;\r
+\r
+ while (InternalAsciiIsDecimalDigitCharacter (*String)) {\r
+ //\r
+ // If the number represented by String overflows according \r
+ // to the range defined by UINTN, then ASSERT().\r
+ //\r
+ ASSERT ((Result < QUOTIENT_MAX_UINT64_DIVIDED_BY_10) || \r
+ ((Result == QUOTIENT_MAX_UINT64_DIVIDED_BY_10) && \r
+ (*String - '0') <= REMAINDER_MAX_UINT64_DIVIDED_BY_10)\r
+ );\r
+\r
+ Result = MultU64x32 (Result, 10) + (*String - '0');\r
+ String++;\r
+ }\r
+ \r
+ return Result;\r
+}\r
+\r
+/**\r
+ Convert a Null-terminated ASCII hexadecimal string to a value of type UINTN.\r
+\r
+ This function returns a value of type UINTN by interpreting the contents of\r
+ the ASCII string String as a hexadecimal number. The format of the input ASCII\r
+ string String is:\r
+\r
+ [spaces][zeros][x][hexadecimal digits].\r
+\r
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].\r
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If "x"\r
+ appears in the input string, it must be prefixed with at least one 0. The function\r
+ will ignore the pad space, which includes spaces or tab characters, before [zeros],\r
+ [x] or [hexadecimal digits]. The running zero before [x] or [hexadecimal digits]\r
+ will be ignored. Then, the decoding starts after [x] or the first valid hexadecimal\r
+ digit. Then, the function stops at the first character that is a not a valid\r
+ hexadecimal character or Null-terminator, whichever on comes first.\r
+\r
+ If String has only pad spaces, then 0 is returned.\r
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits, then\r
+ 0 is returned.\r
+\r
+ If the number represented by String overflows according to the range defined by UINTN,\r
+ then ASSERT().\r
+ If String is NULL, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero,\r
+ and String contains more than PcdMaximumAsciiStringLength ASCII characters not including\r
+ the Null-terminator, then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated ASCII string.\r
+\r
+ @retval Value translated from String.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsciiStrHexToUintn (\r
+ IN CONST CHAR8 *String\r
+ )\r
+{\r
+ UINTN Result;\r
+\r
+ //\r
+ // ASSERT Strings is less long than PcdMaximumAsciiStringLength\r
+ //\r
+ ASSERT (AsciiStrSize (String) != 0);\r
+ \r
+ //\r
+ // Ignore the pad spaces (space or tab) \r
+ //\r
+ while ((*String == ' ') || (*String == '\t' )) {\r
+ String++;\r
+ }\r
+\r
+ //\r
+ // Ignore leading Zeros after the spaces\r
+ //\r
+ while (*String == '0') {\r
+ String++;\r
+ }\r
+\r
+ if (InternalBaseLibAsciiToUpper (*String) == 'X') {\r
+ ASSERT (*(String - 1) == '0');\r
+ if (*(String - 1) != '0') {\r
+ return 0;\r
+ }\r
+ //\r
+ // Skip the 'X'\r
+ //\r
+ String++;\r
+ }\r
+\r
+ Result = 0;\r
+ \r
+ while (InternalAsciiIsHexaDecimalDigitCharacter (*String)) {\r
+ //\r
+ // If the Hex Number represented by String overflows according \r
+ // to the range defined by UINTN, then ASSERT().\r
+ //\r
+ ASSERT ((Result < QUOTIENT_MAX_UINTN_DIVIDED_BY_16) ||\r
+ ((Result == QUOTIENT_MAX_UINTN_DIVIDED_BY_16) && \r
+ (InternalAsciiHexCharToUintn (*String) <= REMAINDER_MAX_UINTN_DIVIDED_BY_16))\r
+ );\r
+\r
+ Result = (Result << 4) + InternalAsciiHexCharToUintn (*String);\r
+ String++;\r
+ }\r
+\r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ Convert a Null-terminated ASCII hexadecimal string to a value of type UINT64.\r
+\r
+ This function returns a value of type UINT64 by interpreting the contents of\r
+ the ASCII string String as a hexadecimal number. The format of the input ASCII\r
+ string String is:\r
+\r
+ [spaces][zeros][x][hexadecimal digits].\r
+\r
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].\r
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If "x"\r
+ appears in the input string, it must be prefixed with at least one 0. The function\r
+ will ignore the pad space, which includes spaces or tab characters, before [zeros],\r
+ [x] or [hexadecimal digits]. The running zero before [x] or [hexadecimal digits]\r
+ will be ignored. Then, the decoding starts after [x] or the first valid hexadecimal\r
+ digit. Then, the function stops at the first character that is a not a valid\r
+ hexadecimal character or Null-terminator, whichever on comes first.\r
+\r
+ If String has only pad spaces, then 0 is returned.\r
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits, then\r
+ 0 is returned.\r
+\r
+ If the number represented by String overflows according to the range defined by UINT64,\r
+ then ASSERT().\r
+ If String is NULL, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero,\r
+ and String contains more than PcdMaximumAsciiStringLength ASCII characters not including\r
+ the Null-terminator, then ASSERT().\r
+\r
+ @param String A pointer to a Null-terminated ASCII string.\r
+\r
+ @retval Value translated from String.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsciiStrHexToUint64 (\r
+ IN CONST CHAR8 *String\r
+ )\r
+{\r
+ UINT64 Result;\r
+\r
+ //\r
+ // ASSERT Strings is less long than PcdMaximumAsciiStringLength\r
+ //\r
+ ASSERT (AsciiStrSize (String) != 0);\r
+ \r
+ //\r
+ // Ignore the pad spaces (space or tab) and leading Zeros\r
+ //\r
+ //\r
+ // Ignore the pad spaces (space or tab) \r
+ //\r
+ while ((*String == ' ') || (*String == '\t' )) {\r
+ String++;\r
+ }\r
+\r
+ //\r
+ // Ignore leading Zeros after the spaces\r
+ //\r
+ while (*String == '0') {\r
+ String++;\r
+ }\r
+\r
+ if (InternalBaseLibAsciiToUpper (*String) == 'X') {\r
+ ASSERT (*(String - 1) == '0');\r
+ if (*(String - 1) != '0') {\r
+ return 0;\r
+ }\r
+ //\r
+ // Skip the 'X'\r
+ //\r
+ String++;\r
+ }\r
+\r
+ Result = 0;\r
+ \r
+ while (InternalAsciiIsHexaDecimalDigitCharacter (*String)) {\r
+ //\r
+ // If the Hex Number represented by String overflows according \r
+ // to the range defined by UINTN, then ASSERT().\r
+ //\r
+ ASSERT ((Result < QUOTIENT_MAX_UINT64_DIVIDED_BY_16) ||\r
+ ((Result == QUOTIENT_MAX_UINT64_DIVIDED_BY_16) && \r
+ (InternalAsciiHexCharToUintn (*String) <= REMAINDER_MAX_UINT64_DIVIDED_BY_16))\r
+ );\r
+\r
+ Result = LShiftU64 (Result, 4);\r
+ Result = Result + InternalAsciiHexCharToUintn (*String);\r
+ String++;\r
+ }\r
+\r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ Convert one Null-terminated ASCII string to a Null-terminated\r
+ Unicode string and returns the Unicode string.\r
+\r
+ This function converts the contents of the ASCII string Source to the Unicode\r
+ string Destination, and returns Destination. The function terminates the\r
+ Unicode string Destination by appending a Null-terminator character at the end.\r
+ The caller is responsible to make sure Destination points to a buffer with size\r
+ equal or greater than ((AsciiStrLen (Source) + 1) * sizeof (CHAR16)) in bytes.\r
+\r
+ If Destination is NULL, then ASSERT().\r
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Source is NULL, then ASSERT().\r
+ If Source and Destination overlap, then ASSERT().\r
+ If PcdMaximumAsciiStringLength is not zero, and Source contains more than\r
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,\r
+ then ASSERT().\r
+ If PcdMaximumUnicodeStringLength is not zero, and Source contains more than\r
+ PcdMaximumUnicodeStringLength ASCII characters not including the\r
+ Null-terminator, then ASSERT().\r
+\r
+ @param Source A pointer to a Null-terminated ASCII string.\r
+ @param Destination A pointer to a Null-terminated Unicode string.\r
+\r
+ @return Destination.\r
+\r
+**/\r
+CHAR16 *\r
+EFIAPI\r
+AsciiStrToUnicodeStr (\r
+ IN CONST CHAR8 *Source,\r
+ OUT CHAR16 *Destination\r
+ )\r
+{\r
+ CHAR16 *ReturnValue;\r
+\r
+ ASSERT (Destination != NULL);\r
+\r
+ //\r
+ // ASSERT Source is less long than PcdMaximumAsciiStringLength\r
+ //\r
+ ASSERT (AsciiStrSize (Source) != 0);\r
+\r
+ //\r
+ // Source and Destination should not overlap\r
+ //\r
+ ASSERT ((UINTN) ((CHAR8 *) Destination - Source) > AsciiStrLen (Source));\r
+ ASSERT ((UINTN) (Source - (CHAR8 *) Destination) > (AsciiStrLen (Source) * sizeof (CHAR16)));\r
+\r
+ \r
+ ReturnValue = Destination;\r
+ while (*Source != '\0') {\r
+ *(Destination++) = (CHAR16) *(Source++);\r
+ }\r
+ //\r
+ // End the Destination with a NULL.\r
+ //\r
+ *Destination = '\0';\r
+\r
+ //\r
+ // ASSERT Original Destination is less long than PcdMaximumUnicodeStringLength\r
+ //\r
+ ASSERT (StrSize (ReturnValue) != 0);\r
+\r
+ return ReturnValue;\r
+}\r
+\r
+/**\r
+ Converts an 8-bit value to an 8-bit BCD value.\r
+\r
+ Converts the 8-bit value specified by Value to BCD. The BCD value is\r
+ returned.\r
+\r
+ If Value >= 100, then ASSERT().\r
+\r
+ @param Value The 8-bit value to convert to BCD. Range 0..99.\r
+\r
+ @return The BCD value.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+DecimalToBcd8 (\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ ASSERT (Value < 100);\r
+ return (UINT8) (((Value / 10) << 4) | (Value % 10));\r
+}\r
+\r
+/**\r
+ Converts an 8-bit BCD value to an 8-bit value.\r
+\r
+ Converts the 8-bit BCD value specified by Value to an 8-bit value. The 8-bit\r
+ value is returned.\r
+\r
+ If Value >= 0xA0, then ASSERT().\r
+ If (Value & 0x0F) >= 0x0A, then ASSERT().\r
+\r
+ @param Value The 8-bit BCD value to convert to an 8-bit value.\r
+\r
+ @return The 8-bit value is returned.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+BcdToDecimal8 (\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ ASSERT (Value < 0xa0);\r
+ ASSERT ((Value & 0xf) < 0xa);\r
+ return (UINT8) ((Value >> 4) * 10 + (Value & 0xf));\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Switches the endianess of a 16-bit integer.\r
+\r
+ This function swaps the bytes in a 16-bit unsigned value to switch the value\r
+ from little endian to big endian or vice versa. The byte swapped value is\r
+ returned.\r
+\r
+ @param Value A 16-bit unsigned value.\r
+\r
+ @return The byte swapped Value.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+SwapBytes16 (\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ return (UINT16) ((Value<< 8) | (Value>> 8));\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Switches the endianess of a 32-bit integer.\r
+\r
+ This function swaps the bytes in a 32-bit unsigned value to switch the value\r
+ from little endian to big endian or vice versa. The byte swapped value is\r
+ returned.\r
+\r
+ @param Value A 32-bit unsigned value.\r
+\r
+ @return The byte swapped Value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+SwapBytes32 (\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ UINT32 LowerBytes;\r
+ UINT32 HigherBytes;\r
+\r
+ LowerBytes = (UINT32) SwapBytes16 ((UINT16) Value);\r
+ HigherBytes = (UINT32) SwapBytes16 ((UINT16) (Value >> 16));\r
+\r
+ return (LowerBytes << 16 | HigherBytes);\r
+}\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Switches the endianess of a 64-bit integer.\r
+\r
+ This function swaps the bytes in a 64-bit unsigned value to switch the value\r
+ from little endian to big endian or vice versa. The byte swapped value is\r
+ returned.\r
+\r
+ @param Value A 64-bit unsigned value.\r
+\r
+ @return The byte swapped Value.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+SwapBytes64 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ return InternalMathSwapBytes64 (Value);\r
+}\r
--- /dev/null
+/** @file\r
+ Switch Stack functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the\r
+ new stack specified by NewStack and passing in the parameters specified\r
+ by Context1 and Context2. Context1 and Context2 are optional and may\r
+ be NULL. The function EntryPoint must never return. This function\r
+ supports a variable number of arguments following the NewStack parameter.\r
+ These additional arguments are ignored on IA-32, x64, and EBC.\r
+ IPF CPUs expect one additional parameter of type VOID * that specifies\r
+ the new backing store pointer.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param ... This variable argument list is ignored for IA32, x64, and EBC. \r
+ For IPF, this variable argument list is expected to contain \r
+ a single parameter of type VOID * that specifies the new backing \r
+ store pointer.\r
+\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SwitchStack (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack,\r
+ ...\r
+ )\r
+{\r
+ VA_LIST Marker;\r
+\r
+ ASSERT (EntryPoint != NULL);\r
+ ASSERT (NewStack != NULL);\r
+\r
+ //\r
+ // New stack must be aligned with CPU_STACK_ALIGNMENT\r
+ //\r
+ ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);\r
+\r
+ VA_START (Marker, NewStack);\r
+\r
+ InternalSwitchStack (EntryPoint, Context1, Context2, NewStack, Marker);\r
+\r
+ VA_END (Marker);\r
+\r
+ //\r
+ // InternalSwitchStack () will never return\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
--- /dev/null
+/** @file\r
+ Unaligned access functions of BaseLib.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+\r
+/**\r
+ Reads a 16-bit value from memory that may be unaligned.\r
+\r
+ This function returns the 16-bit value pointed to by Buffer. The function\r
+ guarantees that the read operation does not produce an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer A pointer to a 16-bit value that may be unaligned.\r
+\r
+ @return The 16-bit value read from Buffer.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+ReadUnaligned16 (\r
+ IN CONST UINT16 *Buffer\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ return *Buffer;\r
+}\r
+\r
+/**\r
+ Writes a 16-bit value to memory that may be unaligned.\r
+\r
+ This function writes the 16-bit value specified by Value to Buffer. Value is\r
+ returned. The function guarantees that the write operation does not produce\r
+ an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer A pointer to a 16-bit value that may be unaligned.\r
+ @param Value 16-bit value to write to Buffer.\r
+\r
+ @return The 16-bit value to write to Buffer.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+WriteUnaligned16 (\r
+ OUT UINT16 *Buffer,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ return *Buffer = Value;\r
+}\r
+\r
+/**\r
+ Reads a 24-bit value from memory that may be unaligned.\r
+\r
+ This function returns the 24-bit value pointed to by Buffer. The function\r
+ guarantees that the read operation does not produce an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer A pointer to a 24-bit value that may be unaligned.\r
+\r
+ @return The 24-bit value read from Buffer.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+ReadUnaligned24 (\r
+ IN CONST UINT32 *Buffer\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ return *Buffer & 0xffffff;\r
+}\r
+\r
+/**\r
+ Writes a 24-bit value to memory that may be unaligned.\r
+\r
+ This function writes the 24-bit value specified by Value to Buffer. Value is\r
+ returned. The function guarantees that the write operation does not produce\r
+ an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer A pointer to a 24-bit value that may be unaligned.\r
+ @param Value 24-bit value to write to Buffer.\r
+\r
+ @return The 24-bit value to write to Buffer.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+WriteUnaligned24 (\r
+ OUT UINT32 *Buffer,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ *Buffer = BitFieldWrite32 (*Buffer, 0, 23, Value);\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit value from memory that may be unaligned.\r
+\r
+ This function returns the 32-bit value pointed to by Buffer. The function\r
+ guarantees that the read operation does not produce an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer A pointer to a 32-bit value that may be unaligned.\r
+\r
+ @return The 32-bit value read from Buffer.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+ReadUnaligned32 (\r
+ IN CONST UINT32 *Buffer\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ return *Buffer;\r
+}\r
+\r
+/**\r
+ Writes a 32-bit value to memory that may be unaligned.\r
+\r
+ This function writes the 32-bit value specified by Value to Buffer. Value is\r
+ returned. The function guarantees that the write operation does not produce\r
+ an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer A pointer to a 32-bit value that may be unaligned.\r
+ @param Value The 32-bit value to write to Buffer.\r
+\r
+ @return The 32-bit value to write to Buffer.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+WriteUnaligned32 (\r
+ OUT UINT32 *Buffer,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ return *Buffer = Value;\r
+}\r
+\r
+/**\r
+ Reads a 64-bit value from memory that may be unaligned.\r
+\r
+ This function returns the 64-bit value pointed to by Buffer. The function\r
+ guarantees that the read operation does not produce an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer A pointer to a 64-bit value that may be unaligned.\r
+\r
+ @return The 64-bit value read from Buffer.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+ReadUnaligned64 (\r
+ IN CONST UINT64 *Buffer\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ return *Buffer;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit value to memory that may be unaligned.\r
+\r
+ This function writes the 64-bit value specified by Value to Buffer. Value is\r
+ returned. The function guarantees that the write operation does not produce\r
+ an alignment fault.\r
+\r
+ If the Buffer is NULL, then ASSERT().\r
+\r
+ @param Buffer A pointer to a 64-bit value that may be unaligned.\r
+ @param Value The 64-bit value to write to Buffer.\r
+\r
+ @return The 64-bit value to write to Buffer.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+WriteUnaligned64 (\r
+ OUT UINT64 *Buffer,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+\r
+ return *Buffer = Value;\r
+}\r
--- /dev/null
+## @file\r
+# Base Library implementation for X64 UnixPkg. X64 code writes CR3 so to\r
+# not change MdeModulePkg DxeIpl we need a UnixPkg copy of the BaseLib.\r
+# \r
+# Currently I'm debugging UnixPkg with SVR V ABI so there are some \r
+# temp changes for that too.\r
+#\r
+#\r
+# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BaseLib\r
+ FILE_GUID = 27d67720-ea68-48ae-93da-a3a074c90e30\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = BaseLib \r
+\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM\r
+#\r
+\r
+[Sources]\r
+ CheckSum.c\r
+ SwitchStack.c\r
+ SwapBytes64.c\r
+ SwapBytes32.c\r
+ SwapBytes16.c\r
+ LongJump.c\r
+ SetJump.c\r
+ RShiftU64.c\r
+ RRotU64.c\r
+ RRotU32.c\r
+ MultU64x64.c\r
+ MultU64x32.c\r
+ MultS64x64.c\r
+ ModU64x32.c\r
+ LShiftU64.c\r
+ LRotU64.c\r
+ LRotU32.c\r
+ LowBitSet64.c\r
+ LowBitSet32.c\r
+ HighBitSet64.c\r
+ HighBitSet32.c\r
+ GetPowerOfTwo64.c\r
+ GetPowerOfTwo32.c\r
+ DivU64x64Remainder.c\r
+ DivU64x32Remainder.c\r
+ DivU64x32.c\r
+ DivS64x64Remainder.c\r
+ ARShiftU64.c\r
+ BitField.c\r
+ CpuDeadLoop.c\r
+ Cpu.c\r
+ LinkedList.c\r
+ String.c\r
+ BaseLibInternals.h\r
+\r
+\r
+[Sources.X64]\r
+ X64/Thunk16.asm\r
+ X64/CpuPause.asm\r
+ X64/EnableDisableInterrupts.asm\r
+ X64/DisableInterrupts.asm\r
+ X64/EnableInterrupts.asm\r
+ X64/FlushCacheLine.asm\r
+ X64/Invd.asm\r
+ X64/Wbinvd.asm\r
+ X64/DisablePaging64.asm\r
+ X64/Mwait.asm\r
+ X64/Monitor.asm\r
+ X64/ReadPmc.asm\r
+ X64/ReadTsc.asm\r
+ X64/WriteMm7.asm\r
+ X64/WriteMm6.asm\r
+ X64/WriteMm5.asm\r
+ X64/WriteMm4.asm\r
+ X64/WriteMm3.asm\r
+ X64/WriteMm2.asm\r
+ X64/WriteMm1.asm\r
+ X64/WriteMm0.asm\r
+ X64/ReadMm7.asm\r
+ X64/ReadMm6.asm\r
+ X64/ReadMm5.asm\r
+ X64/ReadMm4.asm\r
+ X64/ReadMm3.asm\r
+ X64/ReadMm2.asm\r
+ X64/ReadMm1.asm\r
+ X64/ReadMm0.asm\r
+ X64/FxRestore.asm\r
+ X64/FxSave.asm\r
+ X64/WriteLdtr.asm\r
+ X64/ReadLdtr.asm\r
+ X64/WriteIdtr.asm\r
+ X64/ReadIdtr.asm\r
+ X64/WriteGdtr.asm\r
+ X64/ReadGdtr.asm\r
+ X64/ReadTr.asm\r
+ X64/ReadSs.asm\r
+ X64/ReadGs.asm\r
+ X64/ReadFs.asm\r
+ X64/ReadEs.asm\r
+ X64/ReadDs.asm\r
+ X64/ReadCs.asm\r
+ X64/WriteDr7.asm\r
+ X64/WriteDr6.asm\r
+ X64/WriteDr5.asm\r
+ X64/WriteDr4.asm\r
+ X64/WriteDr3.asm\r
+ X64/WriteDr2.asm\r
+ X64/WriteDr1.asm\r
+ X64/WriteDr0.asm\r
+ X64/ReadDr7.asm\r
+ X64/ReadDr6.asm\r
+ X64/ReadDr5.asm\r
+ X64/ReadDr4.asm\r
+ X64/ReadDr3.asm\r
+ X64/ReadDr2.asm\r
+ X64/ReadDr1.asm\r
+ X64/ReadDr0.asm\r
+ X64/WriteCr4.asm\r
+ X64/WriteCr3.asm\r
+ X64/WriteCr2.asm\r
+ X64/WriteCr0.asm\r
+ X64/ReadCr4.asm\r
+ X64/ReadCr3.asm\r
+ X64/ReadCr2.asm\r
+ X64/ReadCr0.asm\r
+ X64/ReadEflags.asm\r
+ X64/CpuIdEx.asm\r
+ X64/CpuId.asm\r
+ X64/LongJump.asm\r
+ X64/SetJump.asm\r
+ X64/SwitchStack.asm\r
+ X64/EnableCache.asm\r
+ X64/DisableCache.asm\r
+\r
+ X64/CpuBreakpoint.c | MSFT \r
+ X64/WriteMsr64.c | MSFT \r
+ X64/ReadMsr64.c | MSFT \r
+\r
+ X64/CpuBreakpoint.asm | INTEL \r
+ X64/WriteMsr64.asm | INTEL \r
+ X64/ReadMsr64.asm | INTEL \r
+\r
+ X64/Non-existing.c\r
+ Math64.c\r
+ Unaligned.c\r
+ X86WriteIdtr.c\r
+ X86WriteGdtr.c\r
+ X86Thunk.c\r
+ X86ReadIdtr.c\r
+ X86ReadGdtr.c\r
+ X86Msr.c\r
+ X86MemoryFence.c | MSFT\r
+ X86MemoryFence.c | INTEL\r
+ X86GetInterruptState.c\r
+ X86FxSave.c\r
+ X86FxRestore.c\r
+ X86EnablePaging64.c\r
+ X86EnablePaging32.c\r
+ X86DisablePaging64.c\r
+ X86DisablePaging32.c\r
+ X64/GccInline.c | GCC\r
+ X64/Thunk16.S | GCC \r
+ X64/SwitchStack.S | GCC \r
+ X64/SetJump.S | GCC \r
+ X64/LongJump.S | GCC \r
+ X64/EnableDisableInterrupts.S | GCC \r
+ X64/DisablePaging64.S | GCC \r
+ X64/CpuId.S | GCC \r
+ X64/CpuIdEx.S | GCC \r
+ X64/EnableCache.S | GCC\r
+ X64/DisableCache.S | GCC\r
+ ChkStkGcc.c | GCC \r
+\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+ PcdLib\r
+ DebugLib\r
+ BaseMemoryLib\r
+\r
+[Pcd]\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength\r
+ gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# CpuBreakpoint.S\r
+#\r
+# Abstract:\r
+#\r
+# Implementation of CpuBreakpoint() on x86_64\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(CpuBreakpoint)\r
+ASM_PFX(CpuBreakpoint):\r
+ int $0x3\r
+ ret\r
--- /dev/null
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; CpuBreakpoint.Asm\r
+;\r
+; Abstract:\r
+;\r
+; CpuBreakpoint function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; CpuBreakpoint (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+CpuBreakpoint PROC\r
+ int 3\r
+ ret\r
+CpuBreakpoint ENDP\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+ CpuBreakpoint function.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+/**\r
+ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
+**/\r
+\r
+void __debugbreak ();\r
+\r
+#pragma intrinsic(__debugbreak)\r
+\r
+/**\r
+ Generates a breakpoint on the CPU.\r
+\r
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+ that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+ VOID\r
+ )\r
+{\r
+ __debugbreak ();\r
+}\r
+\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# CpuId.S\r
+#\r
+# Abstract:\r
+#\r
+# AsmCpuid function\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# AsmCpuid (\r
+# IN UINT32 RegisterInEax,\r
+# OUT UINT32 *RegisterOutEax OPTIONAL,\r
+# OUT UINT32 *RegisterOutEbx OPTIONAL,\r
+# OUT UINT32 *RegisterOutEcx OPTIONAL,\r
+# OUT UINT32 *RegisterOutEdx OPTIONAL\r
+# )\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(AsmCpuid)\r
+ASM_PFX(AsmCpuid):\r
+ push %rbx\r
+ mov %ecx, %eax\r
+ push %rax # save Index on stack\r
+ push %rdx\r
+ cpuid\r
+ test %r9, %r9\r
+ jz L1\r
+ mov %ecx, (%r9)\r
+L1:\r
+ pop %rcx\r
+ jrcxz L2\r
+ mov %eax, (%rcx)\r
+L2:\r
+ mov %r8, %rcx\r
+ jrcxz L3\r
+ mov %ebx, (%rcx)\r
+L3:\r
+ mov 0x38(%rsp), %rcx\r
+ jrcxz L4\r
+ mov %edx, (%rcx)\r
+L4:\r
+ pop %rax # restore Index to rax as return value\r
+ pop %rbx\r
+ ret\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; CpuId.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmCpuid function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmCpuid (\r
+; IN UINT32 RegisterInEax,\r
+; OUT UINT32 *RegisterOutEax OPTIONAL,\r
+; OUT UINT32 *RegisterOutEbx OPTIONAL,\r
+; OUT UINT32 *RegisterOutEcx OPTIONAL,\r
+; OUT UINT32 *RegisterOutEdx OPTIONAL\r
+; )\r
+;------------------------------------------------------------------------------\r
+AsmCpuid PROC USES rbx\r
+ mov eax, ecx\r
+ push rax ; save Index on stack\r
+ push rdx\r
+ cpuid\r
+ test r9, r9\r
+ jz @F\r
+ mov [r9], ecx\r
+@@:\r
+ pop rcx\r
+ jrcxz @F\r
+ mov [rcx], eax\r
+@@:\r
+ mov rcx, r8\r
+ jrcxz @F\r
+ mov [rcx], ebx\r
+@@:\r
+ mov rcx, [rsp + 38h]\r
+ jrcxz @F\r
+ mov [rcx], edx\r
+@@:\r
+ pop rax ; restore Index to rax as return value\r
+ ret\r
+AsmCpuid ENDP\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# CpuIdEx.S\r
+#\r
+# Abstract:\r
+#\r
+# AsmCpuidEx function\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#------------------------------------------------------------------------------\r
+# UINT32\r
+# EFIAPI\r
+# AsmCpuidEx (\r
+# IN UINT32 RegisterInEax,\r
+# IN UINT32 RegisterInEcx,\r
+# OUT UINT32 *RegisterOutEax OPTIONAL,\r
+# OUT UINT32 *RegisterOutEbx OPTIONAL,\r
+# OUT UINT32 *RegisterOutEcx OPTIONAL,\r
+# OUT UINT32 *RegisterOutEdx OPTIONAL\r
+# )\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(AsmCpuidEx)\r
+ASM_PFX(AsmCpuidEx):\r
+ push %rbx\r
+ movl %ecx,%eax\r
+ movl %edx,%ecx\r
+ push %rax # save Index on stack\r
+ cpuid\r
+ mov 0x38(%rsp), %r10\r
+ test %r10, %r10\r
+ jz L1\r
+ mov %ecx,(%r10)\r
+L1: \r
+ mov %r8, %rcx\r
+ jrcxz L2\r
+ movl %eax,(%rcx)\r
+L2: \r
+ mov %r9, %rcx\r
+ jrcxz L3\r
+ mov %ebx, (%rcx)\r
+L3: \r
+ mov 0x40(%rsp), %rcx\r
+ jrcxz L4\r
+ mov %edx, (%rcx)\r
+L4: \r
+ pop %rax # restore Index to rax as return value\r
+ pop %rbx\r
+ ret\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; CpuIdEx.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmCpuidEx function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT32\r
+; EFIAPI\r
+; AsmCpuidEx (\r
+; IN UINT32 RegisterInEax,\r
+; IN UINT32 RegisterInEcx,\r
+; OUT UINT32 *RegisterOutEax OPTIONAL,\r
+; OUT UINT32 *RegisterOutEbx OPTIONAL,\r
+; OUT UINT32 *RegisterOutEcx OPTIONAL,\r
+; OUT UINT32 *RegisterOutEdx OPTIONAL\r
+; )\r
+;------------------------------------------------------------------------------\r
+AsmCpuidEx PROC USES rbx\r
+ mov eax, ecx\r
+ mov ecx, edx\r
+ push rax ; save Index on stack\r
+ cpuid\r
+ mov r10, [rsp + 38h]\r
+ test r10, r10\r
+ jz @F\r
+ mov [r10], ecx\r
+@@:\r
+ mov rcx, r8\r
+ jrcxz @F\r
+ mov [rcx], eax\r
+@@:\r
+ mov rcx, r9\r
+ jrcxz @F\r
+ mov [rcx], ebx\r
+@@:\r
+ mov rcx, [rsp + 40h]\r
+ jrcxz @F\r
+ mov [rcx], edx\r
+@@:\r
+ pop rax ; restore Index to rax as return value\r
+ ret\r
+AsmCpuidEx ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; CpuPause.Asm\r
+;\r
+; Abstract:\r
+;\r
+; CpuPause function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; CpuPause (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+CpuPause PROC\r
+ pause\r
+ ret\r
+CpuPause ENDP\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# DisableCache.S\r
+#\r
+# Abstract:\r
+#\r
+# Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r
+# WBINVD instruction.\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# AsmDisableCache (\r
+# VOID\r
+# );\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(AsmDisableCache)\r
+ASM_PFX(AsmDisableCache):\r
+ movq %cr0, %rax\r
+ btsq $30, %rax\r
+ btrq $29, %rax\r
+ movq %rax, %cr0\r
+ wbinvd\r
+ ret\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; DisableCache.Asm\r
+;\r
+; Abstract:\r
+;\r
+; Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r
+; WBINVD instruction.\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmDisableCache (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmDisableCache PROC\r
+ mov rax, cr0\r
+ bts rax, 30\r
+ btr rax, 29\r
+ mov cr0, rax\r
+ wbinvd\r
+ ret\r
+AsmDisableCache ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; DisableInterrupts.Asm\r
+;\r
+; Abstract:\r
+;\r
+; DisableInterrupts function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; DisableInterrupts (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+DisableInterrupts PROC\r
+ cli\r
+ ret\r
+DisableInterrupts ENDP\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# DisablePaging64.S\r
+#\r
+# Abstract:\r
+#\r
+# AsmDisablePaging64 function\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+ \r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# InternalX86DisablePaging64 (\r
+# IN UINT16 Cs,\r
+# IN UINT32 EntryPoint,\r
+# IN UINT32 Context1, OPTIONAL\r
+# IN UINT32 Context2, OPTIONAL\r
+# IN UINT32 NewStack\r
+# );\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(InternalX86DisablePaging64)\r
+ASM_PFX(InternalX86DisablePaging64):\r
+ cli \r
+ lea L1(%rip), %rsi # rsi <- The start address of transition code\r
+ mov 0x28(%rsp), %edi # rdi <- New stack\r
+ lea _mTransitionEnd(%rip), %rax # rax <- end of transition code\r
+ sub %rsi, %rax # rax <- The size of transition piece code\r
+ add $4, %rax # round rax up to the next 4 byte boundary\r
+ and $0xfc, %al\r
+ sub %rax, %rdi # rdi <- use stack to hold transition code \r
+ mov %edi, %r10d # r10 <- The start address of transicition code below 4G\r
+ push %rcx # save rcx to stack\r
+ mov %rax, %rcx # rcx <- The size of transition piece code\r
+ rep\r
+ movsb # copy transition code to (new stack - 64byte) below 4G\r
+ pop %rcx # restore rcx\r
+ \r
+ mov %r8d, %esi \r
+ mov %r9d, %edi \r
+ mov %r10d, %eax\r
+ sub $4, %eax\r
+ push %rcx # push Cs to stack\r
+ push %r10 # push address of transition code on stack \r
+ .byte 0x48, 0xcb # retq: Use far return to load CS register from stack\r
+ # (Use raw byte code since some GNU assemblers generates incorrect code for "retq") \r
+L1:\r
+ mov %eax,%esp # set up new stack\r
+ mov %cr0,%rax\r
+ btr $0x1f,%eax # clear CR0.PG\r
+ mov %rax,%cr0 # disable paging\r
+\r
+ mov %edx,%ebx # save EntryPoint to ebx, for rdmsr will overwrite edx\r
+ mov $0xc0000080,%ecx\r
+ rdmsr \r
+ and $0xfe,%ah # clear LME\r
+ wrmsr \r
+ mov %cr4,%rax\r
+ and $0xdf,%al # clear PAE\r
+ mov %rax,%cr4\r
+ push %rdi # push Context2\r
+ push %rsi # push Context1\r
+ callq *%rbx # transfer control to EntryPoint\r
+ jmp . # no one should get here\r
+\r
+_mTransitionEnd :\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; DisablePaging64.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmDisablePaging64 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; InternalX86DisablePaging64 (\r
+; IN UINT16 Cs,\r
+; IN UINT32 EntryPoint,\r
+; IN UINT32 Context1, OPTIONAL\r
+; IN UINT32 Context2, OPTIONAL\r
+; IN UINT32 NewStack\r
+; );\r
+;------------------------------------------------------------------------------\r
+InternalX86DisablePaging64 PROC\r
+ cli\r
+ lea rsi, @F ; rsi <- The start address of transition code\r
+ mov edi, [rsp + 28h] ; rdi <- New stack\r
+ lea rax, mTransitionEnd ; rax <- end of transition code\r
+ sub rax, rsi ; rax <- The size of transition piece code \r
+ add rax, 4 ; Round RAX up to the next 4 byte boundary\r
+ and al, 0fch\r
+ sub rdi, rax ; rdi <- Use stack to hold transition code\r
+ mov r10d, edi ; r10 <- The start address of transicition code below 4G\r
+ push rcx ; save rcx to stack\r
+ mov rcx, rax ; rcx <- The size of transition piece code\r
+ rep movsb ; copy transition code to top of new stack which must be below 4GB\r
+ pop rcx ; restore rcx\r
+ \r
+ mov esi, r8d\r
+ mov edi, r9d\r
+ mov eax, r10d ; eax <- start of the transition code on the stack\r
+ sub eax, 4 ; eax <- One slot below transition code on the stack\r
+ push rcx ; push Cs to stack\r
+ push r10 ; push address of tansition code on stack\r
+ DB 48h ; prefix to composite "retq" with next "retf"\r
+ retf ; Use far return to load CS register from stack\r
+\r
+; Start of transition code\r
+@@:\r
+ mov esp, eax ; set up new stack\r
+ mov rax, cr0\r
+ btr eax, 31 ; Clear CR0.PG\r
+ mov cr0, rax ; disable paging and caches\r
+ \r
+ mov ebx, edx ; save EntryPoint to rbx, for rdmsr will overwrite rdx\r
+ mov ecx, 0c0000080h\r
+ rdmsr\r
+ and ah, NOT 1 ; clear LME\r
+ wrmsr\r
+ mov rax, cr4\r
+ and al, NOT (1 SHL 5) ; clear PAE\r
+ mov cr4, rax\r
+ push rdi ; push Context2\r
+ push rsi ; push Context1\r
+ call rbx ; transfer control to EntryPoint\r
+ hlt ; no one should get here\r
+InternalX86DisablePaging64 ENDP\r
+\r
+mTransitionEnd LABEL BYTE\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# EnableCache.S\r
+#\r
+# Abstract:\r
+#\r
+# Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear \r
+# the NW bit of CR0 to 0\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# AsmEnableCache (\r
+# VOID\r
+# );\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(AsmEnableCache)\r
+ASM_PFX(AsmEnableCache):\r
+ wbinvd\r
+ movq %cr0, %rax\r
+ btrq $30, %rax\r
+ btrq $29, %rax\r
+ movq %rax, %cr0\r
+ ret\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; EnableCache.Asm\r
+;\r
+; Abstract:\r
+;\r
+; Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear \r
+; the NW bit of CR0 to 0\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmEnableCache (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmEnableCache PROC\r
+ wbinvd\r
+ mov rax, cr0\r
+ btr rax, 29\r
+ btr rax, 30\r
+ mov cr0, rax\r
+ ret\r
+AsmEnableCache ENDP\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# EnableDisableInterrupts.S\r
+#\r
+# Abstract:\r
+#\r
+# EnableDisableInterrupts function\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# EnableDisableInterrupts (\r
+# VOID\r
+# );\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(EnableDisableInterrupts)\r
+ASM_PFX(EnableDisableInterrupts):\r
+ sti\r
+ cli\r
+ ret\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; EnableDisableInterrupts.Asm\r
+;\r
+; Abstract:\r
+;\r
+; EnableDisableInterrupts function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; EnableDisableInterrupts (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+EnableDisableInterrupts PROC\r
+ sti\r
+ cli\r
+ ret\r
+EnableDisableInterrupts ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; EnableInterrupts.Asm\r
+;\r
+; Abstract:\r
+;\r
+; EnableInterrupts function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; EnableInterrupts (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+EnableInterrupts PROC\r
+ sti\r
+ ret\r
+EnableInterrupts ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; FlushCacheLine.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmFlushCacheLine function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID *\r
+; EFIAPI \r
+; AsmFlushCacheLine (\r
+; IN VOID *LinearAddress\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmFlushCacheLine PROC\r
+ clflush [rcx]\r
+ mov rax, rcx\r
+ ret\r
+AsmFlushCacheLine ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; FxRestore.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmFxRestore function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; InternalX86FxRestore (\r
+; IN CONST IA32_FX_BUFFER *Buffer\r
+; );\r
+;------------------------------------------------------------------------------\r
+InternalX86FxRestore PROC\r
+ fxrstor [rcx]\r
+ ret\r
+InternalX86FxRestore ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; FxSave.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmFxSave function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; InternalX86FxSave (\r
+; OUT IA32_FX_BUFFER *Buffer\r
+; );\r
+;------------------------------------------------------------------------------\r
+InternalX86FxSave PROC\r
+ fxsave [rcx]\r
+ ret\r
+InternalX86FxSave ENDP\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+ GCC inline implementation of BaseLib processor specific functions.\r
+ \r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+\r
+\r
+\r
+/**\r
+ Used to serialize load and store operations.\r
+\r
+ All loads and stores that proceed calls to this function are guaranteed to be\r
+ globally visible when this function returns.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+MemoryFence (\r
+ VOID\r
+ )\r
+{\r
+ // This is a little bit of overkill and it is more about the compiler that it is\r
+ // actually processor synchronization. This is like the _ReadWriteBarrier \r
+ // Microsoft specific intrinsic\r
+ __asm__ __volatile__ ("":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ Enables CPU interrupts.\r
+\r
+ Enables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableInterrupts (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("sti"::: "memory");\r
+}\r
+\r
+\r
+/**\r
+ Disables CPU interrupts.\r
+\r
+ Disables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableInterrupts (\r
+ VOID\r
+ )\r
+{ \r
+ __asm__ __volatile__ ("cli"::: "memory");\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ Requests CPU to pause for a short period of time.\r
+\r
+ Requests CPU to pause for a short period of time. Typically used in MP\r
+ systems to prevent memory starvation while waiting for a spin lock.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuPause (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("pause");\r
+}\r
+\r
+\r
+/**\r
+ Generates a breakpoint on the CPU.\r
+\r
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+ that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("int $3");\r
+}\r
+\r
+\r
+\r
+/**\r
+ Returns a 64-bit Machine Specific Register(MSR).\r
+\r
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is\r
+ performed on Index, and some Index values may cause CPU exceptions. The\r
+ caller must either guarantee that Index is valid, or the caller must set up\r
+ exception handlers to catch the exceptions. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @param Index The 32-bit MSR index to read.\r
+\r
+ @return The value of the MSR identified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMsr64 (\r
+ IN UINT32 Index\r
+ )\r
+{\r
+ UINT32 LowData;\r
+ UINT32 HighData;\r
+ \r
+ __asm__ __volatile__ (\r
+ "rdmsr"\r
+ : "=a" (LowData), // %0\r
+ "=d" (HighData) // %1\r
+ : "c" (Index) // %2\r
+ );\r
+ \r
+ return (((UINT64)HighData) << 32) | LowData;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r
+ value.\r
+\r
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The\r
+ 64-bit value written to the MSR is returned. No parameter checking is\r
+ performed on Index or Value, and some of these may cause CPU exceptions. The\r
+ caller must either guarantee that Index and Value are valid, or the caller\r
+ must establish proper exception handlers. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param Value The 64-bit value to write to the MSR.\r
+\r
+ @return Value\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteMsr64 (\r
+ IN UINT32 Index,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ UINT32 LowData;\r
+ UINT32 HighData;\r
+\r
+ LowData = (UINT32)(Value);\r
+ HighData = (UINT32)(Value >> 32);\r
+ \r
+ __asm__ __volatile__ (\r
+ "wrmsr"\r
+ :\r
+ : "c" (Index),\r
+ "a" (LowData),\r
+ "d" (HighData)\r
+ );\r
+ \r
+ return Value;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Reads the current value of the EFLAGS register.\r
+\r
+ Reads and returns the current value of the EFLAGS register. This function is\r
+ only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a\r
+ 64-bit value on X64.\r
+\r
+ @return EFLAGS on IA-32 or RFLAGS on X64.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadEflags (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Eflags;\r
+ \r
+ __asm__ __volatile__ (\r
+ "pushfq \n\t"\r
+ "pop %0 "\r
+ : "=r" (Eflags) // %0\r
+ );\r
+ \r
+ return Eflags;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Reads the current value of the Control Register 0 (CR0).\r
+\r
+ Reads and returns the current value of CR0. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 0 (CR0).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr0 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cr0,%0" \r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of the Control Register 2 (CR2).\r
+\r
+ Reads and returns the current value of CR2. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 2 (CR2).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr2 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cr2, %0" \r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+/**\r
+ Reads the current value of the Control Register 3 (CR3).\r
+\r
+ Reads and returns the current value of CR3. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 3 (CR3).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr3 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cr3, %0" \r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of the Control Register 4 (CR4).\r
+\r
+ Reads and returns the current value of CR4. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of the Control Register 4 (CR4).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadCr4 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cr4, %0" \r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 0 (CR0).\r
+\r
+ Writes and returns a new value to CR0. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr0 The value to write to CR0.\r
+\r
+ @return The value written to CR0.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr0 (\r
+ UINTN Cr0\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%cr0"\r
+ :\r
+ : "r" (Cr0)\r
+ );\r
+ return Cr0;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 2 (CR2).\r
+\r
+ Writes and returns a new value to CR2. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr2 The value to write to CR2.\r
+\r
+ @return The value written to CR2.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr2 (\r
+ UINTN Cr2\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%cr2"\r
+ :\r
+ : "r" (Cr2)\r
+ );\r
+ return Cr2;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 3 (CR3).\r
+\r
+ Writes and returns a new value to CR3. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr3 The value to write to CR3.\r
+\r
+ @return The value written to CR3.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr3 (\r
+ UINTN Cr3\r
+ )\r
+{\r
+ return Cr3;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Control Register 4 (CR4).\r
+\r
+ Writes and returns a new value to CR4. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Cr4 The value to write to CR4.\r
+\r
+ @return The value written to CR4.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteCr4 (\r
+ UINTN Cr4\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%cr4"\r
+ :\r
+ : "r" (Cr4)\r
+ );\r
+ return Cr4;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 0 (DR0).\r
+\r
+ Reads and returns the current value of DR0. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 0 (DR0).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr0 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr0, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 1 (DR1).\r
+\r
+ Reads and returns the current value of DR1. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 1 (DR1).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr1 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr1, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 2 (DR2).\r
+\r
+ Reads and returns the current value of DR2. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 2 (DR2).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr2 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr2, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 3 (DR3).\r
+\r
+ Reads and returns the current value of DR3. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 3 (DR3).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr3 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr3, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 4 (DR4).\r
+\r
+ Reads and returns the current value of DR4. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 4 (DR4).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr4 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr4, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 5 (DR5).\r
+\r
+ Reads and returns the current value of DR5. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 5 (DR5).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr5 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr5, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 6 (DR6).\r
+\r
+ Reads and returns the current value of DR6. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 6 (DR6).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr6 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr6, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Debug Register 7 (DR7).\r
+\r
+ Reads and returns the current value of DR7. This function is only available\r
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on\r
+ X64.\r
+\r
+ @return The value of Debug Register 7 (DR7).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmReadDr7 (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%dr7, %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 0 (DR0).\r
+\r
+ Writes and returns a new value to DR0. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr0 The value to write to Dr0.\r
+\r
+ @return The value written to Debug Register 0 (DR0).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr0 (\r
+ UINTN Dr0\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr0"\r
+ :\r
+ : "r" (Dr0)\r
+ );\r
+ return Dr0;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 1 (DR1).\r
+\r
+ Writes and returns a new value to DR1. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr1 The value to write to Dr1.\r
+\r
+ @return The value written to Debug Register 1 (DR1).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr1 (\r
+ UINTN Dr1\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr1"\r
+ :\r
+ : "r" (Dr1)\r
+ );\r
+ return Dr1;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 2 (DR2).\r
+\r
+ Writes and returns a new value to DR2. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr2 The value to write to Dr2.\r
+\r
+ @return The value written to Debug Register 2 (DR2).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr2 (\r
+ UINTN Dr2\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr2"\r
+ :\r
+ : "r" (Dr2)\r
+ );\r
+ return Dr2;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 3 (DR3).\r
+\r
+ Writes and returns a new value to DR3. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr3 The value to write to Dr3.\r
+\r
+ @return The value written to Debug Register 3 (DR3).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr3 (\r
+ UINTN Dr3\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr3"\r
+ :\r
+ : "r" (Dr3)\r
+ );\r
+ return Dr3;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 4 (DR4).\r
+\r
+ Writes and returns a new value to DR4. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr4 The value to write to Dr4.\r
+\r
+ @return The value written to Debug Register 4 (DR4).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr4 (\r
+ UINTN Dr4\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr4"\r
+ :\r
+ : "r" (Dr4)\r
+ );\r
+ return Dr4;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 5 (DR5).\r
+\r
+ Writes and returns a new value to DR5. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr5 The value to write to Dr5.\r
+\r
+ @return The value written to Debug Register 5 (DR5).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr5 (\r
+ UINTN Dr5\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr5"\r
+ :\r
+ : "r" (Dr5)\r
+ );\r
+ return Dr5;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 6 (DR6).\r
+\r
+ Writes and returns a new value to DR6. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr6 The value to write to Dr6.\r
+\r
+ @return The value written to Debug Register 6 (DR6).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr6 (\r
+ UINTN Dr6\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr6"\r
+ :\r
+ : "r" (Dr6)\r
+ );\r
+ return Dr6;\r
+}\r
+\r
+\r
+/**\r
+ Writes a value to Debug Register 7 (DR7).\r
+\r
+ Writes and returns a new value to DR7. This function is only available on\r
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.\r
+\r
+ @param Dr7 The value to write to Dr7.\r
+\r
+ @return The value written to Debug Register 7 (DR7).\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmWriteDr7 (\r
+ UINTN Dr7\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mov %0, %%dr7"\r
+ :\r
+ : "r" (Dr7)\r
+ );\r
+ return Dr7;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Code Segment Register (CS).\r
+\r
+ Reads and returns the current value of CS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of CS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadCs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%cs, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Data Segment Register (DS).\r
+\r
+ Reads and returns the current value of DS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of DS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadDs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%ds, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Extra Segment Register (ES).\r
+\r
+ Reads and returns the current value of ES. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of ES.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadEs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%es, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of FS Data Segment Register (FS).\r
+\r
+ Reads and returns the current value of FS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of FS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadFs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%fs, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of GS Data Segment Register (GS).\r
+\r
+ Reads and returns the current value of GS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of GS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadGs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%gs, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Stack Segment Register (SS).\r
+\r
+ Reads and returns the current value of SS. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of SS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadSs (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "mov %%ds, %0"\r
+ :"=a" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Task Register (TR).\r
+\r
+ Reads and returns the current value of TR. This function is only available on\r
+ IA-32 and X64.\r
+\r
+ @return The current value of TR.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadTr (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "str %0"\r
+ : "=r" (Data)\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r
+ function is only available on IA-32 and X64.\r
+\r
+ @param Gdtr The pointer to a GDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86ReadGdtr (\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "sgdt %0"\r
+ : "=m" (*Gdtr)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
+\r
+ Writes and the current GDTR descriptor specified by Gdtr. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Gdtr The pointer to a GDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86WriteGdtr (\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "lgdt %0"\r
+ :\r
+ : "m" (*Gdtr)\r
+ );\r
+ \r
+}\r
+\r
+\r
+/**\r
+ Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This\r
+ function is only available on IA-32 and X64.\r
+\r
+ @param Idtr The pointer to a IDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86ReadIdtr (\r
+ OUT IA32_DESCRIPTOR *Idtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "sidt %0"\r
+ : "=m" (*Idtr)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Writes the current IDTR descriptor and returns it in Idtr. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Idtr The pointer to a IDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86WriteIdtr (\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "lidt %0"\r
+ :\r
+ : "m" (*Idtr)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Reads the current Local Descriptor Table Register(LDTR) selector.\r
+\r
+ Reads and returns the current 16-bit LDTR descriptor value. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @return The current selector of LDT.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+AsmReadLdtr (\r
+ VOID\r
+ )\r
+{\r
+ UINT16 Data;\r
+ \r
+ __asm__ __volatile__ (\r
+ "sldt %0"\r
+ : "=g" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes the current Local Descriptor Table Register (GDTR) selector.\r
+\r
+ Writes and the current LDTR descriptor specified by Ldtr. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Ldtr 16-bit LDTR selector value.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteLdtr (\r
+ IN UINT16 Ldtr\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "lldtw %0"\r
+ :\r
+ : "g" (Ldtr) // %0\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Save the current floating point/SSE/SSE2 context to a buffer.\r
+\r
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by\r
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only\r
+ available on IA-32 and X64.\r
+\r
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86FxSave (\r
+ OUT IA32_FX_BUFFER *Buffer\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "fxsave %0"\r
+ :\r
+ : "m" (*Buffer) // %0\r
+ ); \r
+}\r
+\r
+\r
+/**\r
+ Restores the current floating point/SSE/SSE2 context from a buffer.\r
+\r
+ Restores the current floating point/SSE/SSE2 state from the buffer specified\r
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is\r
+ only available on IA-32 and X64.\r
+\r
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86FxRestore (\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "fxrstor %0"\r
+ :\r
+ : "m" (*Buffer) // %0\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #0 (MM0).\r
+\r
+ Reads and returns the current value of MM0. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM0.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm0 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm0, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #1 (MM1).\r
+\r
+ Reads and returns the current value of MM1. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM1.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm1 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm1, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #2 (MM2).\r
+\r
+ Reads and returns the current value of MM2. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM2.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm2 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm2, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #3 (MM3).\r
+\r
+ Reads and returns the current value of MM3. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM3.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm3 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm3, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #4 (MM4).\r
+\r
+ Reads and returns the current value of MM4. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM4.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm4 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm4, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #5 (MM5).\r
+\r
+ Reads and returns the current value of MM5. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM5.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm5 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm5, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #6 (MM6).\r
+\r
+ Reads and returns the current value of MM6. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM6.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm6 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm6, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of 64-bit MMX Register #7 (MM7).\r
+\r
+ Reads and returns the current value of MM7. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of MM7.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMm7 (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ __asm__ __volatile__ (\r
+ "movd %%mm7, %0 \n\t"\r
+ : "=r" (Data) // %0\r
+ );\r
+ \r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #0 (MM0).\r
+\r
+ Writes the current value of MM0. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM0.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm0 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm0" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #1 (MM1).\r
+\r
+ Writes the current value of MM1. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM1.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm1 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm1" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #2 (MM2).\r
+\r
+ Writes the current value of MM2. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM2.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm2 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm2" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #3 (MM3).\r
+\r
+ Writes the current value of MM3. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM3.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm3 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm3" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #4 (MM4).\r
+\r
+ Writes the current value of MM4. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM4.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm4 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm4" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #5 (MM5).\r
+\r
+ Writes the current value of MM5. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM5.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm5 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm5" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #6 (MM6).\r
+\r
+ Writes the current value of MM6. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM6.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm6 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm6" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Writes the current value of 64-bit MMX Register #7 (MM7).\r
+\r
+ Writes the current value of MM7. This function is only available on IA32 and\r
+ X64.\r
+\r
+ @param Value The 64-bit value to write to MM7.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteMm7 (\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "movd %0, %%mm7" // %0\r
+ : \r
+ : "m" (Value)\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of Time Stamp Counter (TSC).\r
+\r
+ Reads and returns the current value of TSC. This function is only available\r
+ on IA-32 and X64.\r
+\r
+ @return The current value of TSC\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadTsc (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 LowData;\r
+ UINT32 HiData;\r
+ \r
+ __asm__ __volatile__ (\r
+ "rdtsc"\r
+ : "=a" (LowData),\r
+ "=d" (HiData)\r
+ );\r
+ \r
+ return (((UINT64)HiData) << 32) | LowData; \r
+}\r
+\r
+\r
+/**\r
+ Reads the current value of a Performance Counter (PMC).\r
+\r
+ Reads and returns the current value of performance counter specified by\r
+ Index. This function is only available on IA-32 and X64.\r
+\r
+ @param Index The 32-bit Performance Counter index to read.\r
+\r
+ @return The value of the PMC specified by Index.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadPmc (\r
+ IN UINT32 Index\r
+ )\r
+{\r
+ UINT32 LowData;\r
+ UINT32 HiData;\r
+ \r
+ __asm__ __volatile__ (\r
+ "rdpmc"\r
+ : "=a" (LowData),\r
+ "=d" (HiData)\r
+ : "c" (Index)\r
+ );\r
+ \r
+ return (((UINT64)HiData) << 32) | LowData; \r
+}\r
+\r
+\r
+/**\r
+ Sets up a monitor buffer that is used by AsmMwait().\r
+\r
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx\r
+ and Edx. Returns Eax. This function is only available on IA-32 and X64.\r
+\r
+ @param Eax The value to load into EAX or RAX before executing the MONITOR\r
+ instruction.\r
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR\r
+ instruction.\r
+ @param Edx The value to load into EDX or RDX before executing the MONITOR\r
+ instruction.\r
+\r
+ @return Eax\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmMonitor (\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx,\r
+ IN UINTN Edx\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "monitor"\r
+ :\r
+ : "a" (Eax),\r
+ "c" (Ecx),\r
+ "d" (Edx)\r
+ );\r
+ \r
+ return Eax;\r
+}\r
+\r
+\r
+/**\r
+ Executes an MWAIT instruction.\r
+\r
+ Executes an MWAIT instruction with the register state specified by Eax and\r
+ Ecx. Returns Eax. This function is only available on IA-32 and X64.\r
+\r
+ @param Eax The value to load into EAX or RAX before executing the MONITOR\r
+ instruction.\r
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR\r
+ instruction.\r
+\r
+ @return Eax\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+AsmMwait (\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "mwait"\r
+ : \r
+ : "a" (Eax),\r
+ "c" (Ecx)\r
+ );\r
+ \r
+ return Eax; \r
+}\r
+\r
+\r
+/**\r
+ Executes a WBINVD instruction.\r
+\r
+ Executes a WBINVD instruction. This function is only available on IA-32 and\r
+ X64.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWbinvd (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("wbinvd":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ Executes a INVD instruction.\r
+\r
+ Executes a INVD instruction. This function is only available on IA-32 and\r
+ X64.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmInvd (\r
+ VOID\r
+ )\r
+{\r
+ __asm__ __volatile__ ("invd":::"memory");\r
+ \r
+}\r
+\r
+\r
+/**\r
+ Flushes a cache line from all the instruction and data caches within the\r
+ coherency domain of the CPU.\r
+\r
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
+ This function is only available on IA-32 and X64.\r
+\r
+ @param LinearAddress The address of the cache line to flush. If the CPU is\r
+ in a physical addressing mode, then LinearAddress is a\r
+ physical address. If the CPU is in a virtual\r
+ addressing mode, then LinearAddress is a virtual\r
+ address.\r
+\r
+ @return LinearAddress\r
+**/\r
+VOID *\r
+EFIAPI\r
+AsmFlushCacheLine (\r
+ IN VOID *LinearAddress\r
+ )\r
+{\r
+ __asm__ __volatile__ (\r
+ "clflush (%0)"\r
+ :\r
+ : "r" (LinearAddress) \r
+ : "memory"\r
+ );\r
+ \r
+ return LinearAddress;\r
+}\r
+\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; Invd.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmInvd function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmInvd (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmInvd PROC\r
+ invd\r
+ ret\r
+AsmInvd ENDP\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# LongJump.S\r
+#\r
+# Abstract:\r
+#\r
+# Implementation of _LongJump() on x64.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# InternalLongJump (\r
+# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // %rcx\r
+# IN UINTN Value // %rdx\r
+# );\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(EfiInternalLongJump)\r
+ASM_PFX(EfiInternalLongJump):\r
+ mov (%rcx), %rbx\r
+ mov 0x8(%rcx), %rsp\r
+ mov 0x10(%rcx), %rbp\r
+ mov 0x18(%rcx), %rdi\r
+ mov 0x20(%rcx), %rsi\r
+ mov 0x28(%rcx), %r12\r
+ mov 0x30(%rcx), %r13\r
+ mov 0x38(%rcx), %r14\r
+ mov 0x40(%rcx), %r15\r
+ # load non-volatile fp registers\r
+ ldmxcsr 0x50(%rcx)\r
+ movdqu 0x58(%rcx), %xmm6\r
+ movdqu 0x68(%rcx), %xmm7\r
+ movdqu 0x78(%rcx), %xmm8\r
+ movdqu 0x88(%rcx), %xmm9\r
+ movdqu 0x98(%rcx), %xmm10\r
+ movdqu 0xA8(%rcx), %xmm11\r
+ movdqu 0xB8(%rcx), %xmm12\r
+ movdqu 0xC8(%rcx), %xmm13\r
+ movdqu 0xD8(%rcx), %xmm14\r
+ movdqu 0xE8(%rcx), %xmm15 \r
+ mov %rdx, %rax # set return value\r
+ jmp *0x48(%rcx)\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# UnixInternalLongJump (\r
+# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // %rdi\r
+# IN UINTN Value // %rsi\r
+# );\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(InternalLongJump)\r
+ASM_PFX(InternalLongJump):\r
+ mov (%rdi), %rbx\r
+ mov 0x8(%rdi), %rsp\r
+ mov 0x10(%rdi), %rbp\r
+ mov 0x18(%rdi), %rdi\r
+ mov 0x20(%rdi), %rsi\r
+ mov 0x28(%rdi), %r12\r
+ mov 0x30(%rdi), %r13\r
+ mov 0x38(%rdi), %r14\r
+ mov 0x40(%rdi), %r15\r
+ # load non-volatile fp registers\r
+ ldmxcsr 0x50(%rdi)\r
+ movdqu 0x58(%rdi), %xmm6\r
+ movdqu 0x68(%rdi), %xmm7\r
+ movdqu 0x78(%rdi), %xmm8\r
+ movdqu 0x88(%rdi), %xmm9\r
+ movdqu 0x98(%rdi), %xmm10\r
+ movdqu 0xA8(%rdi), %xmm11\r
+ movdqu 0xB8(%rdi), %xmm12\r
+ movdqu 0xC8(%rdi), %xmm13\r
+ movdqu 0xD8(%rdi), %xmm14\r
+ movdqu 0xE8(%rdi), %xmm15 \r
+ mov %rsi, %rax # set return value\r
+ jmp *0x48(%rdi)\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; LongJump.Asm\r
+;\r
+; Abstract:\r
+;\r
+; Implementation of _LongJump() on x64.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; InternalLongJump (\r
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
+; IN UINTN Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+InternalLongJump PROC\r
+ mov rbx, [rcx]\r
+ mov rsp, [rcx + 8]\r
+ mov rbp, [rcx + 10h]\r
+ mov rdi, [rcx + 18h]\r
+ mov rsi, [rcx + 20h]\r
+ mov r12, [rcx + 28h]\r
+ mov r13, [rcx + 30h]\r
+ mov r14, [rcx + 38h]\r
+ mov r15, [rcx + 40h]\r
+ ; load non-volatile fp registers\r
+ ldmxcsr [rcx + 50h]\r
+ movdqu xmm6, [rcx + 58h]\r
+ movdqu xmm7, [rcx + 68h]\r
+ movdqu xmm8, [rcx + 78h]\r
+ movdqu xmm9, [rcx + 88h]\r
+ movdqu xmm10, [rcx + 98h]\r
+ movdqu xmm11, [rcx + 0A8h]\r
+ movdqu xmm12, [rcx + 0B8h]\r
+ movdqu xmm13, [rcx + 0C8h]\r
+ movdqu xmm14, [rcx + 0D8h]\r
+ movdqu xmm15, [rcx + 0E8h]\r
+ mov rax, rdx ; set return value\r
+ jmp qword ptr [rcx + 48h]\r
+InternalLongJump ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; Monitor.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmMonitor function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmMonitor (\r
+; IN UINTN Eax,\r
+; IN UINTN Ecx,\r
+; IN UINTN Edx\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmMonitor PROC\r
+ mov eax, ecx\r
+ mov ecx, edx\r
+ mov edx, r8d\r
+ DB 0fh, 1, 0c8h ; monitor\r
+ ret\r
+AsmMonitor ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; Mwait.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmMwait function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmMwait (\r
+; IN UINTN Eax,\r
+; IN UINTN Ecx\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmMwait PROC\r
+ mov eax, ecx\r
+ mov ecx, edx\r
+ DB 0fh, 1, 0c9h ; mwait\r
+ ret\r
+AsmMwait ENDP\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+ Non-existing BaseLib functions on x64\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+/**\r
+ Enables the 32-bit paging mode on the CPU.\r
+\r
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r
+ must be properly initialized prior to calling this service. This function\r
+ assumes the current execution mode is 32-bit protected mode. This function is\r
+ only available on IA-32. After the 32-bit paging mode is enabled, control is\r
+ transferred to the function specified by EntryPoint using the new stack\r
+ specified by NewStack and passing in the parameters specified by Context1 and\r
+ Context2. Context1 and Context2 are optional and may be NULL. The function\r
+ EntryPoint must never return.\r
+\r
+ There are a number of constraints that must be followed before calling this\r
+ function:\r
+ 1) Interrupts must be disabled.\r
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This\r
+ means all descriptors must have a base of 0 and a limit of 4GB.\r
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat\r
+ descriptors.\r
+ 4) CR3 must point to valid page tables that will be used once the transition\r
+ is complete, and those page tables must guarantee that the pages for this\r
+ function and the stack are identity mapped.\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack after\r
+ paging is enabled.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function as the first parameter after paging is enabled.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function as the second parameter after paging is enabled.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function after paging is enabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86EnablePaging32 (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack\r
+ )\r
+{\r
+ //\r
+ // This function cannot work on x64 platform\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ Disables the 32-bit paging mode on the CPU.\r
+\r
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected\r
+ mode. This function assumes the current execution mode is 32-paged protected\r
+ mode. This function is only available on IA-32. After the 32-bit paging mode\r
+ is disabled, control is transferred to the function specified by EntryPoint\r
+ using the new stack specified by NewStack and passing in the parameters\r
+ specified by Context1 and Context2. Context1 and Context2 are optional and\r
+ may be NULL. The function EntryPoint must never return.\r
+\r
+ There are a number of constraints that must be followed before calling this\r
+ function:\r
+ 1) Interrupts must be disabled.\r
+ 2) The caller must be in 32-bit paged mode.\r
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.\r
+ 4) CR3 must point to valid page tables that guarantee that the pages for\r
+ this function and the stack are identity mapped.\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack after\r
+ paging is disabled.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function as the first parameter after paging is disabled.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function as the second parameter after paging is\r
+ disabled.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function after paging is disabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86DisablePaging32 (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack\r
+ )\r
+{\r
+ //\r
+ // This function cannot work on x64 platform\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
+\r
+\r
+/**\r
+ Enables the 64-bit paging mode on the CPU.\r
+\r
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r
+ must be properly initialized prior to calling this service. This function\r
+ assumes the current execution mode is 32-bit protected mode with flat\r
+ descriptors. This function is only available on IA-32. After the 64-bit\r
+ paging mode is enabled, control is transferred to the function specified by\r
+ EntryPoint using the new stack specified by NewStack and passing in the\r
+ parameters specified by Context1 and Context2. Context1 and Context2 are\r
+ optional and may be 0. The function EntryPoint must never return.\r
+\r
+ @param Cs The 16-bit selector to load in the CS before EntryPoint\r
+ is called. The descriptor in the GDT that this selector\r
+ references must be setup for long mode.\r
+ @param EntryPoint The 64-bit virtual address of the function to call with\r
+ the new stack after paging is enabled.\r
+ @param Context1 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the first parameter after\r
+ paging is enabled.\r
+ @param Context2 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the second parameter after\r
+ paging is enabled.\r
+ @param NewStack The 64-bit virtual address of the new stack to use for\r
+ the EntryPoint function after paging is enabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalX86EnablePaging64 (\r
+ IN UINT16 Cs,\r
+ IN UINT64 EntryPoint,\r
+ IN UINT64 Context1, OPTIONAL\r
+ IN UINT64 Context2, OPTIONAL\r
+ IN UINT64 NewStack\r
+ )\r
+{\r
+ //\r
+ // This function cannot work on x64 platform.\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadCr0.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadCr0 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadCr0 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadCr0 PROC\r
+ mov rax, cr0\r
+ ret\r
+AsmReadCr0 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadCr2.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadCr2 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadCr2 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadCr2 PROC\r
+ mov rax, cr2\r
+ ret\r
+AsmReadCr2 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadCr3.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadCr3 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadCr3 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadCr3 PROC\r
+ mov rax, cr3\r
+ ret\r
+AsmReadCr3 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadCr4.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadCr4 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadCr4 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadCr4 PROC\r
+ mov rax, cr4\r
+ ret\r
+AsmReadCr4 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadCs.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadCs function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT16\r
+; EFIAPI\r
+; AsmReadCs (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadCs PROC\r
+ mov eax, cs\r
+ ret\r
+AsmReadCs ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadDr0.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadDr0 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadDr0 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadDr0 PROC\r
+ mov rax, dr0\r
+ ret\r
+AsmReadDr0 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadDr1.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadDr1 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadDr1 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadDr1 PROC\r
+ mov rax, dr1\r
+ ret\r
+AsmReadDr1 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadDr2.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadDr2 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadDr2 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadDr2 PROC\r
+ mov rax, dr2\r
+ ret\r
+AsmReadDr2 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadDr3.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadDr3 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadDr3 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadDr3 PROC\r
+ mov rax, dr3\r
+ ret\r
+AsmReadDr3 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadDr4.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadDr4 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadDr4 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadDr4 PROC\r
+ ;\r
+ ; There's no obvious reason to access this register, since it's aliased to\r
+ ; DR7 when DE=0 or an exception generated when DE=1\r
+ ;\r
+ DB 0fh, 21h, 0e0h\r
+ ret\r
+AsmReadDr4 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadDr5.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadDr5 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadDr5 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadDr5 PROC\r
+ ;\r
+ ; There's no obvious reason to access this register, since it's aliased to\r
+ ; DR7 when DE=0 or an exception generated when DE=1\r
+ ;\r
+ DB 0fh, 21h, 0e8h\r
+ ret\r
+AsmReadDr5 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadDr6.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadDr6 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadDr6 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadDr6 PROC\r
+ mov rax, dr6\r
+ ret\r
+AsmReadDr6 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadDr7.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadDr7 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadDr7 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadDr7 PROC\r
+ mov rax, dr7\r
+ ret\r
+AsmReadDr7 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadDs.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadDs function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT16\r
+; EFIAPI\r
+; AsmReadDs (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadDs PROC\r
+ mov eax, ds\r
+ ret\r
+AsmReadDs ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadEflags.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadEflags function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmReadEflags (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadEflags PROC\r
+ pushfq\r
+ pop rax\r
+ ret\r
+AsmReadEflags ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadEs.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadEs function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT16\r
+; EFIAPI\r
+; AsmReadEs (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadEs PROC\r
+ mov eax, es\r
+ ret\r
+AsmReadEs ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadFs.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadFs function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT16\r
+; EFIAPI\r
+; AsmReadFs (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadFs PROC\r
+ mov eax, fs\r
+ ret\r
+AsmReadFs ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadGdtr.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadGdtr function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; InternalX86ReadGdtr (\r
+; OUT IA32_DESCRIPTOR *Gdtr\r
+; );\r
+;------------------------------------------------------------------------------\r
+InternalX86ReadGdtr PROC\r
+ sgdt fword ptr [rcx]\r
+ ret\r
+InternalX86ReadGdtr ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadGs.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadGs function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT16\r
+; EFIAPI\r
+; AsmReadGs (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadGs PROC\r
+ mov eax, gs\r
+ ret\r
+AsmReadGs ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadIdtr.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadIdtr function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; InternalX86ReadIdtr (\r
+; OUT IA32_DESCRIPTOR *Idtr\r
+; );\r
+;------------------------------------------------------------------------------\r
+InternalX86ReadIdtr PROC\r
+ sidt fword ptr [rcx]\r
+ ret\r
+InternalX86ReadIdtr ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadLdtr.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadLdtr function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT16\r
+; EFIAPI\r
+; AsmReadLdtr (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadLdtr PROC\r
+ sldt eax\r
+ ret\r
+AsmReadLdtr ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadMm0.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadMm0 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadMm0 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadMm0 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 7eh, 0c0h\r
+ ret\r
+AsmReadMm0 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadMm1.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadMm1 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadMm1 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadMm1 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 7eh, 0c8h\r
+ ret\r
+AsmReadMm1 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadMm2.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadMm2 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadMm2 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadMm2 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 7eh, 0d0h\r
+ ret\r
+AsmReadMm2 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadMm3.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadMm3 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadMm3 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadMm3 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 7eh, 0d8h\r
+ ret\r
+AsmReadMm3 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadMm4.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadMm4 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadMm4 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadMm4 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 7eh, 0e0h\r
+ ret\r
+AsmReadMm4 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadMm5.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadMm5 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadMm5 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadMm5 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 7eh, 0e8h\r
+ ret\r
+AsmReadMm5 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadMm6.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadMm6 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadMm6 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadMm6 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 7eh, 0f0h\r
+ ret\r
+AsmReadMm6 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadMm7.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadMm7 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadMm7 (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadMm7 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 7eh, 0f8h\r
+ ret\r
+AsmReadMm7 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadMsr64.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadMsr64 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadMsr64 (\r
+; IN UINT32 Index\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadMsr64 PROC\r
+ rdmsr ; edx & eax are zero extended\r
+ shl rdx, 20h\r
+ or rax, rdx\r
+ ret\r
+AsmReadMsr64 ENDP\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+ CpuBreakpoint function.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+/**\r
+ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
+**/\r
+\r
+unsigned __int64 __readmsr (int register);\r
+\r
+#pragma intrinsic(__readmsr)\r
+\r
+/**\r
+ Read data to MSR.\r
+\r
+ @param Index Register index of MSR.\r
+\r
+ @return Value read from MSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmReadMsr64 (\r
+ IN UINT32 Index\r
+ )\r
+{\r
+ return __readmsr (Index);\r
+}\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadPmc.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadPmc function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadPmc (\r
+; IN UINT32 PmcIndex\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadPmc PROC\r
+ rdpmc\r
+ shl rdx, 20h\r
+ or rax, rdx\r
+ ret\r
+AsmReadPmc ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadSs.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadSs function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT16\r
+; EFIAPI\r
+; AsmReadSs (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadSs PROC\r
+ mov eax, ss\r
+ ret\r
+AsmReadSs ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadTr.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadTr function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT16\r
+; EFIAPI\r
+; AsmReadTr (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadTr PROC\r
+ str eax\r
+ ret\r
+AsmReadTr ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ReadTsc.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmReadTsc function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmReadTsc (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmReadTsc PROC\r
+ rdtsc\r
+ shl rdx, 20h\r
+ or rax, rdx\r
+ ret\r
+AsmReadTsc ENDP\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# SetJump.S\r
+#\r
+# Abstract:\r
+#\r
+# Implementation of SetJump() on x86_64\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(EfiSetJump)\r
+ASM_PFX(EfiSetJump):\r
+ push %rcx\r
+ add $0xffffffffffffffe0,%rsp\r
+ call ASM_PFX(InternalAssertJumpBuffer)\r
+ add $0x20,%rsp\r
+ pop %rcx\r
+ pop %rdx\r
+ mov %rbx,(%rcx)\r
+ mov %rsp,0x8(%rcx)\r
+ mov %rbp,0x10(%rcx)\r
+ mov %rdi,0x18(%rcx)\r
+ mov %rsi,0x20(%rcx)\r
+ mov %r12,0x28(%rcx)\r
+ mov %r13,0x30(%rcx)\r
+ mov %r14,0x38(%rcx)\r
+ mov %r15,0x40(%rcx)\r
+ mov %rdx,0x48(%rcx)\r
+ # save non-volatile fp registers\r
+ stmxcsr 0x50(%rcx)\r
+ movdqu %xmm6, 0x58(%rcx) \r
+ movdqu %xmm7, 0x68(%rcx)\r
+ movdqu %xmm8, 0x78(%rcx)\r
+ movdqu %xmm9, 0x88(%rcx)\r
+ movdqu %xmm10, 0x98(%rcx)\r
+ movdqu %xmm11, 0xA8(%rcx)\r
+ movdqu %xmm12, 0xB8(%rcx)\r
+ movdqu %xmm13, 0xC8(%rcx)\r
+ movdqu %xmm14, 0xD8(%rcx)\r
+ movdqu %xmm15, 0xE8(%rcx) \r
+ xor %rax,%rax\r
+ jmpq *%rdx\r
+ \r
+ \r
+ASM_GLOBAL ASM_PFX(SetJump)\r
+ASM_PFX(SetJump):\r
+ pop %rdx\r
+ mov %rbx,(%rdi) # Rbx\r
+ mov %rsp,0x8(%rdi)\r
+ mov %rbp,0x10(%rdi)\r
+ mov %rcx,0x18(%rdi)\r
+ mov %rsi,0x20(%rdi)\r
+ mov %r12,0x28(%rdi)\r
+ mov %r13,0x30(%rdi)\r
+ mov %r14,0x38(%rdi)\r
+ mov %r15,0x40(%rdi)\r
+ mov %rdx,0x48(%rdi)\r
+ # save non-volatile fp registers\r
+ stmxcsr 0x50(%rdi)\r
+ movdqu %xmm6, 0x58(%rdi) \r
+ movdqu %xmm7, 0x68(%rdi)\r
+ movdqu %xmm8, 0x78(%rdi)\r
+ movdqu %xmm9, 0x88(%rdi)\r
+ movdqu %xmm10, 0x98(%rdi)\r
+ movdqu %xmm11, 0xA8(%rdi)\r
+ movdqu %xmm12, 0xB8(%rdi)\r
+ movdqu %xmm13, 0xC8(%rdi)\r
+ movdqu %xmm14, 0xD8(%rdi)\r
+ movdqu %xmm15, 0xE8(%rdi) \r
+ xor %rax,%rax\r
+ jmpq *%rdx\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; SetJump.Asm\r
+;\r
+; Abstract:\r
+;\r
+; Implementation of SetJump() on x64.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+EXTERNDEF InternalAssertJumpBuffer:PROC\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; SetJump (\r
+; OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
+; );\r
+;------------------------------------------------------------------------------\r
+SetJump PROC\r
+ push rcx\r
+ add rsp, -20h\r
+ call InternalAssertJumpBuffer\r
+ add rsp, 20h\r
+ pop rcx\r
+ pop rdx\r
+ mov [rcx], rbx\r
+ mov [rcx + 8], rsp\r
+ mov [rcx + 10h], rbp\r
+ mov [rcx + 18h], rdi\r
+ mov [rcx + 20h], rsi\r
+ mov [rcx + 28h], r12\r
+ mov [rcx + 30h], r13\r
+ mov [rcx + 38h], r14\r
+ mov [rcx + 40h], r15\r
+ mov [rcx + 48h], rdx\r
+ ; save non-volatile fp registers\r
+ stmxcsr [rcx + 50h]\r
+ movdqu [rcx + 58h], xmm6\r
+ movdqu [rcx + 68h], xmm7\r
+ movdqu [rcx + 78h], xmm8\r
+ movdqu [rcx + 88h], xmm9\r
+ movdqu [rcx + 98h], xmm10\r
+ movdqu [rcx + 0A8h], xmm11\r
+ movdqu [rcx + 0B8h], xmm12\r
+ movdqu [rcx + 0C8h], xmm13\r
+ movdqu [rcx + 0D8h], xmm14\r
+ movdqu [rcx + 0E8h], xmm15\r
+ xor rax, rax\r
+ jmp rdx\r
+SetJump ENDP\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# SwitchStack.S\r
+#\r
+# Abstract:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+\r
+#------------------------------------------------------------------------------\r
+# Routine Description:\r
+#\r
+# Routine for switching stacks with 2 parameters\r
+#\r
+# Arguments:\r
+#\r
+# (rcx) EntryPoint - Entry point with new stack.\r
+# (rdx) Context1 - Parameter1 for entry point.\r
+# (r8) Context2 - Parameter2 for entry point.\r
+# (r9) NewStack - The pointer to new stack.\r
+#\r
+# Returns:\r
+#\r
+# None\r
+#\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(EfiInternalSwitchStack)\r
+ASM_PFX(EfiInternalSwitchStack):\r
+ mov %rcx, %rax\r
+ mov %rdx, %rcx\r
+ mov %r8, %rdx\r
+ #\r
+ # Reserve space for register parameters (rcx, rdx, r8 & r9) on the stack,\r
+ # in case the callee wishes to spill them.\r
+ #\r
+ lea -0x20(%r9), %rsp\r
+ call *%rax\r
+\r
+\r
+\r
+#------------------------------------------------------------------------------\r
+# Routine Description:\r
+#\r
+# Routine for switching stacks with 2 parameters (Unix ABI)\r
+#\r
+# Arguments:\r
+#\r
+# (rdi) EntryPoint - Entry point with new stack.\r
+# (rsi) Context1 - Parameter1 for entry point.\r
+# (rdx) Context2 - Parameter2 for entry point.\r
+# (rcx) NewStack - The pointer to new stack.\r
+#\r
+# Returns:\r
+#\r
+# None\r
+#\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(InternalSwitchStack)\r
+ASM_PFX(InternalSwitchStack):\r
+ mov %rdi, %rax\r
+ mov %rsi, %rdi\r
+ mov %rdx, %rsi\r
+ #\r
+ # Reserve space for register parameters (rcx, rdx, r8 & r9) on the stack,\r
+ # in case the callee wishes to spill them.\r
+ #\r
+ lea -0x20(%rcx), %rsp\r
+ call *%rax\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; SwitchStack.Asm\r
+;\r
+; Abstract:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; Routine Description:\r
+;\r
+; Routine for switching stacks with 2 parameters\r
+;\r
+; Arguments:\r
+;\r
+; (rcx) EntryPoint - Entry point with new stack.\r
+; (rdx) Context1 - Parameter1 for entry point.\r
+; (r8) Context2 - Parameter2 for entry point.\r
+; (r9) NewStack - The pointer to new stack.\r
+;\r
+; Returns:\r
+;\r
+; None\r
+;\r
+;------------------------------------------------------------------------------\r
+InternalSwitchStack PROC\r
+ mov rax, rcx\r
+ mov rcx, rdx\r
+ mov rdx, r8\r
+ ;\r
+ ; Reserve space for register parameters (rcx, rdx, r8 & r9) on the stack,\r
+ ; in case the callee wishes to spill them.\r
+ ;\r
+ lea rsp, [r9 - 20h]\r
+ call rax\r
+InternalSwitchStack ENDP\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# Thunk16.S\r
+#\r
+# Abstract:\r
+#\r
+# Real mode thunk\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <Library/BaseLib.h>\r
+\r
+ASM_GLOBAL ASM_PFX(m16Start)\r
+ASM_GLOBAL ASM_PFX(m16Size)\r
+ASM_GLOBAL ASM_PFX(mThunk16Attr)\r
+ASM_GLOBAL ASM_PFX(m16Gdt)\r
+ASM_GLOBAL ASM_PFX(m16GdtrBase)\r
+ASM_GLOBAL ASM_PFX(mTransition)\r
+ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
+\r
+# define the structure of IA32_REGS\r
+.set _EDI, 0 #size 4\r
+.set _ESI, 4 #size 4\r
+.set _EBP, 8 #size 4\r
+.set _ESP, 12 #size 4\r
+.set _EBX, 16 #size 4\r
+.set _EDX, 20 #size 4\r
+.set _ECX, 24 #size 4\r
+.set _EAX, 28 #size 4\r
+.set _DS, 32 #size 2\r
+.set _ES, 34 #size 2\r
+.set _FS, 36 #size 2\r
+.set _GS, 38 #size 2\r
+.set _EFLAGS, 40 #size 8\r
+.set _EIP, 48 #size 4\r
+.set _CS, 52 #size 2\r
+.set _SS, 54 #size 2\r
+.set IA32_REGS_SIZE, 56\r
+\r
+ .data\r
+\r
+ASM_PFX(m16Size): .word ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
+ASM_PFX(mThunk16Attr): .word _ThunkAttr - ASM_PFX(m16Start)\r
+ASM_PFX(m16Gdt): .word ASM_PFX(NullSeg) - ASM_PFX(m16Start)\r
+ASM_PFX(m16GdtrBase): .word _16GdtrBase - ASM_PFX(m16Start)\r
+ASM_PFX(mTransition): .word _EntryPoint - ASM_PFX(m16Start)\r
+\r
+ .text\r
+\r
+ASM_PFX(m16Start):\r
+\r
+SavedGdt: .space 10\r
+\r
+#------------------------------------------------------------------------------\r
+# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
+# by user code. It will be shadowed to somewhere in memory below 1MB.\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(BackFromUserCode)\r
+ASM_PFX(BackFromUserCode):\r
+ #\r
+ # The order of saved registers on the stack matches the order they appears\r
+ # in IA32_REGS structure. This facilitates wrapper function to extract them\r
+ # into that structure.\r
+ #\r
+ # Some instructions for manipulation of segment registers have to be written\r
+ # in opcode since 64-bit MASM prevents accesses to those registers.\r
+ #\r
+ .byte 0x16 # push ss\r
+ .byte 0xe # push cs\r
+ .byte 0x66\r
+ call L_Base # push eip\r
+L_Base: \r
+ .byte 0x66\r
+ pushq $0 # reserved high order 32 bits of EFlags\r
+ .byte 0x66, 0x9c # pushfd actually\r
+ cli # disable interrupts\r
+ push %gs\r
+ push %fs\r
+ .byte 6 # push es\r
+ .byte 0x1e # push ds\r
+ .byte 0x66,0x60 # pushad\r
+ .byte 0x66,0xba # mov edx, imm32\r
+_ThunkAttr: .space 4\r
+ testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
+ jz L_1\r
+ movl $0x15cd2401,%eax # mov ax, 2401h & int 15h\r
+ cli # disable interrupts\r
+ jnc L_2\r
+L_1: \r
+ testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
+ jz L_2\r
+ inb $0x92,%al\r
+ orb $2,%al\r
+ outb %al, $0x92 # deactivate A20M#\r
+L_2: \r
+ movl %ss,%eax\r
+ lea IA32_REGS_SIZE(%esp), %bp\r
+ #\r
+ # rsi in the following 2 instructions is indeed bp in 16-bit code\r
+ #\r
+ movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
+ .byte 0x66\r
+ movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
+ shlw $4,%ax # shl eax, 4\r
+ addw %ax,%bp # add ebp, eax\r
+ movw %cs,%ax\r
+ shlw $4,%ax\r
+ lea (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
+ .byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (L_64Eip - L_Base)], eax\r
+ .word L_64Eip - L_Base\r
+ .byte 0x66,0xb8 # mov eax, imm32\r
+SavedCr4: .space 4\r
+ movq %rax, %cr4\r
+ #\r
+ # rdi in the instruction below is indeed bx in 16-bit code\r
+ #\r
+ .byte 0x66,0x2e # 2eh is "cs:" segment override\r
+ lgdt (SavedGdt - L_Base)(%rdi)\r
+ .byte 0x66\r
+ movl $0xc0000080,%ecx\r
+ rdmsr\r
+ orb $1,%ah\r
+ wrmsr\r
+ .byte 0x66,0xb8 # mov eax, imm32\r
+SavedCr0: .space 4\r
+ movq %rax, %cr0\r
+ .byte 0x66,0xea # jmp far cs:L_64Bit\r
+L_64Eip: .space 4\r
+SavedCs: .space 2\r
+L_64BitCode: \r
+ .byte 0x90\r
+ .byte 0x67,0xbc # mov esp, imm32\r
+SavedSp: .space 4 # restore stack\r
+ nop\r
+ ret\r
+\r
+_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
+ .word CODE16\r
+_16Gdtr: .word GDT_SIZE - 1\r
+_16GdtrBase: .quad ASM_PFX(NullSeg)\r
+_16Idtr: .word 0x3ff\r
+ .long 0\r
+\r
+#------------------------------------------------------------------------------\r
+# _ToUserCode() takes control in real mode before passing control to user code.\r
+# It will be shadowed to somewhere in memory below 1MB.\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(ToUserCode)\r
+ASM_PFX(ToUserCode):\r
+ movl %edx,%ss # set new segment selectors\r
+ movl %edx,%ds\r
+ movl %edx,%es\r
+ movl %edx,%fs\r
+ movl %edx,%gs\r
+ .byte 0x66\r
+ movl $0xc0000080,%ecx\r
+ movq %rax, %cr0\r
+ rdmsr\r
+ andb $0xfe, %ah # $0b11111110\r
+ wrmsr\r
+ movq %rbp, %cr4\r
+ movl %esi,%ss # set up 16-bit stack segment\r
+ movw %bx,%sp # set up 16-bit stack pointer\r
+ .byte 0x66 # make the following call 32-bit\r
+ call L_Base1 # push eip\r
+L_Base1: \r
+ popw %bp # ebp <- address of L_Base1\r
+ pushq (IA32_REGS_SIZE + 2)(%esp)\r
+ lea 0x0c(%rsi), %eax\r
+ pushq %rax\r
+ lret # execution begins at next instruction\r
+L_RealMode: \r
+ .byte 0x66,0x2e # CS and operand size override\r
+ lidt (_16Idtr - L_Base1)(%rsi)\r
+ .byte 0x66,0x61 # popad\r
+ .byte 0x1f # pop ds\r
+ .byte 0x7 # pop es\r
+ .byte 0x0f, 0xa1 # pop fs\r
+ .byte 0x0f, 0xa9 # pop gs\r
+ .byte 0x66, 0x9d # popfd\r
+ leaw 4(%esp),%sp # skip high order 32 bits of EFlags\r
+ .byte 0x66 # make the following retf 32-bit\r
+ lret # transfer control to user code\r
+\r
+.set CODE16, ASM_PFX(_16Code) - .\r
+.set DATA16, ASM_PFX(_16Data) - .\r
+.set DATA32, ASM_PFX(_32Data) - .\r
+\r
+ASM_PFX(NullSeg): .quad 0\r
+ASM_PFX(_16Code):\r
+ .word -1\r
+ .word 0\r
+ .byte 0\r
+ .byte 0x9b\r
+ .byte 0x8f # 16-bit segment, 4GB limit\r
+ .byte 0\r
+ASM_PFX(_16Data):\r
+ .word -1\r
+ .word 0\r
+ .byte 0\r
+ .byte 0x93\r
+ .byte 0x8f # 16-bit segment, 4GB limit\r
+ .byte 0\r
+ASM_PFX(_32Data):\r
+ .word -1\r
+ .word 0\r
+ .byte 0\r
+ .byte 0x93\r
+ .byte 0xcf # 16-bit segment, 4GB limit\r
+ .byte 0\r
+\r
+.set GDT_SIZE, . - ASM_PFX(NullSeg)\r
+\r
+#------------------------------------------------------------------------------\r
+# IA32_REGISTER_SET *\r
+# EFIAPI\r
+# InternalAsmThunk16 (\r
+# IN IA32_REGISTER_SET *RegisterSet,\r
+# IN OUT VOID *Transition\r
+# );\r
+#------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(InternalAsmThunk16)\r
+ASM_PFX(InternalAsmThunk16):\r
+ pushq %rbp\r
+ pushq %rbx\r
+ pushq %rsi\r
+ pushq %rdi\r
+ \r
+ movl %ds, %ebx\r
+ pushq %rbx # Save ds segment register on the stack\r
+ movl %es, %ebx\r
+ pushq %rbx # Save es segment register on the stack\r
+ movl %ss, %ebx\r
+ pushq %rbx # Save ss segment register on the stack\r
+\r
+ .byte 0x0f, 0xa0 #push fs\r
+ .byte 0x0f, 0xa8 #push gs\r
+ movq %rcx, %rsi\r
+ movzwl _SS(%rsi), %r8d\r
+ movl _ESP(%rsi), %edi\r
+ lea -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
+ imul $16, %r8d, %eax \r
+ movl %edi,%ebx # ebx <- stack for 16-bit code\r
+ pushq $(IA32_REGS_SIZE / 4)\r
+ addl %eax,%edi # edi <- linear address of 16-bit stack\r
+ popq %rcx\r
+ rep\r
+ movsl # copy RegSet\r
+ lea (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
+ movl %edx,%eax # eax <- transition code address\r
+ andl $0xf,%edx\r
+ shll $12,%eax # segment address in high order 16 bits\r
+ lea (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%rdx), %ax\r
+ stosl # [edi] <- return address of user code\r
+ sgdt 0x60(%rsp) # save GDT stack in argument space\r
+ movzwq 0x60(%rsp), %r10 # r10 <- GDT limit \r
+ lea ((ASM_PFX(InternalAsmThunk16) - SavedCr4) + 0xf)(%rcx), %r11 \r
+ andq $0xfffffffffffffff0, %r11 # r11 <- 16-byte aligned shadowed GDT table in real mode buffer \r
+ \r
+ movw %r10w, (SavedGdt - SavedCr4)(%rcx) # save the limit of shadowed GDT table\r
+ movq %r11, (SavedGdt - SavedCr4 + 0x2)(%rcx) # save the base address of shadowed GDT table\r
+ \r
+ movq 0x62(%rsp) ,%rsi # rsi <- the original GDT base address\r
+ xchg %r10, %rcx # save rcx to r10 and initialize rcx to be the limit of GDT table \r
+ incq %rcx # rcx <- the size of memory to copy\r
+ xchg %r11, %rdi # save rdi to r11 and initialize rdi to the base address of shadowed GDT table\r
+ rep\r
+ movsb # perform memory copy to shadow GDT table\r
+ movq %r10, %rcx # restore the orignal rcx before memory copy\r
+ movq %r11, %rdi # restore the original rdi before memory copy\r
+ \r
+ sidt 0x50(%rsp)\r
+ movq %cr0, %rax\r
+ movl %eax, (SavedCr0 - SavedCr4)(%rcx)\r
+ andl $0x7ffffffe,%eax # clear PE, PG bits\r
+ movq %cr4, %rbp\r
+ movl %ebp, (%rcx) # save CR4 in SavedCr4\r
+ andl $0x300,%ebp # clear all but PCE and OSFXSR bits\r
+ movl %r8d, %esi # esi <- 16-bit stack segment\r
+ .byte 0x6a, DATA32\r
+ popq %rdx\r
+ lgdt (_16Gdtr - SavedCr4)(%rcx)\r
+ movl %edx,%ss\r
+ pushfq\r
+ lea -8(%rdx), %edx\r
+ lea L_RetFromRealMode(%rip), %r8\r
+ pushq %r8\r
+ movl %cs, %r8d\r
+ movw %r8w, (SavedCs - SavedCr4)(%rcx)\r
+ movl %esp, (SavedSp - SavedCr4)(%rcx)\r
+ .byte 0xff, 0x69 # jmp (_EntryPoint - SavedCr4)(%rcx)\r
+ .byte _EntryPoint - SavedCr4\r
+L_RetFromRealMode: \r
+ popfq\r
+ lgdt 0x60(%rsp) # restore protected mode GDTR\r
+ lidt 0x50(%rsp) # restore protected mode IDTR\r
+ lea -IA32_REGS_SIZE(%rbp), %eax\r
+ .byte 0x0f, 0xa9 # pop gs\r
+ .byte 0x0f, 0xa1 # pop fs\r
+ \r
+ popq %rbx\r
+ movl %ebx, %ss\r
+ popq %rbx\r
+ movl %ebx, %es\r
+ popq %rbx\r
+ movl %ebx, %ds\r
+ \r
+ popq %rdi\r
+ popq %rsi\r
+ popq %rbx\r
+ popq %rbp\r
+\r
+ ret\r
--- /dev/null
+\r
+#include "BaseLibInternals.h"\r
+\r
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; Thunk.asm\r
+;\r
+; Abstract:\r
+;\r
+; Real mode thunk\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+EXTERNDEF m16Start:BYTE\r
+EXTERNDEF m16Size:WORD\r
+EXTERNDEF mThunk16Attr:WORD\r
+EXTERNDEF m16Gdt:WORD\r
+EXTERNDEF m16GdtrBase:WORD\r
+EXTERNDEF mTransition:WORD\r
+\r
+IA32_REGS STRUC 4t\r
+_EDI DD ?\r
+_ESI DD ?\r
+_EBP DD ?\r
+_ESP DD ?\r
+_EBX DD ?\r
+_EDX DD ?\r
+_ECX DD ?\r
+_EAX DD ?\r
+_DS DW ?\r
+_ES DW ?\r
+_FS DW ?\r
+_GS DW ?\r
+_EFLAGS DQ ?\r
+_EIP DD ?\r
+_CS DW ?\r
+_SS DW ?\r
+IA32_REGS ENDS\r
+\r
+ .const\r
+\r
+m16Size DW InternalAsmThunk16 - m16Start\r
+mThunk16Attr DW _ThunkAttr - m16Start\r
+m16Gdt DW _NullSeg - m16Start\r
+m16GdtrBase DW _16GdtrBase - m16Start\r
+mTransition DW _EntryPoint - m16Start\r
+\r
+ .code\r
+\r
+m16Start LABEL BYTE\r
+\r
+SavedGdt LABEL FWORD\r
+ DW ?\r
+ DQ ?\r
+\r
+;------------------------------------------------------------------------------\r
+; _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
+; by user code. It will be shadowed to somewhere in memory below 1MB.\r
+;------------------------------------------------------------------------------\r
+_BackFromUserCode PROC\r
+ ;\r
+ ; The order of saved registers on the stack matches the order they appears\r
+ ; in IA32_REGS structure. This facilitates wrapper function to extract them\r
+ ; into that structure.\r
+ ;\r
+ ; Some instructions for manipulation of segment registers have to be written\r
+ ; in opcode since 64-bit MASM prevents accesses to those registers.\r
+ ;\r
+ DB 16h ; push ss\r
+ DB 0eh ; push cs\r
+ DB 66h\r
+ call @Base ; push eip\r
+@Base:\r
+ DB 66h\r
+ push 0 ; reserved high order 32 bits of EFlags\r
+ pushf ; pushfd actually\r
+ cli ; disable interrupts\r
+ push gs\r
+ push fs\r
+ DB 6 ; push es\r
+ DB 1eh ; push ds\r
+ DB 66h, 60h ; pushad\r
+ DB 66h, 0bah ; mov edx, imm32\r
+_ThunkAttr DD ?\r
+ test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15\r
+ jz @1\r
+ mov eax, 15cd2401h ; mov ax, 2401h & int 15h\r
+ cli ; disable interrupts\r
+ jnc @2\r
+@1:\r
+ test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL\r
+ jz @2\r
+ in al, 92h\r
+ or al, 2\r
+ out 92h, al ; deactivate A20M#\r
+@2:\r
+ mov eax, ss\r
+ lea bp, [esp + sizeof (IA32_REGS)]\r
+ ;\r
+ ; rsi in the following 2 instructions is indeed bp in 16-bit code\r
+ ;\r
+ mov word ptr (IA32_REGS ptr [rsi - sizeof (IA32_REGS)])._ESP, bp\r
+ DB 66h\r
+ mov ebx, (IA32_REGS ptr [rsi - sizeof (IA32_REGS)])._EIP\r
+ shl ax, 4 ; shl eax, 4\r
+ add bp, ax ; add ebp, eax\r
+ mov ax, cs\r
+ shl ax, 4\r
+ lea ax, [eax + ebx + (@64BitCode - @Base)]\r
+ DB 66h, 2eh, 89h, 87h ; mov cs:[bx + (@64Eip - @Base)], eax\r
+ DW @64Eip - @Base\r
+ DB 66h, 0b8h ; mov eax, imm32\r
+SavedCr4 DD ?\r
+ mov cr4, rax\r
+ ;\r
+ ; rdi in the instruction below is indeed bx in 16-bit code\r
+ ;\r
+ DB 66h, 2eh ; 2eh is "cs:" segment override\r
+ lgdt fword ptr [rdi + (SavedGdt - @Base)]\r
+ DB 66h\r
+ mov ecx, 0c0000080h\r
+ rdmsr\r
+ or ah, 1\r
+ wrmsr\r
+ DB 66h, 0b8h ; mov eax, imm32\r
+SavedCr0 DD ?\r
+ mov cr0, rax\r
+ DB 66h, 0eah ; jmp far cs:@64Bit\r
+@64Eip DD ?\r
+SavedCs DW ?\r
+@64BitCode:\r
+ db 090h \r
+ db 067h, 0bch ; mov esp, imm32\r
+SavedSp DD ? ; restore stack\r
+ nop\r
+ ret\r
+_BackFromUserCode ENDP\r
+\r
+_EntryPoint DD _ToUserCode - m16Start\r
+ DW CODE16\r
+_16Gdtr LABEL FWORD\r
+ DW GDT_SIZE - 1\r
+_16GdtrBase DQ _NullSeg\r
+_16Idtr FWORD (1 SHL 10) - 1\r
+\r
+;------------------------------------------------------------------------------\r
+; _ToUserCode() takes control in real mode before passing control to user code.\r
+; It will be shadowed to somewhere in memory below 1MB.\r
+;------------------------------------------------------------------------------\r
+_ToUserCode PROC\r
+ mov ss, edx ; set new segment selectors\r
+ mov ds, edx\r
+ mov es, edx\r
+ mov fs, edx\r
+ mov gs, edx\r
+ DB 66h\r
+ mov ecx, 0c0000080h\r
+ mov cr0, rax ; real mode starts at next instruction\r
+ rdmsr\r
+ and ah, NOT 1\r
+ wrmsr\r
+ mov cr4, rbp\r
+ mov ss, esi ; set up 16-bit stack segment\r
+ mov sp, bx ; set up 16-bit stack pointer\r
+ DB 66h ; make the following call 32-bit\r
+ call @Base ; push eip\r
+@Base:\r
+ pop bp ; ebp <- address of @Base\r
+ push [esp + sizeof (IA32_REGS) + 2]\r
+ lea eax, [rsi + (@RealMode - @Base)] ; rsi is "bp" in 16-bit code\r
+ push rax\r
+ retf ; execution begins at next instruction\r
+@RealMode:\r
+ DB 66h, 2eh ; CS and operand size override\r
+ lidt fword ptr [rsi + (_16Idtr - @Base)]\r
+ DB 66h, 61h ; popad\r
+ DB 1fh ; pop ds\r
+ DB 07h ; pop es\r
+ pop fs\r
+ pop gs\r
+ popf ; popfd\r
+ lea sp, [esp + 4] ; skip high order 32 bits of EFlags\r
+ DB 66h ; make the following retf 32-bit\r
+ retf ; transfer control to user code\r
+_ToUserCode ENDP\r
+\r
+CODE16 = _16Code - $\r
+DATA16 = _16Data - $\r
+DATA32 = _32Data - $\r
+\r
+_NullSeg DQ 0\r
+_16Code LABEL QWORD\r
+ DW -1\r
+ DW 0\r
+ DB 0\r
+ DB 9bh\r
+ DB 8fh ; 16-bit segment, 4GB limit\r
+ DB 0\r
+_16Data LABEL QWORD\r
+ DW -1\r
+ DW 0\r
+ DB 0\r
+ DB 93h\r
+ DB 8fh ; 16-bit segment, 4GB limit\r
+ DB 0\r
+_32Data LABEL QWORD\r
+ DW -1\r
+ DW 0\r
+ DB 0\r
+ DB 93h\r
+ DB 0cfh ; 16-bit segment, 4GB limit\r
+ DB 0\r
+\r
+GDT_SIZE = $ - _NullSeg\r
+\r
+;------------------------------------------------------------------------------\r
+; IA32_REGISTER_SET *\r
+; EFIAPI\r
+; InternalAsmThunk16 (\r
+; IN IA32_REGISTER_SET *RegisterSet,\r
+; IN OUT VOID *Transition\r
+; );\r
+;------------------------------------------------------------------------------\r
+InternalAsmThunk16 PROC USES rbp rbx rsi rdi\r
+ mov rbx, ds\r
+ push rbx ; Save ds segment register on the stack\r
+ mov rbx, es\r
+ push rbx ; Save es segment register on the stack\r
+ mov rbx, ss\r
+ push rbx ; Save ss segment register on the stack\r
+ \r
+ push fs\r
+ push gs\r
+ mov rsi, rcx\r
+ movzx r8d, (IA32_REGS ptr [rsi])._SS\r
+ mov edi, (IA32_REGS ptr [rsi])._ESP\r
+ lea rdi, [edi - (sizeof (IA32_REGS) + 4)]\r
+ imul eax, r8d, 16 ; eax <- r8d(stack segment) * 16\r
+ mov ebx, edi ; ebx <- stack for 16-bit code\r
+ push sizeof (IA32_REGS) / 4\r
+ add edi, eax ; edi <- linear address of 16-bit stack\r
+ pop rcx\r
+ rep movsd ; copy RegSet\r
+ lea ecx, [rdx + (SavedCr4 - m16Start)]\r
+ mov eax, edx ; eax <- transition code address\r
+ and edx, 0fh\r
+ shl eax, 12 ; segment address in high order 16 bits\r
+ lea ax, [rdx + (_BackFromUserCode - m16Start)] ; offset address\r
+ stosd ; [edi] <- return address of user code\r
+ \r
+ sgdt fword ptr [rsp + 60h] ; save GDT stack in argument space\r
+ movzx r10, word ptr [rsp + 60h] ; r10 <- GDT limit \r
+ lea r11, [rcx + (InternalAsmThunk16 - SavedCr4) + 0xf]\r
+ and r11, 0xfffffff0 ; r11 <- 16-byte aligned shadowed GDT table in real mode buffer\r
+ \r
+ mov word ptr [rcx + (SavedGdt - SavedCr4)], r10w ; save the limit of shadowed GDT table\r
+ mov qword ptr [rcx + (SavedGdt - SavedCr4) + 2], r11 ; save the base address of shadowed GDT table\r
+ \r
+ mov rsi, qword ptr [rsp + 62h] ; rsi <- the original GDT base address\r
+ xchg rcx, r10 ; save rcx to r10 and initialize rcx to be the limit of GDT table\r
+ inc rcx ; rcx <- the size of memory to copy\r
+ xchg rdi, r11 ; save rdi to r11 and initialize rdi to the base address of shadowed GDT table\r
+ rep movsb ; perform memory copy to shadow GDT table\r
+ mov rcx, r10 ; restore the orignal rcx before memory copy\r
+ mov rdi, r11 ; restore the original rdi before memory copy\r
+ \r
+ sidt fword ptr [rsp + 50h] ; save IDT stack in argument space\r
+ mov rax, cr0\r
+ mov [rcx + (SavedCr0 - SavedCr4)], eax\r
+ and eax, 7ffffffeh ; clear PE, PG bits\r
+ mov rbp, cr4\r
+ mov [rcx], ebp ; save CR4 in SavedCr4\r
+ and ebp, 300h ; clear all but PCE and OSFXSR bits\r
+ mov esi, r8d ; esi <- 16-bit stack segment\r
+ DB 6ah, DATA32 ; push DATA32\r
+ pop rdx ; rdx <- 32-bit data segment selector\r
+ lgdt fword ptr [rcx + (_16Gdtr - SavedCr4)]\r
+ mov ss, edx\r
+ pushfq\r
+ lea edx, [rdx + DATA16 - DATA32]\r
+ lea r8, @RetFromRealMode\r
+ push r8\r
+ mov r8d, cs\r
+ mov [rcx + (SavedCs - SavedCr4)], r8w\r
+ mov [rcx + (SavedSp - SavedCr4)], esp\r
+ jmp fword ptr [rcx + (_EntryPoint - SavedCr4)]\r
+@RetFromRealMode:\r
+ popfq\r
+ lgdt fword ptr [rsp + 60h] ; restore protected mode GDTR\r
+ lidt fword ptr [rsp + 50h] ; restore protected mode IDTR\r
+ lea eax, [rbp - sizeof (IA32_REGS)]\r
+ pop gs\r
+ pop fs\r
+ pop rbx\r
+ mov ss, rbx\r
+ pop rbx\r
+ mov es, rbx\r
+ pop rbx\r
+ mov ds, rbx\r
+ ret\r
+InternalAsmThunk16 ENDP\r
+\r
+ END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# Wbinvd.S\r
+#\r
+# Abstract:\r
+#\r
+# AsmWbinvd function\r
+#\r
+# Notes:\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# AsmWbinvd (\r
+# VOID\r
+# );\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(AsmWbinvd)\r
+ASM_PFX(AsmWbinvd):\r
+ wbinvd\r
+ ret\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; Wbinvd.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWbinvd function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmWbinvd (\r
+; VOID\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWbinvd PROC\r
+ wbinvd\r
+ ret\r
+AsmWbinvd ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteCr0.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteCr0 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteCr0 (\r
+; UINTN Cr0\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteCr0 PROC\r
+ mov cr0, rcx\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteCr0 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteCr2.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteCr2 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteCr2 (\r
+; UINTN Cr2\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteCr2 PROC\r
+ mov cr2, rcx\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteCr2 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteCr3.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteCr3 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteCr3 (\r
+; UINTN Cr3\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteCr3 PROC\r
+ mov cr3, rcx\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteCr3 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteCr4.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteCr4 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteCr4 (\r
+; UINTN Cr4\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteCr4 PROC\r
+ mov cr4, rcx\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteCr4 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteDr0.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteDr0 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteDr0 (\r
+; IN UINTN Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteDr0 PROC\r
+ mov dr0, rcx\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteDr0 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteDr1.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteDr1 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteDr1 (\r
+; IN UINTN Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteDr1 PROC\r
+ mov dr1, rcx\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteDr1 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteDr2.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteDr2 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteDr2 (\r
+; IN UINTN Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteDr2 PROC\r
+ mov dr2, rcx\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteDr2 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteDr3.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteDr3 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteDr3 (\r
+; IN UINTN Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteDr3 PROC\r
+ mov dr3, rcx\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteDr3 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteDr4.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteDr4 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteDr4 (\r
+; IN UINTN Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteDr4 PROC\r
+ ;\r
+ ; There's no obvious reason to access this register, since it's aliased to\r
+ ; DR6 when DE=0 or an exception generated when DE=1\r
+ ;\r
+ DB 0fh, 23h, 0e1h\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteDr4 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteDr5.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteDr5 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteDr5 (\r
+; IN UINTN Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteDr5 PROC\r
+ ;\r
+ ; There's no obvious reason to access this register, since it's aliased to\r
+ ; DR7 when DE=0 or an exception generated when DE=1\r
+ ;\r
+ DB 0fh, 23h, 0e9h\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteDr5 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteDr6.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteDr6 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteDr6 (\r
+; IN UINTN Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteDr6 PROC\r
+ mov dr6, rcx\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteDr6 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteDr7.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteDr7 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EFIAPI\r
+; AsmWriteDr7 (\r
+; IN UINTN Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteDr7 PROC\r
+ mov dr7, rcx\r
+ mov rax, rcx\r
+ ret\r
+AsmWriteDr7 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteGdtr.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteGdtr function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; InternalX86WriteGdtr (\r
+; IN CONST IA32_DESCRIPTOR *Idtr\r
+; );\r
+;------------------------------------------------------------------------------\r
+InternalX86WriteGdtr PROC\r
+ lgdt fword ptr [rcx]\r
+ ret\r
+InternalX86WriteGdtr ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteIdtr.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteIdtr function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; InternalX86WriteIdtr (\r
+; IN CONST IA32_DESCRIPTOR *Idtr\r
+; );\r
+;------------------------------------------------------------------------------\r
+InternalX86WriteIdtr PROC\r
+ pushfq\r
+ cli\r
+ lidt fword ptr [rcx]\r
+ popfq\r
+ ret\r
+InternalX86WriteIdtr ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteLdtr.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteLdtr function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmWriteLdtr (\r
+; IN UINT16 Ldtr\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteLdtr PROC\r
+ lldt cx\r
+ ret\r
+AsmWriteLdtr ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteMm0.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteMm0 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmWriteMm0 (\r
+; IN UINT64 Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteMm0 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 6eh, 0c1h\r
+ ret\r
+AsmWriteMm0 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteMm1.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteMm1 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmWriteMm1 (\r
+; IN UINT64 Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteMm1 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 6eh, 0c9h\r
+ ret\r
+AsmWriteMm1 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteMm2.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteMm2 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmWriteMm2 (\r
+; IN UINT64 Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteMm2 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 6eh, 0d1h\r
+ ret\r
+AsmWriteMm2 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteMm3.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteMm3 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmWriteMm3 (\r
+; IN UINT64 Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteMm3 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 6eh, 0d9h\r
+ ret\r
+AsmWriteMm3 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteMm4.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteMm4 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmWriteMm4 (\r
+; IN UINT64 Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteMm4 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 6eh, 0e1h\r
+ ret\r
+AsmWriteMm4 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteMm5.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteMm5 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmWriteMm5 (\r
+; IN UINT64 Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteMm5 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 6eh, 0e9h\r
+ ret\r
+AsmWriteMm5 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteMm6.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteMm6 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmWriteMm6 (\r
+; IN UINT64 Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteMm6 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 6eh, 0f1h\r
+ ret\r
+AsmWriteMm6 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteMm7.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteMm7 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; AsmWriteMm7 (\r
+; IN UINT64 Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteMm7 PROC\r
+ ;\r
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
+ ;\r
+ DB 48h, 0fh, 6eh, 0f9h\r
+ ret\r
+AsmWriteMm7 ENDP\r
+\r
+ END\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; WriteMsr64.Asm\r
+;\r
+; Abstract:\r
+;\r
+; AsmWriteMsr64 function\r
+;\r
+; Notes:\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+ .code\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EFIAPI\r
+; AsmWriteMsr64 (\r
+; IN UINT32 Index,\r
+; IN UINT64 Value\r
+; );\r
+;------------------------------------------------------------------------------\r
+AsmWriteMsr64 PROC\r
+ mov rax, rdx ; meanwhile, rax <- return value\r
+ shr rdx, 20h ; edx:eax contains the value to write\r
+ wrmsr\r
+ ret\r
+AsmWriteMsr64 ENDP\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+ CpuBreakpoint function.\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+/**\r
+ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
+**/\r
+\r
+void __writemsr (unsigned long Register, unsigned __int64 Value);\r
+\r
+#pragma intrinsic(__writemsr)\r
+\r
+/**\r
+ Write data to MSR.\r
+\r
+ @param Index The register index of MSR.\r
+ @param Value Data wants to be written.\r
+\r
+ @return Value written to MSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmWriteMsr64 (\r
+ IN UINT32 Index,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ __writemsr (Index, Value);\r
+ return Value;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ IA-32/x64 AsmDisablePaging32()\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Disables the 32-bit paging mode on the CPU.\r
+\r
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected\r
+ mode. This function assumes the current execution mode is 32-paged protected\r
+ mode. This function is only available on IA-32. After the 32-bit paging mode\r
+ is disabled, control is transferred to the function specified by EntryPoint\r
+ using the new stack specified by NewStack and passing in the parameters\r
+ specified by Context1 and Context2. Context1 and Context2 are optional and\r
+ may be NULL. The function EntryPoint must never return.\r
+\r
+ If the current execution mode is not 32-bit paged mode, then ASSERT().\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ There are a number of constraints that must be followed before calling this\r
+ function:\r
+ 1) Interrupts must be disabled.\r
+ 2) The caller must be in 32-bit paged mode.\r
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.\r
+ 4) CR3 must point to valid page tables that guarantee that the pages for\r
+ this function and the stack are identity mapped.\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack after\r
+ paging is disabled.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function as the first parameter after paging is disabled.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function as the second parameter after paging is\r
+ disabled.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function after paging is disabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmDisablePaging32 (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack\r
+ )\r
+{\r
+ ASSERT (EntryPoint != NULL);\r
+ ASSERT (NewStack != NULL);\r
+ InternalX86DisablePaging32 (EntryPoint, Context1, Context2, NewStack);\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 AsmDisablePaging64()\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Disables the 64-bit paging mode on the CPU.\r
+\r
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r
+ mode. This function assumes the current execution mode is 64-paging mode.\r
+ This function is only available on x64. After the 64-bit paging mode is\r
+ disabled, control is transferred to the function specified by EntryPoint\r
+ using the new stack specified by NewStack and passing in the parameters\r
+ specified by Context1 and Context2. Context1 and Context2 are optional and\r
+ may be 0. The function EntryPoint must never return.\r
+\r
+ If the current execution mode is not 64-bit paged mode, then ASSERT().\r
+ If EntryPoint is 0, then ASSERT().\r
+ If NewStack is 0, then ASSERT().\r
+\r
+ @param Cs The 16-bit selector to load in the CS before EntryPoint\r
+ is called. The descriptor in the GDT that this selector\r
+ references must be setup for 32-bit protected mode.\r
+ @param EntryPoint The 64-bit virtual address of the function to call with\r
+ the new stack after paging is disabled.\r
+ @param Context1 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the first parameter after\r
+ paging is disabled.\r
+ @param Context2 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the second parameter after\r
+ paging is disabled.\r
+ @param NewStack The 64-bit virtual address of the new stack to use for\r
+ the EntryPoint function after paging is disabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmDisablePaging64 (\r
+ IN UINT16 Cs,\r
+ IN UINT32 EntryPoint,\r
+ IN UINT32 Context1, OPTIONAL\r
+ IN UINT32 Context2, OPTIONAL\r
+ IN UINT32 NewStack\r
+ )\r
+{\r
+ ASSERT (EntryPoint != 0);\r
+ ASSERT (NewStack != 0);\r
+ InternalX86DisablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 AsmEnablePaging32()\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Enables the 32-bit paging mode on the CPU.\r
+\r
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r
+ must be properly initialized prior to calling this service. This function\r
+ assumes the current execution mode is 32-bit protected mode. This function is\r
+ only available on IA-32. After the 32-bit paging mode is enabled, control is\r
+ transferred to the function specified by EntryPoint using the new stack\r
+ specified by NewStack and passing in the parameters specified by Context1 and\r
+ Context2. Context1 and Context2 are optional and may be NULL. The function\r
+ EntryPoint must never return.\r
+\r
+ If the current execution mode is not 32-bit protected mode, then ASSERT().\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ There are a number of constraints that must be followed before calling this\r
+ function:\r
+ 1) Interrupts must be disabled.\r
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This\r
+ means all descriptors must have a base of 0 and a limit of 4GB.\r
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat\r
+ descriptors.\r
+ 4) CR3 must point to valid page tables that will be used once the transition\r
+ is complete, and those page tables must guarantee that the pages for this\r
+ function and the stack are identity mapped.\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack after\r
+ paging is enabled.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function as the first parameter after paging is enabled.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function as the second parameter after paging is enabled.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function after paging is enabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmEnablePaging32 (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *NewStack\r
+ )\r
+{\r
+ ASSERT (EntryPoint != NULL);\r
+ ASSERT (NewStack != NULL);\r
+ InternalX86EnablePaging32 (EntryPoint, Context1, Context2, NewStack);\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 AsmEnablePaging64()\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Enables the 64-bit paging mode on the CPU.\r
+\r
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r
+ must be properly initialized prior to calling this service. This function\r
+ assumes the current execution mode is 32-bit protected mode with flat\r
+ descriptors. This function is only available on IA-32. After the 64-bit\r
+ paging mode is enabled, control is transferred to the function specified by\r
+ EntryPoint using the new stack specified by NewStack and passing in the\r
+ parameters specified by Context1 and Context2. Context1 and Context2 are\r
+ optional and may be 0. The function EntryPoint must never return.\r
+\r
+ If the current execution mode is not 32-bit protected mode with flat\r
+ descriptors, then ASSERT().\r
+ If EntryPoint is 0, then ASSERT().\r
+ If NewStack is 0, then ASSERT().\r
+\r
+ @param Cs The 16-bit selector to load in the CS before EntryPoint\r
+ is called. The descriptor in the GDT that this selector\r
+ references must be setup for long mode.\r
+ @param EntryPoint The 64-bit virtual address of the function to call with\r
+ the new stack after paging is enabled.\r
+ @param Context1 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the first parameter after\r
+ paging is enabled.\r
+ @param Context2 The 64-bit virtual address of the context to pass into\r
+ the EntryPoint function as the second parameter after\r
+ paging is enabled.\r
+ @param NewStack The 64-bit virtual address of the new stack to use for\r
+ the EntryPoint function after paging is enabled.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmEnablePaging64 (\r
+ IN UINT16 Cs,\r
+ IN UINT64 EntryPoint,\r
+ IN UINT64 Context1, OPTIONAL\r
+ IN UINT64 Context2, OPTIONAL\r
+ IN UINT64 NewStack\r
+ )\r
+{\r
+ ASSERT (EntryPoint != 0);\r
+ ASSERT (NewStack != 0);\r
+ InternalX86EnablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 AsmFxRestore()\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Restores the current floating point/SSE/SSE2 context from a buffer.\r
+\r
+ Restores the current floating point/SSE/SSE2 state from the buffer specified\r
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is\r
+ only available on IA-32 and x64.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 16-byte boundary, then ASSERT().\r
+ If Buffer was not saved with AsmFxSave(), then ASSERT().\r
+\r
+ @param Buffer A pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmFxRestore (\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+ ASSERT (0 == ((UINTN)Buffer & 0xf));\r
+\r
+ //\r
+ // Check the flag recorded by AsmFxSave()\r
+ //\r
+ ASSERT (0xAA5555AA == *(UINT32 *) (&Buffer[sizeof (IA32_FX_BUFFER) - 4]));\r
+\r
+ InternalX86FxRestore (Buffer);\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 AsmFxSave()\r
+\r
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Save the current floating point/SSE/SSE2 context to a buffer.\r
+\r
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by\r
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only\r
+ available on IA-32 and x64.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+ If Buffer is not aligned on a 16-byte boundary, then ASSERT().\r
+\r
+ @param Buffer A pointer to a buffer to save the floating point/SSE/SSE2 context.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmFxSave (\r
+ OUT IA32_FX_BUFFER *Buffer\r
+ )\r
+{\r
+ ASSERT (Buffer != NULL);\r
+ ASSERT (0 == ((UINTN)Buffer & 0xf));\r
+\r
+ InternalX86FxSave (Buffer);\r
+\r
+ //\r
+ // Mark one flag at end of Buffer, it will be check by AsmFxRestor()\r
+ //\r
+ *(UINT32 *) (&Buffer[sizeof (IA32_FX_BUFFER) - 4]) = 0xAA5555AA;\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 GetInterruptState()\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+\r
+/**\r
+ Retrieves the current CPU interrupt state.\r
+\r
+ Returns TRUE is interrupts are currently enabled. Otherwise\r
+ returns FALSE.\r
+\r
+ @retval TRUE CPU interrupts are enabled.\r
+ @retval FALSE CPU interrupts are disabled.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+GetInterruptState (\r
+ VOID\r
+ )\r
+{\r
+ IA32_EFLAGS32 EFlags;\r
+\r
+ EFlags.UintN = AsmReadEflags ();\r
+ return (BOOLEAN)(1 == EFlags.Bits.IF);\r
+}\r
+\r
+\r
--- /dev/null
+/** @file\r
+ IA-32/x64 MemoryFence().\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+/**\r
+ Used to serialize load and store operations.\r
+\r
+ All loads and stores that proceed calls to this function are guaranteed to be\r
+ globally visible when this function returns.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+MemoryFence (\r
+ VOID\r
+ )\r
+{\r
+ return;\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 MSR functions.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+\r
+/**\r
+ Returns the lower 32-bits of a Machine Specific Register(MSR).\r
+\r
+ Reads and returns the lower 32-bits of the MSR specified by Index.\r
+ No parameter checking is performed on Index, and some Index values may cause\r
+ CPU exceptions. The caller must either guarantee that Index is valid, or the\r
+ caller must set up exception handlers to catch the exceptions. This function\r
+ is only available on IA-32 and x64.\r
+\r
+ @param Index The 32-bit MSR index to read.\r
+\r
+ @return The lower 32 bits of the MSR identified by Index.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmReadMsr32 (\r
+ IN UINT32 Index\r
+ )\r
+{\r
+ return (UINT32)AsmReadMsr64 (Index);\r
+}\r
+\r
+/**\r
+ Writes a 32-bit value to a Machine Specific Register(MSR), and returns the value.\r
+ The upper 32-bits of the MSR are set to zero.\r
+\r
+ Writes the 32-bit value specified by Value to the MSR specified by Index. The\r
+ upper 32-bits of the MSR write are set to zero. The 32-bit value written to\r
+ the MSR is returned. No parameter checking is performed on Index or Value,\r
+ and some of these may cause CPU exceptions. The caller must either guarantee\r
+ that Index and Value are valid, or the caller must establish proper exception\r
+ handlers. This function is only available on IA-32 and x64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param Value The 32-bit value to write to the MSR.\r
+\r
+ @return Value\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmWriteMsr32 (\r
+ IN UINT32 Index,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ return (UINT32)AsmWriteMsr64 (Index, Value);\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MSR, performs a bitwise OR on the lower 32-bits, and\r
+ writes the result back to the 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
+ between the lower 32-bits of the read result and the value specified by\r
+ OrData, and writes the result to the 64-bit MSR specified by Index. The lower\r
+ 32-bits of the value written to the MSR is returned. No parameter checking is\r
+ performed on Index or OrData, and some of these may cause CPU exceptions. The\r
+ caller must either guarantee that Index and OrData are valid, or the caller\r
+ must establish proper exception handlers. This function is only available on\r
+ IA-32 and x64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param OrData The value to OR with the read value from the MSR.\r
+\r
+ @return The lower 32-bit value written to the MSR.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmMsrOr32 (\r
+ IN UINT32 Index,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return (UINT32)AsmMsrOr64 (Index, OrData);\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MSR, performs a bitwise AND on the lower 32-bits, and writes\r
+ the result back to the 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r
+ lower 32-bits of the read result and the value specified by AndData, and\r
+ writes the result to the 64-bit MSR specified by Index. The lower 32-bits of\r
+ the value written to the MSR is returned. No parameter checking is performed\r
+ on Index or AndData, and some of these may cause CPU exceptions. The caller\r
+ must either guarantee that Index and AndData are valid, or the caller must\r
+ establish proper exception handlers. This function is only available on IA-32\r
+ and x64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param AndData The value to AND with the read value from the MSR.\r
+\r
+ @return The lower 32-bit value written to the MSR.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmMsrAnd32 (\r
+ IN UINT32 Index,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ return (UINT32)AsmMsrAnd64 (Index, AndData);\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise OR\r
+ on the lower 32-bits, and writes the result back to the 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r
+ lower 32-bits of the read result and the value specified by AndData\r
+ preserving the upper 32-bits, performs a bitwise OR between the\r
+ result of the AND operation and the value specified by OrData, and writes the\r
+ result to the 64-bit MSR specified by Address. The lower 32-bits of the value\r
+ written to the MSR is returned. No parameter checking is performed on Index,\r
+ AndData, or OrData, and some of these may cause CPU exceptions. The caller\r
+ must either guarantee that Index, AndData, and OrData are valid, or the\r
+ caller must establish proper exception handlers. This function is only\r
+ available on IA-32 and x64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param AndData The value to AND with the read value from the MSR.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The lower 32-bit value written to the MSR.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmMsrAndThenOr32 (\r
+ IN UINT32 Index,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return (UINT32)AsmMsrAndThenOr64 (Index, AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of an MSR.\r
+\r
+ Reads the bit field in the lower 32-bits of a 64-bit MSR. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned. The caller must either guarantee that Index is valid, or the caller\r
+ must set up exception handlers to catch the exceptions. This function is only\r
+ available on IA-32 and x64.\r
+\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Index The 32-bit MSR index to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+\r
+ @return The bit field read from the MSR.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmMsrBitFieldRead32 (\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return BitFieldRead32 (AsmReadMsr32 (Index), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to an MSR.\r
+\r
+ Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination MSR are preserved. The lower 32-bits of the MSR written is\r
+ returned. The caller must either guarantee that Index and the data written \r
+ is valid, or the caller must set up exception handlers to catch the exceptions. \r
+ This function is only available on IA-32 and x64.\r
+\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The lower 32-bit of the value written to the MSR.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmMsrBitFieldWrite32 (\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT (EndBit < sizeof (Value) * 8);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT32)AsmMsrBitFieldWrite64 (Index, StartBit, EndBit, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the\r
+ result back to the bit field in the 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 64-bit MSR specified by Index. The lower 32-bits of the value\r
+ written to the MSR are returned. Extra left bits in OrData are stripped. The\r
+ caller must either guarantee that Index and the data written is valid, or\r
+ the caller must set up exception handlers to catch the exceptions. This\r
+ function is only available on IA-32 and x64.\r
+\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param OrData The value to OR with the read value from the MSR.\r
+\r
+ @return The lower 32-bit of the value written to the MSR.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmMsrBitFieldOr32 (\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ ASSERT (EndBit < sizeof (OrData) * 8);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT32)AsmMsrBitFieldOr64 (Index, StartBit, EndBit, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the\r
+ result back to the bit field in the 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r
+ read result and the value specified by AndData, and writes the result to the\r
+ 64-bit MSR specified by Index. The lower 32-bits of the value written to the\r
+ MSR are returned. Extra left bits in AndData are stripped. The caller must\r
+ either guarantee that Index and the data written is valid, or the caller must\r
+ set up exception handlers to catch the exceptions. This function is only\r
+ available on IA-32 and x64.\r
+\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the read value from the MSR.\r
+\r
+ @return The lower 32-bit of the value written to the MSR.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmMsrBitFieldAnd32 (\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ ASSERT (EndBit < sizeof (AndData) * 8);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT32)AsmMsrBitFieldAnd64 (Index, StartBit, EndBit, AndData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by a\r
+ bitwise OR between the read result and the value specified by\r
+ AndData, and writes the result to the 64-bit MSR specified by Index. The\r
+ lower 32-bits of the value written to the MSR are returned. Extra left bits\r
+ in both AndData and OrData are stripped. The caller must either guarantee\r
+ that Index and the data written is valid, or the caller must set up exception\r
+ handlers to catch the exceptions. This function is only available on IA-32\r
+ and x64.\r
+\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the read value from the MSR.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The lower 32-bit of the value written to the MSR.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+AsmMsrBitFieldAndThenOr32 (\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ ASSERT (EndBit < sizeof (AndData) * 8);\r
+ ASSERT (StartBit <= EndBit);\r
+ return (UINT32)AsmMsrBitFieldAndThenOr64 (\r
+ Index,\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MSR, performs a bitwise OR, and writes the result\r
+ back to the 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 64-bit MSR specified by Index. The value written to the MSR is\r
+ returned. No parameter checking is performed on Index or OrData, and some of\r
+ these may cause CPU exceptions. The caller must either guarantee that Index\r
+ and OrData are valid, or the caller must establish proper exception handlers.\r
+ This function is only available on IA-32 and x64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param OrData The value to OR with the read value from the MSR.\r
+\r
+ @return The value written back to the MSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmMsrOr64 (\r
+ IN UINT32 Index,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return AsmWriteMsr64 (Index, AsmReadMsr64 (Index) | OrData);\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MSR, performs a bitwise AND, and writes the result back to the\r
+ 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r
+ read result and the value specified by OrData, and writes the result to the\r
+ 64-bit MSR specified by Index. The value written to the MSR is returned. No\r
+ parameter checking is performed on Index or OrData, and some of these may\r
+ cause CPU exceptions. The caller must either guarantee that Index and OrData\r
+ are valid, or the caller must establish proper exception handlers. This\r
+ function is only available on IA-32 and x64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param AndData The value to AND with the read value from the MSR.\r
+\r
+ @return The value written back to the MSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmMsrAnd64 (\r
+ IN UINT32 Index,\r
+ IN UINT64 AndData\r
+ )\r
+{\r
+ return AsmWriteMsr64 (Index, AsmReadMsr64 (Index) & AndData);\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise \r
+ OR, and writes the result back to the 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between read\r
+ result and the value specified by AndData, performs a bitwise OR\r
+ between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 64-bit MSR specified by Index. The value written\r
+ to the MSR is returned. No parameter checking is performed on Index, AndData,\r
+ or OrData, and some of these may cause CPU exceptions. The caller must either\r
+ guarantee that Index, AndData, and OrData are valid, or the caller must\r
+ establish proper exception handlers. This function is only available on IA-32\r
+ and x64.\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param AndData The value to AND with the read value from the MSR.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the MSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmMsrAndThenOr64 (\r
+ IN UINT32 Index,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return AsmWriteMsr64 (Index, (AsmReadMsr64 (Index) & AndData) | OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of an MSR.\r
+\r
+ Reads the bit field in the 64-bit MSR. The bit field is specified by the\r
+ StartBit and the EndBit. The value of the bit field is returned. The caller\r
+ must either guarantee that Index is valid, or the caller must set up\r
+ exception handlers to catch the exceptions. This function is only available\r
+ on IA-32 and x64.\r
+\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Index The 32-bit MSR index to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+\r
+ @return The value read from the MSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmMsrBitFieldRead64 (\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return BitFieldRead64 (AsmReadMsr64 (Index), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to an MSR.\r
+\r
+ Writes Value to a bit field in a 64-bit MSR. The bit field is specified by\r
+ the StartBit and the EndBit. All other bits in the destination MSR are\r
+ preserved. The MSR written is returned. The caller must either guarantee \r
+ that Index and the data written is valid, or the caller must set up exception \r
+ handlers to catch the exceptions. This function is only available on IA-32 and x64.\r
+\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param Value The new value of the bit field.\r
+\r
+ @return The value written back to the MSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmMsrBitFieldWrite64 (\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ return AsmWriteMsr64 (\r
+ Index,\r
+ BitFieldWrite64 (AsmReadMsr64 (Index), StartBit, EndBit, Value)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit MSR, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 64-bit MSR specified by Index. The value written to the MSR is\r
+ returned. Extra left bits in OrData are stripped. The caller must either\r
+ guarantee that Index and the data written is valid, or the caller must set up\r
+ exception handlers to catch the exceptions. This function is only available\r
+ on IA-32 and x64.\r
+\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param OrData The value to OR with the read value from the bit field.\r
+\r
+ @return The value written back to the MSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmMsrBitFieldOr64 (\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return AsmWriteMsr64 (\r
+ Index,\r
+ BitFieldOr64 (AsmReadMsr64 (Index), StartBit, EndBit, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the\r
+ result back to the bit field in the 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r
+ read result and the value specified by AndData, and writes the result to the\r
+ 64-bit MSR specified by Index. The value written to the MSR is returned.\r
+ Extra left bits in AndData are stripped. The caller must either guarantee\r
+ that Index and the data written is valid, or the caller must set up exception\r
+ handlers to catch the exceptions. This function is only available on IA-32\r
+ and x64.\r
+\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param AndData The value to AND with the read value from the bit field.\r
+\r
+ @return The value written back to the MSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmMsrBitFieldAnd64 (\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
+ )\r
+{\r
+ return AsmWriteMsr64 (\r
+ Index,\r
+ BitFieldAnd64 (AsmReadMsr64 (Index), StartBit, EndBit, AndData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 64-bit MSR.\r
+\r
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by\r
+ a bitwise OR between the read result and the value specified by\r
+ AndData, and writes the result to the 64-bit MSR specified by Index. The\r
+ value written to the MSR is returned. Extra left bits in both AndData and\r
+ OrData are stripped. The caller must either guarantee that Index and the data\r
+ written is valid, or the caller must set up exception handlers to catch the\r
+ exceptions. This function is only available on IA-32 and x64.\r
+\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Index The 32-bit MSR index to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param AndData The value to AND with the read value from the bit field.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the MSR.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+AsmMsrBitFieldAndThenOr64 (\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return AsmWriteMsr64 (\r
+ Index,\r
+ BitFieldAndThenOr64 (\r
+ AsmReadMsr64 (Index),\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ )\r
+ );\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 AsmReadGdtr()\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
+\r
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r
+ function is only available on IA-32 and x64.\r
+\r
+ If Gdtr is NULL, then ASSERT().\r
+\r
+ @param Gdtr The pointer to a GDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmReadGdtr (\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
+ )\r
+{\r
+ ASSERT (Gdtr != NULL);\r
+ InternalX86ReadGdtr (Gdtr);\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 AsmReadIdtr()\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.\r
+\r
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This\r
+ function is only available on IA-32 and x64.\r
+\r
+ If Idtr is NULL, then ASSERT().\r
+\r
+ @param Idtr The pointer to a IDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmReadIdtr (\r
+ OUT IA32_DESCRIPTOR *Idtr\r
+ )\r
+{\r
+ ASSERT (Idtr != NULL);\r
+ InternalX86ReadIdtr (Idtr);\r
+}\r
--- /dev/null
+/** @file\r
+ Real Mode Thunk Functions for IA32 and x64.\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+\r
+//\r
+// Byte packed structure for a segment descriptor in a GDT/LDT\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 LimitLow:16;\r
+ UINT32 BaseLow:16;\r
+ UINT32 BaseMid:8;\r
+ UINT32 Type:4;\r
+ UINT32 S:1;\r
+ UINT32 DPL:2;\r
+ UINT32 P:1;\r
+ UINT32 LimitHigh:4;\r
+ UINT32 AVL:1;\r
+ UINT32 L:1;\r
+ UINT32 DB:1;\r
+ UINT32 G:1;\r
+ UINT32 BaseHigh:8;\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} IA32_SEGMENT_DESCRIPTOR;\r
+\r
+extern CONST UINT8 m16Start;\r
+extern CONST UINT16 m16Size;\r
+extern CONST UINT16 mThunk16Attr;\r
+extern CONST UINT16 m16Gdt;\r
+extern CONST UINT16 m16GdtrBase;\r
+extern CONST UINT16 mTransition;\r
+\r
+/**\r
+ Invokes 16-bit code in big real mode and returns the updated register set.\r
+\r
+ This function transfers control to the 16-bit code specified by CS:EIP using\r
+ the stack specified by SS:ESP in RegisterSet. The updated registers are saved\r
+ on the real mode stack and the starting address of the save area is returned.\r
+\r
+ @param RegisterSet Values of registers before invocation of 16-bit code.\r
+ @param Transition The pointer to the transition code under 1MB.\r
+\r
+ @return The pointer to a IA32_REGISTER_SET structure containing the updated\r
+ register values.\r
+\r
+**/\r
+IA32_REGISTER_SET *\r
+EFIAPI\r
+InternalAsmThunk16 (\r
+ IN IA32_REGISTER_SET *RegisterSet,\r
+ IN OUT VOID *Transition\r
+ );\r
+\r
+/**\r
+ Retrieves the properties for 16-bit thunk functions.\r
+\r
+ Computes the size of the buffer and stack below 1MB required to use the\r
+ AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This\r
+ buffer size is returned in RealModeBufferSize, and the stack size is returned\r
+ in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\r
+ then the actual minimum stack size is ExtraStackSize plus the maximum number\r
+ of bytes that need to be passed to the 16-bit real mode code.\r
+\r
+ If RealModeBufferSize is NULL, then ASSERT().\r
+ If ExtraStackSize is NULL, then ASSERT().\r
+\r
+ @param RealModeBufferSize A pointer to the size of the buffer below 1MB\r
+ required to use the 16-bit thunk functions.\r
+ @param ExtraStackSize A pointer to the extra size of stack below 1MB\r
+ that the 16-bit thunk functions require for\r
+ temporary storage in the transition to and from\r
+ 16-bit real mode.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmGetThunk16Properties (\r
+ OUT UINT32 *RealModeBufferSize,\r
+ OUT UINT32 *ExtraStackSize\r
+ )\r
+{\r
+ ASSERT (RealModeBufferSize != NULL);\r
+ ASSERT (ExtraStackSize != NULL);\r
+\r
+ *RealModeBufferSize = m16Size;\r
+\r
+ //\r
+ // Extra 4 bytes for return address, and another 4 bytes for mode transition\r
+ //\r
+ *ExtraStackSize = sizeof (IA32_DWORD_REGS) + 8;\r
+}\r
+\r
+/**\r
+ Prepares all structures a code required to use AsmThunk16().\r
+\r
+ Prepares all structures and code required to use AsmThunk16().\r
+ \r
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r
+\r
+ If ThunkContext is NULL, then ASSERT().\r
+\r
+ @param ThunkContext A pointer to the context structure that describes the\r
+ 16-bit real mode code to call.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmPrepareThunk16 (\r
+ OUT THUNK_CONTEXT *ThunkContext\r
+ )\r
+{\r
+ IA32_SEGMENT_DESCRIPTOR *RealModeGdt;\r
+\r
+ ASSERT (ThunkContext != NULL);\r
+ ASSERT ((UINTN)ThunkContext->RealModeBuffer < 0x100000);\r
+ ASSERT (ThunkContext->RealModeBufferSize >= m16Size);\r
+ ASSERT ((UINTN)ThunkContext->RealModeBuffer + m16Size <= 0x100000);\r
+\r
+ CopyMem (ThunkContext->RealModeBuffer, &m16Start, m16Size);\r
+\r
+ //\r
+ // Point RealModeGdt to the GDT to be used in transition\r
+ //\r
+ // RealModeGdt[0]: Reserved as NULL descriptor\r
+ // RealModeGdt[1]: Code Segment\r
+ // RealModeGdt[2]: Data Segment\r
+ // RealModeGdt[3]: Call Gate\r
+ //\r
+ RealModeGdt = (IA32_SEGMENT_DESCRIPTOR*)(\r
+ (UINTN)ThunkContext->RealModeBuffer + m16Gdt);\r
+\r
+ //\r
+ // Update Code & Data Segment Descriptor\r
+ //\r
+ RealModeGdt[1].Bits.BaseLow =\r
+ (UINT32)(UINTN)ThunkContext->RealModeBuffer & ~0xf;\r
+ RealModeGdt[1].Bits.BaseMid =\r
+ (UINT32)(UINTN)ThunkContext->RealModeBuffer >> 16;\r
+\r
+ //\r
+ // Update transition code entry point offset\r
+ //\r
+ *(UINT32*)((UINTN)ThunkContext->RealModeBuffer + mTransition) +=\r
+ (UINT32)(UINTN)ThunkContext->RealModeBuffer & 0xf;\r
+\r
+ //\r
+ // Update Segment Limits for both Code and Data Segment Descriptors\r
+ //\r
+ if ((ThunkContext->ThunkAttributes & THUNK_ATTRIBUTE_BIG_REAL_MODE) == 0) {\r
+ //\r
+ // Set segment limits to 64KB\r
+ //\r
+ RealModeGdt[1].Bits.LimitHigh = 0;\r
+ RealModeGdt[1].Bits.G = 0;\r
+ RealModeGdt[2].Bits.LimitHigh = 0;\r
+ RealModeGdt[2].Bits.G = 0;\r
+ }\r
+\r
+ //\r
+ // Update GDTBASE for this thunk context\r
+ //\r
+ *(VOID**)((UINTN)ThunkContext->RealModeBuffer + m16GdtrBase) = RealModeGdt;\r
+\r
+ //\r
+ // Update Thunk Attributes\r
+ //\r
+ *(UINT32*)((UINTN)ThunkContext->RealModeBuffer + mThunk16Attr) =\r
+ ThunkContext->ThunkAttributes;\r
+}\r
+\r
+/**\r
+ Transfers control to a 16-bit real mode entry point and returns the results.\r
+\r
+ Transfers control to a 16-bit real mode entry point and returns the results.\r
+ AsmPrepareThunk16() must be called with ThunkContext before this function is used.\r
+ This function must be called with interrupts disabled.\r
+\r
+ The register state from the RealModeState field of ThunkContext is restored just prior \r
+ to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState, \r
+ which is used to set the interrupt state when a 16-bit real mode entry point is called.\r
+ Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.\r
+ The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to \r
+ the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function. \r
+ The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,\r
+ so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment \r
+ and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry \r
+ point must exit with a RETF instruction. The register state is captured into RealModeState immediately \r
+ after the RETF instruction is executed.\r
+ \r
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, \r
+ or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure \r
+ the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode. \r
+ \r
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, \r
+ then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode. \r
+ This includes the base vectors, the interrupt masks, and the edge/level trigger mode.\r
+ \r
+ If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code \r
+ is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.\r
+ \r
+ If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in \r
+ ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to \r
+ disable the A20 mask.\r
+ \r
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in \r
+ ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails, \r
+ then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r
+ \r
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in \r
+ ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r
+ \r
+ If ThunkContext is NULL, then ASSERT().\r
+ If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().\r
+ If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in \r
+ ThunkAttributes, then ASSERT().\r
+\r
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r
+ \r
+ @param ThunkContext A pointer to the context structure that describes the\r
+ 16-bit real mode code to call.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmThunk16 (\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
+ )\r
+{\r
+ IA32_REGISTER_SET *UpdatedRegs;\r
+\r
+ ASSERT (ThunkContext != NULL);\r
+ ASSERT ((UINTN)ThunkContext->RealModeBuffer < 0x100000);\r
+ ASSERT (ThunkContext->RealModeBufferSize >= m16Size);\r
+ ASSERT ((UINTN)ThunkContext->RealModeBuffer + m16Size <= 0x100000);\r
+ ASSERT (((ThunkContext->ThunkAttributes & (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)) != \\r
+ (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)));\r
+ \r
+ UpdatedRegs = InternalAsmThunk16 (\r
+ ThunkContext->RealModeState,\r
+ ThunkContext->RealModeBuffer\r
+ );\r
+\r
+ CopyMem (ThunkContext->RealModeState, UpdatedRegs, sizeof (*UpdatedRegs));\r
+}\r
+\r
+/**\r
+ Prepares all structures and code for a 16-bit real mode thunk, transfers\r
+ control to a 16-bit real mode entry point, and returns the results.\r
+\r
+ Prepares all structures and code for a 16-bit real mode thunk, transfers\r
+ control to a 16-bit real mode entry point, and returns the results. If the\r
+ caller only need to perform a single 16-bit real mode thunk, then this\r
+ service should be used. If the caller intends to make more than one 16-bit\r
+ real mode thunk, then it is more efficient if AsmPrepareThunk16() is called\r
+ once and AsmThunk16() can be called for each 16-bit real mode thunk.\r
+\r
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r
+ \r
+ See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.\r
+\r
+ @param ThunkContext A pointer to the context structure that describes the\r
+ 16-bit real mode code to call.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmPrepareAndThunk16 (\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
+ )\r
+{\r
+ AsmPrepareThunk16 (ThunkContext);\r
+ AsmThunk16 (ThunkContext);\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 AsmWriteGdtr()\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
+\r
+ Writes and the current GDTR descriptor specified by Gdtr. This function is\r
+ only available on IA-32 and x64.\r
+\r
+ If Gdtr is NULL, then ASSERT().\r
+\r
+ @param Gdtr The pointer to a GDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteGdtr (\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
+ )\r
+{\r
+ ASSERT (Gdtr != NULL);\r
+ InternalX86WriteGdtr (Gdtr);\r
+}\r
--- /dev/null
+/** @file\r
+ IA-32/x64 AsmWriteIdtr()\r
+\r
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+ Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.\r
+\r
+ Writes the current IDTR descriptor and returns it in Idtr. This function is\r
+ only available on IA-32 and x64.\r
+\r
+ If Idtr is NULL, then ASSERT().\r
+\r
+ @param Idtr The pointer to a IDTR descriptor.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteIdtr (\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
+ )\r
+{\r
+ ASSERT (Idtr != NULL);\r
+ InternalX86WriteIdtr (Idtr);\r
+}\r
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