//\r
#define INTEL_Q35_MCH_DEVICE_ID 0x29C0\r
\r
+//\r
+// B/D/F/Type: 0/0/0/PCI\r
+//\r
+#define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
+\r
+#define MCH_GGC 0x52\r
+#define MCH_GGC_IVD BIT1\r
+\r
+#define MCH_SMRAM 0x9D\r
+#define MCH_SMRAM_D_LCK BIT4\r
+#define MCH_SMRAM_G_SMRAME BIT3\r
+\r
+#define MCH_ESMRAMC 0x9E\r
+#define MCH_ESMRAMC_H_SMRAME BIT7\r
+#define MCH_ESMRAMC_E_SMERR BIT6\r
+#define MCH_ESMRAMC_SM_CACHE BIT5\r
+#define MCH_ESMRAMC_SM_L1 BIT4\r
+#define MCH_ESMRAMC_SM_L2 BIT3\r
+#define MCH_ESMRAMC_TSEG_8MB BIT2\r
+#define MCH_ESMRAMC_TSEG_2MB BIT1\r
+#define MCH_ESMRAMC_TSEG_1MB 0\r
+#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)\r
+#define MCH_ESMRAMC_T_EN BIT0\r
+\r
+#define MCH_GBSM 0xA4\r
+#define MCH_GBSM_MB_SHIFT 20\r
+\r
+#define MCH_BGSM 0xA8\r
+#define MCH_BGSM_MB_SHIFT 20\r
+\r
+#define MCH_TSEGMB 0xAC\r
+#define MCH_TSEGMB_MB_SHIFT 20\r
+\r
+#define MCH_TOLUD 0xB0\r
+#define MCH_TOLUD_MB_SHIFT 4\r
+\r
//\r
// B/D/F/Type: 0/0x1f/0/PCI\r
//\r
#define POWER_MGMT_REGISTER_Q35(Offset) \\r
PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))\r
\r
+#define ICH9_PMBASE 0x40\r
+#define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \\r
+ BIT10 | BIT9 | BIT8 | BIT7)\r
+\r
+#define ICH9_ACPI_CNTL 0x44\r
+#define ICH9_ACPI_CNTL_ACPI_EN BIT7\r
+\r
+#define ICH9_GEN_PMCON_1 0xA0\r
+#define ICH9_GEN_PMCON_1_SMI_LOCK BIT4\r
+\r
+//\r
+// IO ports\r
+//\r
+#define ICH9_APM_CNT 0xB2\r
+#define ICH9_APM_STS 0xB3\r
+\r
+//\r
+// IO ports relative to PMBASE\r
+//\r
+#define ICH9_PMBASE_OFS_SMI_EN 0x30\r
+#define ICH9_SMI_EN_APMC_EN BIT5\r
+#define ICH9_SMI_EN_GBL_SMI_EN BIT0\r
+\r
#endif\r