REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1366
Commit
b3c71b472dff2c02f0cc38d7a1959cfb2ba8420d supported MSR setting
in different scopes. It added below macro:
CPU_FEATURE_THREAD_BEFORE
CPU_FEATURE_THREAD_AFTER
CPU_FEATURE_CORE_BEFORE
CPU_FEATURE_CORE_AFTER
CPU_FEATURE_PACKAGE_BEFORE
CPU_FEATURE_PACKAGE_AFTER
And it re-interpreted CPU_FEATURE_BEFORE as CPU_FEATURE_THREAD_BEFORE
and CPU_FEATURE_AFTER as CPU_FEATURE_THREAD_AFTER.
This patch retires CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER
completely.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
/** @file\r
Register CPU Features Library to register and manage CPU features.\r
\r
- Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#define CPU_FEATURE_BEFORE_ALL BIT23\r
#define CPU_FEATURE_AFTER_ALL BIT24\r
-//\r
-// CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER only mean Thread scope\r
-// before and Thread scope after.\r
-// It will be replace with CPU_FEATURE_THREAD_BEFORE and\r
-// CPU_FEATURE_THREAD_AFTER, and should not be used anymore.\r
-//\r
-#define CPU_FEATURE_BEFORE BIT25\r
-#define CPU_FEATURE_AFTER BIT26\r
-\r
-#define CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_BEFORE\r
-#define CPU_FEATURE_THREAD_AFTER CPU_FEATURE_AFTER\r
+#define CPU_FEATURE_THREAD_BEFORE BIT25\r
+#define CPU_FEATURE_THREAD_AFTER BIT26\r
#define CPU_FEATURE_CORE_BEFORE BIT27\r
#define CPU_FEATURE_CORE_AFTER BIT28\r
#define CPU_FEATURE_PACKAGE_BEFORE BIT29\r
This library registers CPU features defined in Intel(R) 64 and IA-32\r
Architectures Software Developer's Manual.\r
\r
- Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
SmxSupport,\r
SmxInitialize,\r
CPU_FEATURE_SMX,\r
- CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEFORE,\r
+ CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_THREAD_BEFORE,\r
CPU_FEATURE_END\r
);\r
ASSERT_EFI_ERROR (Status);\r
VmxSupport,\r
VmxInitialize,\r
CPU_FEATURE_VMX,\r
- CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEFORE,\r
+ CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_THREAD_BEFORE,\r
CPU_FEATURE_END\r
);\r
ASSERT_EFI_ERROR (Status);\r
LmceSupport,\r
LmceInitialize,\r
CPU_FEATURE_LMCE,\r
- CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEFORE,\r
+ CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_THREAD_BEFORE,\r
CPU_FEATURE_END\r
);\r
ASSERT_EFI_ERROR (Status);\r
/** @file\r
CPU Register Table Library functions.\r
\r
- Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
!= (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER));\r
ASSERT ((Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER))\r
!= (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER));\r
- if (Feature < CPU_FEATURE_BEFORE) {\r
+ if (Feature < CPU_FEATURE_THREAD_BEFORE) {\r
BeforeAll = ((Feature & CPU_FEATURE_BEFORE_ALL) != 0) ? TRUE : FALSE;\r
AfterAll = ((Feature & CPU_FEATURE_AFTER_ALL) != 0) ? TRUE : FALSE;\r
Feature &= ~(CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL);\r
ASSERT (FeatureMask == NULL);\r
SetCpuFeaturesBitMask (&FeatureMask, Feature, CpuFeaturesData->BitMaskSize);\r
- } else if ((Feature & CPU_FEATURE_BEFORE) != 0) {\r
- SetCpuFeaturesBitMask (&BeforeFeatureBitMask, Feature & ~CPU_FEATURE_BEFORE, CpuFeaturesData->BitMaskSize);\r
- } else if ((Feature & CPU_FEATURE_AFTER) != 0) {\r
- SetCpuFeaturesBitMask (&AfterFeatureBitMask, Feature & ~CPU_FEATURE_AFTER, CpuFeaturesData->BitMaskSize);\r
+ } else if ((Feature & CPU_FEATURE_THREAD_BEFORE) != 0) {\r
+ SetCpuFeaturesBitMask (&BeforeFeatureBitMask, Feature & ~CPU_FEATURE_THREAD_BEFORE, CpuFeaturesData->BitMaskSize);\r
+ } else if ((Feature & CPU_FEATURE_THREAD_AFTER) != 0) {\r
+ SetCpuFeaturesBitMask (&AfterFeatureBitMask, Feature & ~CPU_FEATURE_THREAD_AFTER, CpuFeaturesData->BitMaskSize);\r
} else if ((Feature & CPU_FEATURE_CORE_BEFORE) != 0) {\r
SetCpuFeaturesBitMask (&CoreBeforeFeatureBitMask, Feature & ~CPU_FEATURE_CORE_BEFORE, CpuFeaturesData->BitMaskSize);\r
} else if ((Feature & CPU_FEATURE_CORE_AFTER) != 0) {\r