ArmPkg/ArmMmuLib AARCH64: invalidate page tables before populating them

As it turns out, ARMv8 also permits accesses made with the MMU and
caches off to hit in the caches, so to ensure that any modifications
we make before enabling the MMU are visible afterwards as well, we
should invalidate page tables right after allocation like we do now on
ARM, if the MMU is still disabled at that point.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Message-Id: <20200307083849.8940-3-ard.biesheuvel@linaro.org>

diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index 00a38bc31d0af2e0d1a0f7c17c25be5157e1a503..221175ca65357de0d6789becd472afbbe742ab19 100644 (file)
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -204,6 +204,14 @@ UpdateRegionMappingRecursive (
           return EFI_OUT_OF_RESOURCES;\r
         }\r
 \r
+        if (!ArmMmuEnabled ()) {\r
+          //\r
+          // Make sure we are not inadvertently hitting in the caches\r
+          // when populating the page tables.\r
+          //\r
+          InvalidateDataCacheRange (TranslationTable, EFI_PAGE_SIZE);\r
+        }\r
+\r
         if ((*Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) {\r
           //\r
           // We are splitting an existing block entry, so we have to populate\r
@@ -602,6 +610,12 @@ ArmConfigureMmu (
     *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);\r
   }\r
 \r
+  //\r
+  // Make sure we are not inadvertently hitting in the caches\r
+  // when populating the page tables.\r
+  //\r
+  InvalidateDataCacheRange (TranslationTable,\r
+    RootTableEntryCount * sizeof(UINT64));\r
   ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));\r
 \r
   TranslationTableAttribute = TT_ATTR_INDX_INVALID;\r