Commit
7b8fe63561b4 ("OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG
/ ECAM) on Q35", 2016-03-10) claimed that,
On Q35 machine types that QEMU intends to support in the long term, QEMU
never lets the RAM below 4 GB exceed 2 GB.
Alas, this statement came from a misunderstanding that occurred while we
worked out the interface contract. In fact QEMU does allow the 32-bit RAM
extend up to 0xB000_0000 (exclusive), in case the RAM size falls in the
range (0x8000_0000, 0xB000_0000) (i.e., the RAM size is greater than
2048MB and smaller than 2816MB).
In turn, such a RAM size (justifiedly) triggers
ASSERT (TopOfLowRam <= PciExBarBase);
in MemMapInitialization(), because we placed the 256MB PCIEXBAR at
0x8000_0000 (2GB) exactly, relying on the interface contract. (And, the
32-bit PCI window would follow the PCIEXBAR, covering the [0x9000_0000,
0xFC00_0000) range.)
In order to fix this, reorder the 32-bit PCI window against the PCIEXBAR,
as follows:
- start the 32-bit PCI window where it starts on i440fx as well, that is,
at 2GB or TopOfLowRam, whichever is higher;
- unlike on i440fx, where the 32-bit PCI window extends up to 0xFC00_0000,
stop it at 0xE000_0000 on q35,
- place the PCIEXBAR at 0xE000_0000.
(We cannot place the PCIEXBAR at 0xF000_0000 because the 256MB MMIO area
that starts there is not entirely free.)
Before this patch, the 32-bit PCI window used to only *end* at the same
spot (namely, 0xFC00_0000) between i440fx and q35; now it will only
*start* at the same spot (namely, 2GB or TopOfLowRam, whichever is higher)
between both boards.
On q35, the maximal window shrinks from
0xFC00_0000 - 0x9000_0000 = 0x6C00_0000 == 1728 MB
to
0xE000_0000 - 0x8000_0000 == 1536 MB.
We lose 192 MB of the aperture; however, the aperture is now aligned at
1GB, rather than 256 MB, and so it could fit a 1GB BAR even.
Regarding the minimal window (triggered by RAM size 2815MB), its size is
0xE000_0000 - 0xAFF0_0000 = 769 MB
which is not great, but probably better than a failed ASSERT.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1814
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=
1666941
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=
1701710
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
# This PCD is used to set the base address of the PCI express hierarchy. It\r
# is only consulted when OVMF runs on Q35. In that case it is programmed into\r
# the PCIEXBAR register.\r
- #\r
- # On Q35 machine types that QEMU intends to support in the long term, QEMU\r
- # never lets the RAM below 4 GB exceed 2 GB.\r
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000\r
\r
!ifdef $(SOURCE_DEBUG_ENABLE)\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r
# This PCD is used to set the base address of the PCI express hierarchy. It\r
# is only consulted when OVMF runs on Q35. In that case it is programmed into\r
# the PCIEXBAR register.\r
- #\r
- # On Q35 machine types that QEMU intends to support in the long term, QEMU\r
- # never lets the RAM below 4 GB exceed 2 GB.\r
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000\r
\r
!ifdef $(SOURCE_DEBUG_ENABLE)\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r
# This PCD is used to set the base address of the PCI express hierarchy. It\r
# is only consulted when OVMF runs on Q35. In that case it is programmed into\r
# the PCIEXBAR register.\r
- #\r
- # On Q35 machine types that QEMU intends to support in the long term, QEMU\r
- # never lets the RAM below 4 GB exceed 2 GB.\r
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000\r
\r
!ifdef $(SOURCE_DEBUG_ENABLE)\r
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r
PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
- // The MMCONFIG area is expected to fall between the top of low RAM and\r
- // the base of the 32-bit PCI host aperture.\r
+ // The 32-bit PCI host aperture is expected to fall between the top of\r
+ // low RAM and the base of the MMCONFIG area.\r
//\r
PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
- ASSERT (TopOfLowRam <= PciExBarBase);\r
+ ASSERT (PciBase < PciExBarBase);\r
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
- PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
- PciSize = 0xFC000000 - PciBase;\r
+ PciSize = (UINT32)(PciExBarBase - PciBase);\r
} else {\r
PciSize = 0xFC000000 - PciBase;\r
}\r