powerpc/pseries/npu: Enable platform support

BugLink: https://bugs.launchpad.net/bugs/1819989
We already changed NPU API for GPUs to not to call OPAL and the remaining
bit is initializing NPU structures.

This searches for POWER9 NVLinks attached to any device on a PHB and
initializes an NPU structure if any found.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
(backported from commit 3be2df00e299821ad255498ac4411906a8d59cfa)
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.ibm.com>
Acked-by: Kamal Mostafa <kamal@canonical.com>
Acked-by: Kleber Souza <kleber.souza@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c
index 09eba5a9929afc6818dac60bac41079c89f6330b..6a0e1dcd4e79a6addae80eee8e916fbb56005440 100644 (file)
--- a/arch/powerpc/platforms/pseries/pci.c
+++ b/arch/powerpc/platforms/pseries/pci.c
@@ -29,6 +29,7 @@
 #include <asm/pci-bridge.h>
 #include <asm/prom.h>
 #include <asm/ppc-pci.h>
+#include <asm/pci.h>
 #include "pseries.h"
 
 #if 0
@@ -73,9 +74,31 @@ static void __init pSeries_request_regions(void)
 
 void __init pSeries_final_fixup(void)
 {
+       struct pci_controller *hose;
+
        pSeries_request_regions();
 
        eeh_addr_cache_build();
+
+       list_for_each_entry(hose, &hose_list, list_node) {
+               struct device_node *dn = hose->dn, *nvdn;
+
+               while (1) {
+                       dn = of_find_all_nodes(dn);
+                       if (!dn)
+                               break;
+                       nvdn = of_parse_phandle(dn, "ibm,nvlink", 0);
+                       if (!nvdn)
+                               continue;
+                       if (!of_device_is_compatible(nvdn, "ibm,npu-link"))
+                               continue;
+                       if (!of_device_is_compatible(nvdn->parent,
+                                               "ibm,power9-npu"))
+                               continue;
+                       WARN_ON_ONCE(pnv_npu2_init(hose));
+                       break;
+               }
+       }
 }
 
 /*