ArmPkg: Expand AArch64 address width to 48 bits

The VA address space has a maximum address width of 48 bits in
AArch64 state; 48 bits address width limit will provide better
compatibility than 40 bits for future CPU.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17526 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
index 77a96ec637310c0d8de6e5a908141074f9fb38f4..2398ba2539c79ac74eb2b255683059b5fb2b4bfe 100644 (file)
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -51,8 +51,8 @@
 #define TT_ALIGNMENT_BLOCK_ENTRY                BIT12\r
 #define TT_ALIGNMENT_DESCRIPTION_TABLE          BIT12\r
 \r
-#define TT_ADDRESS_MASK_BLOCK_ENTRY             (0xFFFFFFFULL << 12)\r
-#define TT_ADDRESS_MASK_DESCRIPTION_TABLE       (0xFFFFFFFULL << 12)\r
+#define TT_ADDRESS_MASK_BLOCK_ENTRY             (0xFFFFFFFFFULL << 12)\r
+#define TT_ADDRESS_MASK_DESCRIPTION_TABLE       (0xFFFFFFFFFULL << 12)\r
 \r
 #define TT_TYPE_MASK                            0x3\r
 #define TT_TYPE_TABLE_ENTRY                     0x3\r