UefiCpuPkg/PiSmmCpuDxeSmm: Add a new mIsShadowStack flag

This patch is code refactoring and doesn't change any functionality.
Add a new mIsShadowStack flag to identify whether current memory is
shadow stack. Previous smm code logic regards a RO range as shadow
stack and set the dirty bit in corresponding page table entry if
mInternalCr3 is not 0, which may be confusing.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index 1f7cc15727cd1e93ec2a3c547cc77392ef175c10..10de8dd8e4d083004082daaf8b4bd91a58c7be37 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -32,7 +32,8 @@ PAGE_ATTRIBUTE_TABLE  mPageAttributeTable[] = {
   { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 },\r
 };\r
 \r
-UINTN  mInternalCr3;\r
+UINTN    mInternalCr3;\r
+BOOLEAN  mIsShadowStack = FALSE;\r
 \r
 /**\r
   Set the internal page table base address.\r
@@ -249,7 +250,7 @@ ConvertPageEntryAttribute (
   if ((Attributes & EFI_MEMORY_RO) != 0) {\r
     if (IsSet) {\r
       NewPageEntry &= ~(UINT64)IA32_PG_RW;\r
-      if (mInternalCr3 != 0) {\r
+      if (mIsShadowStack) {\r
         // Environment setup\r
         // ReadOnly page need set Dirty bit for shadow stack\r
         NewPageEntry |= IA32_PG_D;\r
@@ -734,10 +735,11 @@ SetShadowStack (
   EFI_STATUS  Status;\r
 \r
   SetPageTableBase (Cr3);\r
-\r
-  Status = SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);\r
+  mIsShadowStack = TRUE;\r
+  Status         = SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);\r
 \r
   SetPageTableBase (0);\r
+  mIsShadowStack = FALSE;\r
 \r
   return Status;\r
 }\r