Update for ICC 10

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3749 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index a54abc0772486dd96e5ded0d58b06b9f41ee7604..5e143d3779d9882950a6777011e357714e9ce15a 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -489,7 +489,8 @@
   Ipf/Synchronization.c\r
   Ipf/InterlockedCompareExchange64.s\r
   Ipf/InterlockedCompareExchange32.s\r
-  Ipf/CpuBreakpoint.c\r
+  Ipf/CpuBreakpoint.c    | INTEL\r
+  Ipf/CpuBreakpointMsc.c | MSFT\r
   Ipf/Unaligned.c\r
   Ipf/SwitchStack.s\r
   Ipf/longjmp.s\r

diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
index 3dcbecf29d53e0e37f9f43692c3722e11137c43b..59c7e408181c0cecefbf53ac5de158d7a4ebf67e 100644 (file)
--- a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
+++ b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
@@ -17,14 +17,6 @@
 //\r
 #include <BaseLibInternals.h>\r
 \r
-//void __mfa (void);\r
-\r
-#pragma intrinsic (_enable)\r
-#pragma intrinsic (_disable)\r
-#pragma intrinsic (__break)\r
-#pragma intrinsic (__mfa)\r
-\r
-\r
 /**\r
   Generates a breakpoint on the CPU.\r
 \r

diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c b/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
new file mode 100644 (file)
index 0000000..ed53e42
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
@@ -0,0 +1,120 @@
+/** @file\r
+  Base Library CPU functions for Itanium\r
+\r
+  Copyright (c) 2006, Intel Corporation<BR>\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include <BaseLibInternals.h>\r
+\r
+#pragma intrinsic (_enable)\r
+#pragma intrinsic (_disable)\r
+#pragma intrinsic (__break)\r
+#pragma intrinsic (__mfa)\r
+\r
+/**\r
+  Generates a breakpoint on the CPU.\r
+\r
+  Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+  that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+  VOID\r
+  )\r
+{\r
+  __break (0);\r
+}\r
+\r
+/**\r
+  Used to serialize load and store operations.\r
+\r
+  All loads and stores that proceed calls to this function are guaranteed to be\r
+  globally visible when this function returns.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+MemoryFence (\r
+  VOID\r
+  )\r
+{\r
+  __mfa ();\r
+}\r
+\r
+/**\r
+  Disables CPU interrupts.\r
+\r
+  Disables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  _disable ();\r
+}\r
+\r
+/**\r
+  Enables CPU interrupts.\r
+\r
+  Enables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  _enable ();\r
+}\r
+\r
+/**\r
+  Enables CPU interrupts for the smallest window required to capture any\r
+  pending interrupts.\r
+\r
+  Enables CPU interrupts for the smallest window required to capture any\r
+  pending interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableDisableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  EnableInterrupts ();\r
+  DisableInterrupts ();\r
+}\r
+\r
+/**\r
+  Places the CPU in a sleep state until an interrupt is received.\r
+\r
+  Places the CPU in a sleep state until an interrupt is received. If interrupts\r
+  are disabled prior to calling this function, then the CPU will be placed in a\r
+  sleep state indefinitely.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuSleep (\r
+  VOID\r
+  )\r
+{\r
+  PalCallStatic (NULL, 29, 0, 0, 0);\r
+}\r