OvmfPkg: Enable TDX in ResetVector

RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429

Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology
that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory
Encryption (MKTME) with a new kind of virutal machines guest called a
Trust Domain (TD). A TD is desinged to run in a CPU mode that protects the
confidentiality of TD memory contents and the TD's CPU state from other
software, including the hosting Virtual-Machine Monitor (VMM), unless
explicitly shared by the TD itself.

Note: Intel TDX is only available on X64, so the Tdx related changes are
in X64 path. In IA32 path, there may be null stub to make the build
success.

This patch includes below major changes.

1. Ia32/IntelTdx.asm
IntelTdx.asm includes below routines used in ResetVector
 - IsTdx
   Check if the running system is Tdx guest.

 - InitTdxWorkarea
   It initialize the TDX_WORK_AREA. Because it is called by both BSP and
   APs and to avoid the race condition, only BSP can initialize the
   WORK_AREA. AP will wait until the field of TDX_WORK_AREA_PGTBL_READY
   is set.

 - ReloadFlat32
   After reset all CPUs in TDX are initialized to 32-bit protected mode.
   But GDT register is not set. So this routine loads the GDT then jump
   to Flat 32 protected mode again.

 - InitTdx
   This routine wrap above 3 routines together to do Tdx initialization
   in ResetVector phase.

 - IsTdxEnabled
   It is a OneTimeCall to probe if TDX is enabled by checking the
   CC_WORK_AREA.

 - CheckTdxFeaturesBeforeBuildPagetables
   This routine is called to check if it is Non-TDX guest, TDX-Bsp or
   TDX-APs. Because in TDX guest all the initialization is done by BSP
   (including the page tables). APs should not build the tables.

 - TdxPostBuildPageTables
   It is called after Page Tables are built by BSP.
   byte[TDX_WORK_AREA_PGTBL_READY] is set by BSP to indicate APs can
   leave spin and go.

2. Ia32/PageTables64.asm
As described above only the TDX BSP build the page tables. So
PageTables64.asm is updated to make sure only TDX BSP build the
PageTables. TDX APs will skip the page table building and set Cr3
directly.

3. Ia16/ResetVectorVtf0.asm
In Tdx all CPUs "reset" to run on 32-bit protected mode with flat
descriptor (paging disabled). But in Non-Td guest the initial state of
CPUs is 16-bit real mode. To resolve this conflict, BITS 16/32 is used
in the ResetVectorVtf0.asm. It checks the 32-bit protected mode or 16-bit
real mode, then jump to the corresponding entry point.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

diff --git a/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm b/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm
index 7be43fb44a69f2376a999685f7832378acc17795..dee2e3f9de315da48fb597d985caf81440a9adaa 100644 (file)
--- a/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm
+++ b/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm
@@ -177,10 +177,30 @@ resetVector:
 ;\r
 ; This is where the processor will begin execution\r
 ;\r
+; In IA32 we follow the standard reset vector flow. While in X64, Td guest\r
+; may be supported. Td guest requires the startup mode to be 32-bit\r
+; protected mode but the legacy VM startup mode is 16-bit real mode.\r
+; To make NASM generate such shared entry code that behaves correctly in\r
+; both 16-bit and 32-bit mode, more BITS directives are added.\r
+;\r
+%ifdef ARCH_IA32\r
     nop\r
     nop\r
     jmp     EarlyBspInitReal16\r
 \r
+%else\r
+\r
+    mov     eax, cr0\r
+    test    al, 1\r
+    jz      .Real\r
+BITS 32\r
+    jmp     Main32\r
+BITS 16\r
+.Real:\r
+    jmp     EarlyBspInitReal16\r
+\r
+%endif\r
+\r
 ALIGN   16\r
 \r
 fourGigabytes:\r

diff --git a/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm b/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm
index c6d0d898bcd166129f5c3e89234578dd8fd1b434..eb3546668ef82a3fa55276fed74037c2c21177a9 100644 (file)
--- a/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm
+++ b/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm
@@ -21,6 +21,17 @@ Transition32FlatTo64Flat:
     bts     eax, 5                      ; enable PAE\r
     mov     cr4, eax\r
 \r
+    ;\r
+    ; In TDX LME has already been set. So we're done and jump to enable\r
+    ; paging directly if Tdx is enabled.\r
+    ; EBX is cleared because in the later it will be used to check if\r
+    ; the second step of the SEV-ES mitigation is to be performed.\r
+    ;\r
+    xor     ebx, ebx\r
+    OneTimeCall IsTdxEnabled\r
+    test    eax, eax\r
+    jnz     EnablePaging\r
+\r
     mov     ecx, 0xc0000080\r
     rdmsr\r
     bts     eax, 8                      ; set LME\r

diff --git a/OvmfPkg/ResetVector/Ia32/IntelTdx.asm b/OvmfPkg/ResetVector/Ia32/IntelTdx.asm
new file mode 100644 (file)
index 0000000..06794ba
--- /dev/null
+++ b/OvmfPkg/ResetVector/Ia32/IntelTdx.asm
@@ -0,0 +1,222 @@
+;------------------------------------------------------------------------------\r
+; @file\r
+;   Intel TDX routines\r
+;\r
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+%define VM_GUEST_TDX     2\r
+\r
+BITS 32\r
+\r
+;\r
+; Check if it is Intel Tdx\r
+;\r
+; Modified: EAX, EBX, ECX, EDX\r
+;\r
+; If it is Intel Tdx, EAX is 1\r
+; If it is not Intel Tdx, EAX is 0\r
+;\r
+IsTdx:\r
+    ;\r
+    ; CPUID (0)\r
+    ;\r
+    mov     eax, 0\r
+    cpuid\r
+    cmp     ebx, 0x756e6547  ; "Genu"\r
+    jne     IsNotTdx\r
+    cmp     edx, 0x49656e69  ; "ineI"\r
+    jne     IsNotTdx\r
+    cmp     ecx, 0x6c65746e  ; "ntel"\r
+    jne     IsNotTdx\r
+\r
+    ;\r
+    ; CPUID (1)\r
+    ;\r
+    mov     eax, 1\r
+    cpuid\r
+    test    ecx, 0x80000000\r
+    jz      IsNotTdx\r
+\r
+    ;\r
+    ; CPUID[0].EAX >= 0x21?\r
+    ;\r
+    mov     eax, 0\r
+    cpuid\r
+    cmp     eax, 0x21\r
+    jl      IsNotTdx\r
+\r
+    ;\r
+    ; CPUID (0x21,0)\r
+    ;\r
+    mov     eax, 0x21\r
+    mov     ecx, 0\r
+    cpuid\r
+\r
+    cmp     ebx, 0x65746E49   ; "Inte"\r
+    jne     IsNotTdx\r
+    cmp     edx, 0x5844546C   ; "lTDX"\r
+    jne     IsNotTdx\r
+    cmp     ecx, 0x20202020   ; "    "\r
+    jne     IsNotTdx\r
+\r
+    mov     eax, 1\r
+    jmp     ExitIsTdx\r
+\r
+IsNotTdx:\r
+    xor     eax, eax\r
+\r
+ExitIsTdx:\r
+\r
+  OneTimeCallRet IsTdx\r
+\r
+;\r
+; Initialize work area if it is Tdx guest. Detailed definition is in\r
+; OvmfPkg/Include/WorkArea.h.\r
+; BSP and APs all go here. Only BSP initialize this work area.\r
+;\r
+; Param[in] EBX[5:0]    CPU Supported GPAW (48 or 52)\r
+; Param[in] ESI[31:0]   vCPU ID (BSP is 0, others are AP)\r
+;\r
+; Modified:  EBX\r
+;\r
+InitTdxWorkarea:\r
+\r
+    ;\r
+    ; First check if it is Tdx\r
+    ;\r
+    OneTimeCall IsTdx\r
+\r
+    test    eax, eax\r
+    jz      ExitInitTdxWorkarea\r
+\r
+    cmp     esi, 0\r
+    je      TdxBspEntry\r
+\r
+    ;\r
+    ; In Td guest, BSP/AP shares the same entry point\r
+    ; BSP builds up the page table, while APs shouldn't do the same task.\r
+    ; Instead, APs just leverage the page table which is built by BSP.\r
+    ; APs will wait until the page table is ready.\r
+    ;\r
+TdxApWait:\r
+    cmp     byte[TDX_WORK_AREA_PGTBL_READY], 0\r
+    je      TdxApWait\r
+    jmp     ExitInitTdxWorkarea\r
+\r
+TdxBspEntry:\r
+    ;\r
+    ; Set Type of WORK_AREA_GUEST_TYPE so that the following code can use\r
+    ; these information.\r
+    ;\r
+    mov     byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX\r
+\r
+    ;\r
+    ; EBX[5:0] CPU supported GPA width\r
+    ;\r
+    and     ebx, 0x3f\r
+    mov     DWORD[TDX_WORK_AREA_GPAW], ebx\r
+\r
+ExitInitTdxWorkarea:\r
+    OneTimeCallRet InitTdxWorkarea\r
+\r
+;\r
+; Load the GDT and set the CS/DS/ES/FS/GS/SS.\r
+;\r
+; Modified:  EAX, DS, ES, FS, GS, SS, CS\r
+;\r
+ReloadFlat32:\r
+\r
+    cli\r
+    mov     eax, ADDR_OF(gdtr)\r
+    lgdt    [eax]\r
+\r
+    jmp     LINEAR_CODE_SEL:dword ADDR_OF(jumpToFlat32BitAndLandHere)\r
+\r
+jumpToFlat32BitAndLandHere:\r
+\r
+    debugShowPostCode POSTCODE_32BIT_MODE\r
+\r
+    mov     ax, LINEAR_SEL\r
+    mov     ds, ax\r
+    mov     es, ax\r
+    mov     fs, ax\r
+    mov     gs, ax\r
+    mov     ss, ax\r
+\r
+    OneTimeCallRet ReloadFlat32\r
+\r
+;\r
+; Tdx initialization after entering into ResetVector\r
+;\r
+; Modified:  EAX, EBX, ECX, EDX, EBP, EDI, ESP\r
+;\r
+InitTdx:\r
+    ;\r
+    ; First load the GDT and jump to Flat32 mode\r
+    ;\r
+    OneTimeCall ReloadFlat32\r
+\r
+    ;\r
+    ; Initialization of Tdx work area\r
+    ;\r
+    OneTimeCall  InitTdxWorkarea\r
+\r
+    OneTimeCallRet InitTdx\r
+\r
+;\r
+; Check TDX features, TDX or TDX-BSP or TDX-APs?\r
+;\r
+; By design TDX BSP is reponsible for initializing the PageTables.\r
+; After PageTables are ready, byte[TDX_WORK_AREA_PGTBL_READY] is set to 1.\r
+; APs will spin when byte[TDX_WORK_AREA_PGTBL_READY] is 0 until it is set to 1.\r
+;\r
+; When this routine is run on TDX BSP, byte[TDX_WORK_AREA_PGTBL_READY] should be 0.\r
+; When this routine is run on TDX APs, byte[TDX_WORK_AREA_PGTBL_READY] should be 1.\r
+;\r
+;\r
+; Modified:  EAX, EDX\r
+;\r
+; 0-NonTdx, 1-TdxBsp, 2-TdxAps\r
+;\r
+CheckTdxFeaturesBeforeBuildPagetables:\r
+    xor     eax, eax\r
+    cmp     byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX\r
+    jne     NotTdx\r
+\r
+    xor     edx, edx\r
+    mov     al, byte[TDX_WORK_AREA_PGTBL_READY]\r
+    inc     eax\r
+\r
+NotTdx:\r
+    OneTimeCallRet CheckTdxFeaturesBeforeBuildPagetables\r
+\r
+;\r
+; Set byte[TDX_WORK_AREA_PGTBL_READY] to 1\r
+;\r
+TdxPostBuildPageTables:\r
+    cmp     byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX\r
+    jne     ExitTdxPostBuildPageTables\r
+    mov     byte[TDX_WORK_AREA_PGTBL_READY], 1\r
+\r
+ExitTdxPostBuildPageTables:\r
+    OneTimeCallRet TdxPostBuildPageTables\r
+\r
+;\r
+; Check if TDX is enabled\r
+;\r
+; Modified:  EAX\r
+;\r
+; If TDX is enabled then EAX will be 1\r
+; If TDX is disabled then EAX will be 0.\r
+;\r
+IsTdxEnabled:\r
+    xor     eax, eax\r
+    cmp     byte[WORK_AREA_GUEST_TYPE], VM_GUEST_TDX\r
+    jne     TdxNotEnabled\r
+    mov     eax, 1\r
+\r
+TdxNotEnabled:\r
+    OneTimeCallRet IsTdxEnabled\r

diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVector/Ia32/PageTables64.asm
index 02528221e560460ba6c87017ea8c09bef7388d06..317cad430f29f90b59d3890062f5b6ffaf72f3df 100644 (file)
--- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm
+++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm
@@ -37,10 +37,23 @@ BITS    32
                        PAGE_READ_WRITE + \\r
                        PAGE_PRESENT)\r
 \r
+%define TDX_BSP         1\r
+%define TDX_AP          2\r
+\r
 ;\r
 ; Modified:  EAX, EBX, ECX, EDX\r
 ;\r
 SetCr3ForPageTables64:\r
+    ; Check the TDX features.\r
+    ; If it is TDX APs, then jump to SetCr3 directly.\r
+    ; In TD guest the initialization is done by BSP, including building\r
+    ; the page tables. APs will spin on until byte[TDX_WORK_AREA_PGTBL_READY]\r
+    ; is set.\r
+    OneTimeCall   CheckTdxFeaturesBeforeBuildPagetables\r
+    cmp       eax, TDX_BSP\r
+    je        ClearOvmfPageTables\r
+    cmp       eax, TDX_AP\r
+    je        SetCr3\r
 \r
     ; Check whether the SEV is active and populate the SevEsWorkArea\r
     OneTimeCall   CheckSevFeatures\r
@@ -50,6 +63,7 @@ SetCr3ForPageTables64:
     ; the page table build below.\r
     OneTimeCall   GetSevCBitMaskAbove31\r
 \r
+ClearOvmfPageTables:\r
     ;\r
     ; For OVMF, build some initial page tables at\r
     ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).\r
@@ -101,6 +115,10 @@ pageTableEntriesLoop:
     ; Clear the C-bit from the GHCB page if the SEV-ES is enabled.\r
     OneTimeCall   SevClearPageEncMaskForGhcbPage\r
 \r
+    ; TDX will do some PostBuildPages task, such as setting\r
+    ; byte[TDX_WORK_AREA_PGTBL_READY].\r
+    OneTimeCall   TdxPostBuildPageTables\r
+\r
 SetCr3:\r
     ;\r
     ; Set CR3 now that the paging structures are available\r

diff --git a/OvmfPkg/ResetVector/Main.asm b/OvmfPkg/ResetVector/Main.asm
index bbfeac1c88bc1e70f5b64682d6c5dc948b3733c6..5cfc0b5c72b11982c2eaf3c6b05a9fc9421bb10d 100644 (file)
--- a/OvmfPkg/ResetVector/Main.asm
+++ b/OvmfPkg/ResetVector/Main.asm
@@ -40,6 +40,20 @@ BITS    32
     ; work area when detected.\r
     mov     byte[WORK_AREA_GUEST_TYPE], 0\r
 \r
+%ifdef ARCH_X64\r
+\r
+    jmp SearchBfv\r
+\r
+;\r
+; Entry point of Main32\r
+;\r
+Main32:\r
+    OneTimeCall InitTdx\r
+\r
+SearchBfv:\r
+\r
+%endif\r
+\r
     ;\r
     ; Search for the Boot Firmware Volume (BFV)\r
     ;\r

diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/ResetVector.nasmb
index eb9733e402561dcc6834f64556492bc565af69b7..87effedb9c60a17945d67b0fccb4671d4e73fc0f 100644 (file)
--- a/OvmfPkg/ResetVector/ResetVector.nasmb
+++ b/OvmfPkg/ResetVector/ResetVector.nasmb
@@ -108,6 +108,7 @@
 %include "Ia32/Flat32ToFlat64.asm"\r
 %include "Ia32/AmdSev.asm"\r
 %include "Ia32/PageTables64.asm"\r
+%include "Ia32/IntelTdx.asm"\r
 %endif\r
 \r
 %include "Ia16/Real16ToFlat32.asm"\r