IN UINTN Address\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT8 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoRead8 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3));\r
+ Result = IoRead8 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3));\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT8 Value\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT8 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoWrite8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- Value\r
- );\r
+ Result = IoWrite8 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
+ Value\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT8 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT8 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoOr8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- OrData\r
- );\r
+ Result = IoOr8 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT8 AndData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT8 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAnd8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- AndData\r
- );\r
+ Result = IoAnd8 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
+ AndData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT8 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT8 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAndThenOr8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- AndData,\r
- OrData\r
- );\r
+ Result = IoAndThenOr8 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
+ AndData,\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINTN EndBit\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT8 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldRead8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- StartBit,\r
- EndBit\r
- );\r
+ Result = IoBitFieldRead8 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
+ StartBit,\r
+ EndBit\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT8 Value\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT8 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldWrite8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
+ Result = IoBitFieldWrite8 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
+ StartBit,\r
+ EndBit,\r
+ Value\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT8 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT8 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldOr8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
+ Result = IoBitFieldOr8 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT8 AndData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT8 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAnd8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
+ Result = IoBitFieldAnd8 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
+ StartBit,\r
+ EndBit,\r
+ AndData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT8 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT8 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAndThenOr8 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
+ Result = IoBitFieldAndThenOr8 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINTN Address\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT16 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoRead16 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2));\r
+ Result = IoRead16 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2));\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT16 Value\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT16 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoWrite16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- Value\r
- );\r
+ Result = IoWrite16 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
+ Value\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT16 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT16 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoOr16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- OrData\r
- );\r
+ Result = IoOr16 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT16 AndData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT16 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAnd16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- AndData\r
- );\r
+ Result = IoAnd16 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
+ AndData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT16 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT16 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAndThenOr16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- AndData,\r
- OrData\r
- );\r
+ Result = IoAndThenOr16 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
+ AndData,\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINTN EndBit\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT16 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldRead16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- StartBit,\r
- EndBit\r
- );\r
+ Result = IoBitFieldRead16 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
+ StartBit,\r
+ EndBit\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT16 Value\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT16 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldWrite16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
+ Result = IoBitFieldWrite16 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
+ StartBit,\r
+ EndBit,\r
+ Value\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT16 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT16 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldOr16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
+ Result = IoBitFieldOr16 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT16 AndData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT16 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAnd16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
+ Result = IoBitFieldAnd16 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
+ StartBit,\r
+ EndBit,\r
+ AndData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT16 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT16 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAndThenOr16 (\r
- PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
+ Result = IoBitFieldAndThenOr16 (\r
+ PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINTN Address\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT32 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoRead32 (PCI_CONFIGURATION_DATA_PORT);\r
+ Result = IoRead32 (PCI_CONFIGURATION_DATA_PORT);\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT32 Value\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT32 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoWrite32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- Value\r
- );\r
+ Result = IoWrite32 (\r
+ PCI_CONFIGURATION_DATA_PORT,\r
+ Value\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT32 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT32 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoOr32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- OrData\r
- );\r
+ Result = IoOr32 (\r
+ PCI_CONFIGURATION_DATA_PORT,\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT32 AndData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT32 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAnd32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- AndData\r
- );\r
+ Result = IoAnd32 (\r
+ PCI_CONFIGURATION_DATA_PORT,\r
+ AndData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT32 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT32 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoAndThenOr32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- AndData,\r
- OrData\r
- );\r
+ Result = IoAndThenOr32 (\r
+ PCI_CONFIGURATION_DATA_PORT,\r
+ AndData,\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINTN EndBit\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT32 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldRead32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit\r
- );\r
+ Result = IoBitFieldRead32 (\r
+ PCI_CONFIGURATION_DATA_PORT,\r
+ StartBit,\r
+ EndBit\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT32 Value\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT32 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldWrite32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
+ Result = IoBitFieldWrite32 (\r
+ PCI_CONFIGURATION_DATA_PORT,\r
+ StartBit,\r
+ EndBit,\r
+ Value\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT32 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT32 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldOr32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
+ Result = IoBitFieldOr32 (\r
+ PCI_CONFIGURATION_DATA_PORT,\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT32 AndData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT32 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAnd32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
+ Result = IoBitFieldAnd32 (\r
+ PCI_CONFIGURATION_DATA_PORT,\r
+ StartBit,\r
+ EndBit,\r
+ AndData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r
IN UINT32 OrData\r
)\r
{\r
+ BOOLEAN InterruptState;\r
+ UINT32 AddressPort;\r
+ UINT32 Result;\r
+ \r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
+ InterruptState = SaveAndDisableInterrupts ();\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
- return IoBitFieldAndThenOr32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
+ Result = IoBitFieldAndThenOr32 (\r
+ PCI_CONFIGURATION_DATA_PORT,\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
+ IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
+ SetInterruptState (InterruptState);\r
+ return Result;\r
}\r
\r
/**\r