]> git.proxmox.com Git - mirror_edk2.git/commitdiff
IntelFsp2Pkg/SplitFspBin.py: adopt FSP 2.3 specification.
authorChasel Chiu <chasel.chiu@intel.com>
Tue, 26 Oct 2021 07:53:37 +0000 (15:53 +0800)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Wed, 27 Oct 2021 11:54:06 +0000 (11:54 +0000)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3705

FSP 2.3 has updated FSP_INFO_HEADER to support ExtendedImageRevision
and SplitFspBin.py needs to support it.

Also updated script to display integer value basing on length.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
IntelFsp2Pkg/Tools/SplitFspBin.py

index 24272e82af88cb832ca68a5fa7a3571f31671112..20e329a76e06a21107b9940e848b7378018efeb8 100644 (file)
@@ -1,6 +1,6 @@
 ## @ FspTool.py\r
 #\r
-# Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>\r
 # SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
 ##\r
@@ -103,26 +103,29 @@ class FSP_COMMON_HEADER(Structure):
 \r
 class FSP_INFORMATION_HEADER(Structure):\r
      _fields_ = [\r
-        ('Signature',            ARRAY(c_char, 4)),\r
-        ('HeaderLength',         c_uint32),\r
-        ('Reserved1',            c_uint16),\r
-        ('SpecVersion',          c_uint8),\r
-        ('HeaderRevision',       c_uint8),\r
-        ('ImageRevision',        c_uint32),\r
-        ('ImageId',              ARRAY(c_char, 8)),\r
-        ('ImageSize',            c_uint32),\r
-        ('ImageBase',            c_uint32),\r
-        ('ImageAttribute',       c_uint16),\r
-        ('ComponentAttribute',   c_uint16),\r
-        ('CfgRegionOffset',      c_uint32),\r
-        ('CfgRegionSize',        c_uint32),\r
-        ('Reserved2',            c_uint32),\r
-        ('TempRamInitEntryOffset',     c_uint32),\r
-        ('Reserved3',                  c_uint32),\r
-        ('NotifyPhaseEntryOffset',     c_uint32),\r
-        ('FspMemoryInitEntryOffset',   c_uint32),\r
-        ('TempRamExitEntryOffset',     c_uint32),\r
-        ('FspSiliconInitEntryOffset',  c_uint32)\r
+        ('Signature',                      ARRAY(c_char, 4)),\r
+        ('HeaderLength',                   c_uint32),\r
+        ('Reserved1',                      c_uint16),\r
+        ('SpecVersion',                    c_uint8),\r
+        ('HeaderRevision',                 c_uint8),\r
+        ('ImageRevision',                  c_uint32),\r
+        ('ImageId',                        ARRAY(c_char, 8)),\r
+        ('ImageSize',                      c_uint32),\r
+        ('ImageBase',                      c_uint32),\r
+        ('ImageAttribute',                 c_uint16),\r
+        ('ComponentAttribute',             c_uint16),\r
+        ('CfgRegionOffset',                c_uint32),\r
+        ('CfgRegionSize',                  c_uint32),\r
+        ('Reserved2',                      c_uint32),\r
+        ('TempRamInitEntryOffset',         c_uint32),\r
+        ('Reserved3',                      c_uint32),\r
+        ('NotifyPhaseEntryOffset',         c_uint32),\r
+        ('FspMemoryInitEntryOffset',       c_uint32),\r
+        ('TempRamExitEntryOffset',         c_uint32),\r
+        ('FspSiliconInitEntryOffset',      c_uint32),\r
+        ('FspMultiPhaseSiInitEntryOffset', c_uint32),\r
+        ('ExtendedImageRevision',          c_uint16),\r
+        ('Reserved4',                      c_uint16)\r
     ]\r
 \r
 class FSP_PATCH_TABLE(Structure):\r
@@ -390,7 +393,26 @@ def OutputStruct (obj, indent = 0, plen = 0):
             if IsStrType (val):\r
                 rep = HandleNameStr (val)\r
             elif IsIntegerType (val):\r
-                rep = '0x%X' % val\r
+                if (key == 'ImageRevision'):\r
+                    FspImageRevisionMajor       = ((val >> 24) & 0xFF)\r
+                    FspImageRevisionMinor       = ((val >> 16) & 0xFF)\r
+                    FspImageRevisionRevision    = ((val >> 8) & 0xFF)\r
+                    FspImageRevisionBuildNumber = (val & 0xFF)\r
+                    rep = '0x%08X' % val\r
+                elif (key == 'ExtendedImageRevision'):\r
+                    FspImageRevisionRevision    |= (val & 0xFF00)\r
+                    FspImageRevisionBuildNumber |= ((val << 8) & 0xFF00)\r
+                    rep = "0x%04X ('%02X.%02X.%04X.%04X')" % (val, FspImageRevisionMajor, FspImageRevisionMinor, FspImageRevisionRevision, FspImageRevisionBuildNumber)\r
+                elif field[1] == c_uint64:\r
+                    rep = '0x%016X' % val\r
+                elif field[1] == c_uint32:\r
+                    rep = '0x%08X' % val\r
+                elif field[1] == c_uint16:\r
+                    rep = '0x%04X' % val\r
+                elif field[1] == c_uint8:\r
+                    rep = '0x%02X' % val\r
+                else:\r
+                    rep = '0x%X' % val\r
             elif isinstance(val, c_uint24):\r
                 rep = '0x%X' % val.get_value()\r
             elif 'c_ubyte_Array' in str(type(val)):\r