OvmfPkg: Handle Cloud Hypervisor host bridge

Handle things differently when the detected host bridge matches the
Cloud Hypervisor PCI host bridge identifier.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Rob Bradford <robert.bradford@intel.com>
Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>

diff --git a/OvmfPkg/Include/IndustryStandard/CloudHv.h b/OvmfPkg/Include/IndustryStandard/CloudHv.h
new file mode 100644 (file)
index 0000000..1155335
--- /dev/null
+++ b/OvmfPkg/Include/IndustryStandard/CloudHv.h
@@ -0,0 +1,36 @@
+/** @file\r
+  Various defines related to Cloud Hypervisor\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef __CLOUDHV_H__\r
+#define __CLOUDHV_H__\r
+\r
+//\r
+// Host Bridge Device ID\r
+//\r
+#define CLOUDHV_DEVICE_ID  0x0d57\r
+\r
+//\r
+// ACPI timer address\r
+//\r
+#define CLOUDHV_ACPI_TIMER_IO_ADDRESS  0xb008\r
+\r
+//\r
+// ACPI shutdown device address\r
+//\r
+#define CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS  0x03c0\r
+\r
+//\r
+// 32-bit MMIO memory hole base address\r
+//\r
+#define CLOUDHV_MMIO_HOLE_ADDRESS  0xc0000000\r
+\r
+//\r
+// 32-bit MMIO memory hole size\r
+//\r
+#define CLOUDHV_MMIO_HOLE_SIZE  0x38000000\r
+\r
+#endif // __CLOUDHV_H__\r

diff --git a/OvmfPkg/Include/OvmfPlatforms.h b/OvmfPkg/Include/OvmfPlatforms.h
index de5d7663b469d95c3fca2ad7f779664df6fb009c..f613dd7e2d565147956041e5d390249cac43e491 100644 (file)
--- a/OvmfPkg/Include/OvmfPlatforms.h
+++ b/OvmfPkg/Include/OvmfPlatforms.h
@@ -16,6 +16,7 @@
 #include <IndustryStandard/I440FxPiix4.h>\r
 #include <IndustryStandard/Bhyve.h>\r
 #include <IndustryStandard/Microvm.h>\r
+#include <IndustryStandard/CloudHv.h>\r
 \r
 //\r
 // OVMF Host Bridge DID Address\r

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index 1d33c863134c62d878307beb6688daea218dd832..6d1e1cb05e00091f425093e325bf85a8bd8e4a2d 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -55,6 +55,9 @@ AcpiTimerLibConstructor (
       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
       break;\r
+    case CLOUDHV_DEVICE_ID:\r
+      mAcpiTimerIoAddr =  CLOUDHV_ACPI_TIMER_IO_ADDRESS;\r
+      return RETURN_SUCCESS;\r
     default:\r
       DEBUG ((\r
         DEBUG_ERROR,\r

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index 54a288d52ff5d33c9c3506a358403c48d5b8b103..c771997a2a493851e4057f0736b7cd1a4d4aa64a 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -53,6 +53,8 @@ AcpiTimerLibConstructor (
       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
       break;\r
+    case CLOUDHV_DEVICE_ID:\r
+      return RETURN_SUCCESS;\r
     default:\r
       DEBUG ((\r
         DEBUG_ERROR,\r
@@ -111,6 +113,8 @@ InternalAcpiGetTimerTick (
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
       break;\r
+    case CLOUDHV_DEVICE_ID:\r
+      return IoRead32 (CLOUDHV_ACPI_TIMER_IO_ADDRESS);\r
     default:\r
       DEBUG ((\r
         DEBUG_ERROR,\r

diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
index 01f28b29160acb0504308dd75f422614a33b7cd1..1158461874550db1b8c40a5a1560e09ceff78cbc 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
@@ -50,6 +50,9 @@ AcpiTimerLibConstructor (
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
       break;\r
+    case CLOUDHV_DEVICE_ID:\r
+      mAcpiTimerIoAddr = CLOUDHV_ACPI_TIMER_IO_ADDRESS;\r
+      return RETURN_SUCCESS;\r
     default:\r
       DEBUG ((\r
         DEBUG_ERROR,\r

diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
index f73c59dfff501b54f94b9bb2cfdf93272ac36ba3..5feadc51d7469f6ec7fba6c828951bc22da5d809 100644 (file)
--- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
@@ -1390,6 +1390,7 @@ PciAcpiInitialization (
       PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), PciHostIrqs[3]); // H\r
       break;\r
     case MICROVM_PSEUDO_DEVICE_ID:\r
+    case CLOUDHV_DEVICE_ID:\r
       return;\r
     default:\r
       if (XenDetected ()) {\r

diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c b/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c
index 29abd57fa7995caac4b29432380bc8cbaceb365a..c21d3c89cf95177eceda541c32920cadeeb63b23 100644 (file)
--- a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c
+++ b/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c
@@ -40,6 +40,9 @@ ResetShutdown (
     case INTEL_Q35_MCH_DEVICE_ID:\r
       AcpiPmBaseAddress = ICH9_PMBASE_VALUE;\r
       break;\r
+    case CLOUDHV_DEVICE_ID:\r
+      IoWrite8 (CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS, 5 << 2 | 1 << 5);\r
+      CpuDeadLoop ();\r
     default:\r
       ASSERT (FALSE);\r
       CpuDeadLoop ();\r

diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c b/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c
index a0db8b50bf839bff81529c0fe66bec8eb103d756..31f01b82e4eee43b5424812eb4de91bb50134fcd 100644 (file)
--- a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c
+++ b/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c
@@ -16,6 +16,7 @@
 #include <OvmfPlatforms.h>          // PIIX4_PMBA_VALUE\r
 \r
 STATIC UINT16  mAcpiPmBaseAddress;\r
+STATIC UINT16  mAcpiHwReducedSleepCtl;\r
 \r
 EFI_STATUS\r
 EFIAPI\r
@@ -34,6 +35,9 @@ DxeResetInit (
     case INTEL_Q35_MCH_DEVICE_ID:\r
       mAcpiPmBaseAddress = ICH9_PMBASE_VALUE;\r
       break;\r
+    case CLOUDHV_DEVICE_ID:\r
+      mAcpiHwReducedSleepCtl = CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS;\r
+      break;\r
     default:\r
       ASSERT (FALSE);\r
       CpuDeadLoop ();\r
@@ -56,7 +60,12 @@ ResetShutdown (
   VOID\r
   )\r
 {\r
-  IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0);\r
-  IoOr16 (mAcpiPmBaseAddress + 4, BIT13);\r
+  if (mAcpiHwReducedSleepCtl) {\r
+    IoWrite8 (mAcpiHwReducedSleepCtl, 5 << 2 | 1 << 5);\r
+  } else {\r
+    IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0);\r
+    IoOr16 (mAcpiPmBaseAddress + 4, BIT13);\r
+  }\r
+\r
   CpuDeadLoop ();\r
 }\r

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 738ed0c208ae53ffc6888de2f9bd49edf2b1947f..934d5c196570cbbece58eb77b2718340a8ea68bb 100644 (file)
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -16,6 +16,7 @@ Module Name:
 #include <IndustryStandard/E820.h>\r
 #include <IndustryStandard/I440FxPiix4.h>\r
 #include <IndustryStandard/Q35MchIch9.h>\r
+#include <IndustryStandard/CloudHv.h>\r
 #include <PiPei.h>\r
 #include <Register/Intel/SmramSaveStateMap.h>\r
 \r
@@ -159,6 +160,12 @@ QemuUc32BaseInitialization (
     return;\r
   }\r
 \r
+  if (mHostBridgeDevId == CLOUDHV_DEVICE_ID) {\r
+    Uc32Size      = CLOUDHV_MMIO_HOLE_SIZE;\r
+    mQemuUc32Base = CLOUDHV_MMIO_HOLE_ADDRESS;\r
+    return;\r
+  }\r
+\r
   ASSERT (mHostBridgeDevId == INTEL_82441_DEVICE_ID);\r
   //\r
   // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one\r
@@ -819,7 +826,7 @@ QemuInitializeRam (
   // practically any alignment, and we may not have enough variable MTRRs to\r
   // cover it exactly.\r
   //\r
-  if (IsMtrrSupported ()) {\r
+  if (IsMtrrSupported () && (mHostBridgeDevId != CLOUDHV_DEVICE_ID)) {\r
     MtrrGetAllMtrrs (&MtrrSettings);\r
 \r
     //\r

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 3000176efdbf96cebd31923cb55df9905dd6b154..906f64615de7b0c90d04313ba9796d668f1aa25e 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -374,6 +374,14 @@ MiscInitialization (
                     );\r
       ASSERT_RETURN_ERROR (PcdStatus);\r
       return;\r
+    case CLOUDHV_DEVICE_ID:\r
+      DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION__));\r
+      PcdStatus = PcdSet16S (\r
+                    PcdOvmfHostBridgePciDevId,\r
+                    CLOUDHV_DEVICE_ID\r
+                    );\r
+      ASSERT_RETURN_ERROR (PcdStatus);\r
+      return;\r
     default:\r
       DEBUG ((\r
         DEBUG_ERROR,\r