MdeModulePkg/DxeIpl: Create 5-level page table for long mode

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008

Correct the logic about whether 5-level paging is supported.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 0700f310b203eb5cc0ec6b1ea491ad0cd1787f87..1ebab2782010ba77c4a4558a85b86f3a174635c3 100644 (file)
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
     2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
 \r
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
 \r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
@@ -748,8 +748,8 @@ CreateIdentityMappingPageTables (
       CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
       CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
       NULL,\r
-      &EcxFlags.Uint32,\r
       NULL,\r
+      &EcxFlags.Uint32,\r
       NULL\r
       );\r
     if (EcxFlags.Bits.FiveLevelPage != 0) {\r