Update MDE Library instances according to code review comments.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@5823 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c
index d9605566fd52c1773215c57c6b97bacd8c8b37ef..0e70f2d1561a88efc70232dc53d9952855bbeab1 100644 (file)
--- a/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c
@@ -1,7 +1,7 @@
 /** @file\r
   Cache Maintenance Functions.\r
 \r
-  Copyright (c) 2006, Intel Corporation<BR>\r
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
   All rights reserved. This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -12,9 +12,6 @@
 \r
 **/\r
 \r
-//\r
-// Include common header file for this module.\r
-//\r
 #include <Base.h>\r
 #include <Library/DebugLib.h>\r
 \r
@@ -22,9 +19,6 @@
   Invalidates the entire instruction cache in cache coherency domain of the\r
   calling CPU.\r
 \r
-  Invalidates the entire instruction cache in cache coherency domain of the\r
-  calling CPU.\r
-\r
 **/\r
 VOID\r
 EFIAPI\r
@@ -165,7 +159,7 @@ WriteBackDataCache (
                   mode, then Address is a virtual address.\r
   @param  Length  The number of bytes to write back from the data cache.\r
 \r
-  @return Address of cache wrote in main memory.\r
+  @return Address of cache written in main memory.\r
 \r
 **/\r
 VOID *\r

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
index a46df594973f69b294f42d6641be37cdf1a6c09e..fc6ea25d5202bea65d51dff35dca66091fa5850e 100644 (file)
--- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
@@ -1,7 +1,7 @@
 /** @file\r
   Cache Maintenance Functions.\r
 \r
-  Copyright (c) 2006, Intel Corporation<BR>\r
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
   All rights reserved. This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -12,10 +12,6 @@
 \r
 **/\r
 \r
-\r
-//\r
-// Include common header file for this module.\r
-//\r
 #include <Base.h>\r
 #include <Library/CacheMaintenanceLib.h>\r
 #include <Library/BaseLib.h>\r
@@ -26,9 +22,6 @@
   Invalidates the entire instruction cache in cache coherency domain of the\r
   calling CPU.\r
 \r
-  Invalidates the entire instruction cache in cache coherency domain of the\r
-  calling CPU.\r
-\r
 **/\r
 VOID\r
 EFIAPI\r
@@ -36,7 +29,7 @@ InvalidateInstructionCache (
   VOID\r
   )\r
 {\r
-  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES, 0);\r
+  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
 }\r
 \r
 /**\r
@@ -61,7 +54,7 @@ InvalidateInstructionCache (
 \r
   @param  Length  The number of bytes to invalidate from the instruction cache.\r
 \r
-  @return Address of cahce invalidation.\r
+  @return Address of cache invalidation.\r
 \r
 **/\r
 VOID *\r
@@ -71,6 +64,7 @@ InvalidateInstructionCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
+  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
   return IpfFlushCacheRange (Address, Length);\r
 }\r
 \r
@@ -90,7 +84,7 @@ WriteBackInvalidateDataCache (
   VOID\r
   )\r
 {\r
-  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES, 0);\r
+  PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r
 }\r
 \r
 /**\r
@@ -172,7 +166,7 @@ WriteBackDataCache (
                   mode, then Address is a virtual address.\r
   @param  Length  The number of bytes to write back from the data cache.\r
 \r
-  @return Address of cache wrote in main memory.\r
+  @return Address of cache written in main memory.\r
 \r
 **/\r
 VOID *\r
@@ -204,6 +198,10 @@ InvalidateDataCache (
   VOID\r
   )\r
 {\r
+  //\r
+  // Invalidation of entire data cache without writing back is not supported on\r
+  // IPF architecture, so write back and invalidate operation is performed.\r
+  //\r
   WriteBackInvalidateDataCache ();\r
 }\r
 \r
@@ -241,5 +239,10 @@ InvalidateDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
+  ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+  //\r
+  // Invalidation of a data cache range without writing back is not supported on\r
+  // IPF architecture, so write back and invalidate operation is performed.\r
+  //\r
   return IpfFlushCacheRange (Address, Length);\r
 }\r

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c b/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
index 1fc2b95daa999c25f32b6c038d487f4460fe5d6b..8b169c22444fac664eedc8017e36986d5fe5aa01 100644 (file)
--- a/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
@@ -1,7 +1,7 @@
 /** @file\r
   Cache Maintenance Functions.\r
 \r
-  Copyright (c) 2006, Intel Corporation<BR>\r
+  Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
   All rights reserved. This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -13,9 +13,6 @@
 \r
 **/\r
 \r
-//\r
-// Include common header file for this module.\r
-//\r
 #include <Base.h>\r
 #include <Library/BaseLib.h>\r
 #include <Library/DebugLib.h>\r
@@ -30,9 +27,6 @@
   Invalidates the entire instruction cache in cache coherency domain of the\r
   calling CPU.\r
 \r
-  Invalidates the entire instruction cache in cache coherency domain of the\r
-  calling CPU.\r
-\r
 **/\r
 VOID\r
 EFIAPI\r
@@ -130,7 +124,8 @@ WriteBackInvalidateDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
-  UINTN                             Start, End;\r
+  UINTN                             Start;\r
+  UINTN                             End;\r
 \r
   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
 \r
@@ -192,7 +187,7 @@ WriteBackDataCache (
                   mode, then Address is a virtual address.\r
   @param  Length  The number of bytes to write back from the data cache.\r
 \r
-  @return Address of cache wrote in main memory.\r
+  @return Address of cache written in main memory.\r
 \r
 **/\r
 VOID *\r
@@ -259,5 +254,9 @@ InvalidateDataCacheRange (
   IN      UINTN                     Length\r
   )\r
 {\r
+  //\r
+  // Invalidation of a data cache range without writing back is not supported on\r
+  // x86 architecture, so write back and invalidate operation is performed.\r
+  //\r
   return WriteBackInvalidateDataCacheRange (Address, Length);\r
 }\r

diff --git a/MdePkg/Library/BaseDebugLibNull/DebugLib.c b/MdePkg/Library/BaseDebugLibNull/DebugLib.c
index a540411bcaa872e1b8546e0233c8df468423ee98..9259ab6432a888ba2910e17c5110146ddd104345 100644 (file)
--- a/MdePkg/Library/BaseDebugLibNull/DebugLib.c
+++ b/MdePkg/Library/BaseDebugLibNull/DebugLib.c
@@ -14,14 +14,9 @@
 \r
 \r
 #include <Base.h>\r
-\r
-//\r
-// The Library classes this module produced\r
-//\r
 #include <Library/DebugLib.h>\r
 \r
 /**\r
-\r
   Prints a debug message to the debug output device if the specified error level is enabled.\r
 \r
   If any bit in ErrorLevel is also set in PcdDebugPrintErrorLevel, then print \r
@@ -45,7 +40,6 @@ DebugPrint (
 \r
 \r
 /**\r
-\r
   Prints an assert message containing a filename, line number, and description.  \r
   This may be followed by a breakpoint or a dead loop.\r
 \r
@@ -79,7 +73,6 @@ DebugAssert (
 \r
 \r
 /**\r
-\r
   Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
 \r
   This function fills Length bytes of Buffer with the value specified by \r
@@ -107,7 +100,6 @@ DebugClearMemory (
 \r
 \r
 /**\r
-  \r
   Returns TRUE if ASSERT() macros are enabled.\r
 \r
   This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of \r
@@ -130,8 +122,7 @@ DebugAssertEnabled (
 \r
 \r
 /**\r
-  \r
-  Returns TRUE if DEBUG()macros are enabled.\r
+  Returns TRUE if the DEBUG() macro is enabled.\r
 \r
   This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of \r
   PcdDebugProperyMask is set.  Otherwise FALSE is returned.\r
@@ -153,8 +144,7 @@ DebugPrintEnabled (
 \r
 \r
 /**\r
-  \r
-  Returns TRUE if DEBUG_CODE()macros are enabled.\r
+  Returns TRUE if the DEBUG_CODE() macros are enabled.\r
 \r
   This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of \r
   PcdDebugProperyMask is set.  Otherwise FALSE is returned.\r
@@ -176,8 +166,7 @@ DebugCodeEnabled (
 \r
 \r
 /**\r
-  \r
-  Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.\r
+  Returns TRUE if the DEBUG_CLEAR_MEMORY() macro is enabled.\r
 \r
   This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of \r
   PcdDebugProperyMask is set.  Otherwise FALSE is returned.\r

diff --git a/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c b/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c
index 2c92365ec8ef3aa7c738ba99d45c2a8fea860e47..266b25cdcf3e293421c97c791dd4f0fb06bdf71a 100644 (file)
--- a/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c
+++ b/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c
@@ -29,7 +29,6 @@
 \r
 \r
 /**\r
-\r
   Prints a debug message to the debug output device if the specified error level is enabled.\r
 \r
   If any bit in ErrorLevel is also set in PcdDebugPrintErrorLevel, then print \r
@@ -81,7 +80,6 @@ DebugPrint (
 \r
 \r
 /**\r
-\r
   Prints an assert message containing a filename, line number, and description.  \r
   This may be followed by a breakpoint or a dead loop.\r
 \r
@@ -135,7 +133,6 @@ DebugAssert (
 \r
 \r
 /**\r
-\r
   Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
 \r
   This function fills Length bytes of Buffer with the value specified by \r
@@ -148,7 +145,7 @@ DebugAssert (
   @param   Buffer  Pointer to the target buffer to be filled with PcdDebugClearMemoryValue.\r
   @param   Length  Number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue. \r
 \r
-  @return  Buffer  Pointer to the target buffer filled with PcdDebugClearMemoryValue.\r
+  @return  Buffer filled with PcdDebugClearMemoryValue.\r
 \r
 **/\r
 VOID *\r
@@ -171,7 +168,6 @@ DebugClearMemory (
 \r
 \r
 /**\r
-  \r
   Returns TRUE if ASSERT() macros are enabled.\r
 \r
   This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of \r
@@ -192,8 +188,7 @@ DebugAssertEnabled (
 \r
 \r
 /**\r
-  \r
-  Returns TRUE if DEBUG()macros are enabled.\r
+  Returns TRUE if the DEBUG() macro is enabled.\r
 \r
   This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of \r
   PcdDebugProperyMask is set.  Otherwise FALSE is returned.\r
@@ -213,8 +208,7 @@ DebugPrintEnabled (
 \r
 \r
 /**\r
-  \r
-  Returns TRUE if DEBUG_CODE()macros are enabled.\r
+  Returns TRUE if the DEBUG_CODE() macros are enabled.\r
 \r
   This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of \r
   PcdDebugProperyMask is set.  Otherwise FALSE is returned.\r
@@ -234,8 +228,7 @@ DebugCodeEnabled (
 \r
 \r
 /**\r
-  \r
-  Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.\r
+  Returns TRUE if the DEBUG_CLEAR_MEMORY() macro is enabled.\r
 \r
   This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of \r
   PcdDebugProperyMask is set.  Otherwise FALSE is returned.\r

diff --git a/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf b/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
index 4e9c64aab1745775ff10e6725bd7fe56fac17676..13629c741815efdecff39a9088a2c4bd63e1aff6 100644 (file)
--- a/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+++ b/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
@@ -1,5 +1,5 @@
 #/** @file\r
-# This driver implemnets one PCI Cf8 Library instance.\r
+# This module implements PCI CF8 Library instance.\r
 #\r
 # PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.\r
 #  Layers on top of an I/O Library instance.\r

diff --git a/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c b/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
index 2754d305607498fc7ddfcab10ab34246b82cd46d..995e4ab1b7154ed9efde34670d62f977d7644e03 100644 (file)
--- a/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
+++ b/MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
@@ -27,32 +27,19 @@
 #define PCI_CONFIGURATION_ADDRESS_PORT  0xCF8\r
 #define PCI_CONFIGURATION_DATA_PORT     0xCFC\r
 \r
-//\r
-// Declare macro to convert PCI Library formatted address to CF8 formatted address\r
-//\r
-// PCI Library formatted address    CF8 Formatted Address\r
-// =============================    ======================\r
-//    Bits 00..11  Register           Bits 00..07  Register\r
-//    Bits 12..14  Function           Bits 08..10  Function\r
-//    Bits 15..19  Device             Bits 11..15  Device\r
-//    Bits 20..27  Bus                Bits 16..23  Bus\r
-//    Bits 28..31  Reserved(MBZ)      Bits 24..30  Reserved(MBZ)\r
-//                                    Bits 31..31  Must be 1\r
-//\r
-\r
-/**\r
-  Assert the validity of a PCI address. A valid PCI address should contain 1's\r
-  only in the low 28 bits.\r
-\r
-  @param  A The address to validate.\r
-  @param  M Additional bits to assert to be zero.\r
-\r
-**/\r
-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
-  ASSERT (((A) & (~0xffff0ff | (M))) == 0)\r
-\r
 /**\r
-  Convert a PCI Express address to PCI CF8 address.\r
+  Convert a PCI Library address to PCI CF8 formatted address.\r
+\r
+  Declare macro to convert PCI Library address to PCI CF8 formatted address.\r
+  Bit fields of PCI Library and CF8 formatted address is as follows:\r
+  PCI Library formatted address    CF8 Formatted Address\r
+ =============================    ======================\r
+    Bits 00..11  Register           Bits 00..07  Register\r
+    Bits 12..14  Function           Bits 08..10  Function\r
+    Bits 15..19  Device             Bits 11..15  Device\r
+    Bits 20..27  Bus                Bits 16..23  Bus\r
+    Bits 28..31  Reserved(MBZ)      Bits 24..30  Reserved(MBZ)\r
+                                    Bits 31..31  Must be 1\r
 \r
   @param  A The address to convert.\r
 \r
@@ -62,6 +49,17 @@
 #define PCI_TO_CF8_ADDRESS(A) \\r
   ((UINT32) ((((A) >> 4) & 0x00ffff00) | ((A) & 0xfc) | 0x80000000))\r
 \r
+/**\r
+  Assert the validity of a PCI CF8 address. A valid PCI CF8 address should contain 1's\r
+  only in the low 28 bits, excluding bits 08..11.\r
+\r
+  @param  A The address to validate.\r
+  @param  M Additional bits to assert to be zero.\r
+\r
+**/\r
+#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
+  ASSERT (((A) & (~0xffff0ff | (M))) == 0)\r
+\r
 /**\r
   Reads an 8-bit PCI configuration register.\r
 \r

diff --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
index b6f87f173845d4e0ed656afa7e9b22af4b0ce1f9..779524cdeab6f3873235a4e470f8a788d3a5a010 100644 (file)
--- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
@@ -1,5 +1,5 @@
 #/** @file\r
-# This driver implements one PCI Express Library instance.\r
+# This module implements one PCI Express Library instance.\r
 #\r
 # PCI Express Library that uses the 256 MB PCI Express MMIO window to perform\r
 #  PCI Configuration cycles. Layers on top of an I/O Library instance.\r

diff --git a/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf b/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
index be28249f3a7de07a566c9d04b8fcb315b9957b58..25b9ff958ee6b62de32fb154ac59c8c026dc8242 100644 (file)
--- a/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+++ b/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
@@ -1,5 +1,5 @@
 #/** @file\r
-# This driver implements one PCI Library instance based on PCI CF8 Library.\r
+# This module implements one PCI Library instance based on PCI CF8 Library.\r
 #\r
 # PCI Library that uses I/O ports 0xCF8 and 0xCFC to perform\r
 #  PCI Configuration cycles. Layers on top of one PCI CF8 Library instance.\r

diff --git a/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf b/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
index c74f680f96e0dcc9901bacf6c246fdb597dc13e0..2f85e9028de2f9f41ad4aec2f89e16919d3b12bc 100644 (file)
--- a/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+++ b/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
@@ -1,5 +1,5 @@
 #/** @file\r
-# This driver impements one PCI Library based on PCI Express Library.\r
+# This module impements one PCI Library based on PCI Express Library.\r
 #\r
 # PCI Library that uses the 256 MB PCI Express MMIO window to perform PCI\r
 #  Configuration cycles. Layers on one PCI Express Library instance.\r