The 'cspell' CI test detected some small typos in ArmPkg.
Correct them.
Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
@param This Instance pointer for this protocol\r
@param Source Hardware source of the interrupt\r
\r
- @retval EFI_SUCCESS Source interrupt EOI'ed.\r
+ @retval EFI_SUCCESS Source interrupt ended successfully.\r
@retval EFI_UNSUPPORTED Source interrupt is not supported\r
\r
**/\r
@param This Instance pointer for this protocol\r
@param Source Hardware source of the interrupt\r
\r
- @retval EFI_SUCCESS Source interrupt EOI'ed.\r
+ @retval EFI_SUCCESS Source interrupt ended successfully.\r
@retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
\r
**/\r
break;\r
\r
case EFI_MEMORY_WC:\r
- // Map to normal non-cachable\r
+ // Map to normal non-cacheable\r
ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
break;\r
\r
};\r
\r
//\r
-// Device path for semi-hosting. It contains our autogened Caller ID GUID.\r
+// Device path for semi-hosting. It contains our auto-generated Caller ID GUID.\r
//\r
typedef struct {\r
VENDOR_DEVICE_PATH Guid;\r
} else if ((Attributes & EFI_MEMORY_WC) != 0) {\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;\r
- // map to normal non-cachable\r
+ // map to normal non-cacheable\r
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
} else if ((Attributes & EFI_MEMORY_WT) != 0) {\r
// modify cacheability attributes\r
} else if ((Attributes & EFI_MEMORY_WC) != 0) {\r
// modify cacheability attributes\r
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;\r
- // map to normal non-cachable\r
+ // map to normal non-cacheable\r
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0\r
} else if ((Attributes & EFI_MEMORY_WT) != 0) {\r
// modify cacheability attributes\r
/**\r
Write data to serial device.\r
\r
- @param Buffer Point of data buffer which need to be writed.\r
+ @param Buffer Point of data buffer which need to be written.\r
@param NumberOfBytes Number of output bytes which are cached in Buffer.\r
\r
@retval 0 Write data failed.\r
- @retval !0 Actual number of bytes writed to serial device.\r
+ @retval !0 Actual number of bytes written to serial device.\r
\r
**/\r
\r
/**\r
Read data from serial device and save the datas in buffer.\r
\r
- @param Buffer Point of data buffer which need to be writed.\r
+ @param Buffer Point of data buffer which need to be written.\r
@param NumberOfBytes Number of output bytes which are cached in Buffer.\r
\r
@retval 0 Read data failed.\r
\r
// Check error response from Callee.\r
if ((*RetVal & BIT31) != 0) {\r
- // Bit 31 set means there is an error retured\r
+ // Bit 31 set means there is an error returned\r
// See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 and\r
// Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64.\r
switch (*RetVal) {\r
/**\r
Get next language from language code list (with separator ';').\r
\r
- @param LangCode Input: point to first language in the list. On\r
- Otput: point to next language in the list, or\r
- NULL if no more language in the list.\r
+ @param LangCode Input: point to first language in the list. On\r
+ Output: point to next language in the list, or\r
+ NULL if no more language in the list.\r
@param Lang The first language in the list.\r
\r
**/\r