]> git.proxmox.com Git - mirror_edk2.git/commitdiff
UefiPayloadPkg: Fix PciHostBridgeLib
authorLean Sheng Tan <sheng.tan@9elements.com>
Wed, 30 Mar 2022 18:29:02 +0000 (11:29 -0700)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Sun, 10 Apr 2022 17:46:10 +0000 (17:46 +0000)
Don't assume a 64bit register always holds an address greater than 4GB.
Check the value in the register and decide which Aperature it should be
assigned to.

Fixes assertion
"ASSERT [PciHostBridgeDxe] Bridge->MemAbove4G.Base >= 0x0000000100000000ULL".

Tested with coreboot as bootloader on platforms that have PCI resource
above 4GiB and on platforms that don't have resource above 4GiB.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Guo Dong <guo.dong@intel.com>
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c

index 8a890b6b53adad0fdde1357d57c7950a7cf92727..e1faa24ae759bb43a5abba3386e3b20c4f96e5de 100644 (file)
@@ -354,14 +354,19 @@ ScanForRootBridges (
           Base  = ((UINT32)Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
           Limit = (((UINT32)Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
                    << 16) | 0xfffff;\r
-          MemAperture = &Mem;\r
+\r
           if (Value == BIT0) {\r
-            Base       |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
-            Limit      |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
-            MemAperture = &MemAbove4G;\r
+            Base  |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
+            Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
           }\r
 \r
           if ((Base > 0) && (Base < Limit)) {\r
+            if (Base < BASE_4GB) {\r
+              MemAperture = &Mem;\r
+            } else {\r
+              MemAperture = &MemAbove4G;\r
+            }\r
+\r
             if (MemAperture->Base > Base) {\r
               MemAperture->Base = Base;\r
             }\r