#include <Library/PciLib.h>\r
#include "PciHostBridge.h"\r
\r
-/**\r
- Adjust the collected PCI resource.\r
-\r
- @param[in] Io IO aperture.\r
-\r
- @param[in] Mem MMIO aperture.\r
-\r
- @param[in] MemAbove4G MMIO aperture above 4G.\r
-\r
- @param[in] PMem Prefetchable MMIO aperture.\r
-\r
- @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
-**/\r
-VOID\r
-AdjustRootBridgeResource (\r
- IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
- IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
- IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
- IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
- IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
- )\r
-{\r
- UINT64 Mask;\r
-\r
- //\r
- // For now try to downgrade everything into MEM32 since\r
- // - coreboot does not assign resource above 4GB\r
- // - coreboot might allocate interleaved MEM32 and PMEM32 resource\r
- // in some cases\r
- //\r
- if (PMem->Base < Mem->Base) {\r
- Mem->Base = PMem->Base;\r
- }\r
-\r
- if (PMem->Limit > Mem->Limit) {\r
- Mem->Limit = PMem->Limit;\r
- }\r
-\r
- PMem->Base = MAX_UINT64;\r
- PMem->Limit = 0;\r
-\r
- if (MemAbove4G->Base < 0x100000000ULL) {\r
- if (MemAbove4G->Base < Mem->Base) {\r
- Mem->Base = MemAbove4G->Base;\r
- }\r
-\r
- if (MemAbove4G->Limit > Mem->Limit) {\r
- Mem->Limit = MemAbove4G->Limit;\r
- }\r
-\r
- MemAbove4G->Base = MAX_UINT64;\r
- MemAbove4G->Limit = 0;\r
- }\r
-\r
- if (PMemAbove4G->Base < 0x100000000ULL) {\r
- if (PMemAbove4G->Base < Mem->Base) {\r
- Mem->Base = PMemAbove4G->Base;\r
- }\r
-\r
- if (PMemAbove4G->Limit > Mem->Limit) {\r
- Mem->Limit = PMemAbove4G->Limit;\r
- }\r
-\r
- PMemAbove4G->Base = MAX_UINT64;\r
- PMemAbove4G->Limit = 0;\r
- }\r
-\r
- //\r
- // Align IO resource at 4K boundary\r
- //\r
- Mask = 0xFFFULL;\r
- Io->Limit = ((Io->Limit + Mask) & ~Mask) - 1;\r
- if (Io->Base != MAX_UINT64) {\r
- Io->Base &= ~Mask;\r
- }\r
-\r
- //\r
- // Align MEM resource at 1MB boundary\r
- //\r
- Mask = 0xFFFFFULL;\r
- Mem->Limit = ((Mem->Limit + Mask) & ~Mask) - 1;\r
- if (Mem->Base != MAX_UINT64) {\r
- Mem->Base &= ~Mask;\r
- }\r
-}\r
-\r
/**\r
Probe a bar is existed or not.\r
\r
STATIC\r
VOID\r
PcatPciRootBridgeBarExisted (\r
- IN UINT64 Address,\r
+ IN UINTN Address,\r
OUT UINT32 *OriginalValue,\r
OUT UINT32 *Value\r
)\r
{\r
- UINTN PciAddress;\r
-\r
- PciAddress = (UINTN)Address;\r
-\r
//\r
// Preserve the original value\r
//\r
- *OriginalValue = PciRead32 (PciAddress);\r
+ *OriginalValue = PciRead32 (Address);\r
\r
//\r
// Disable timer interrupt while the BAR is probed\r
//\r
DisableInterrupts ();\r
\r
- PciWrite32 (PciAddress, 0xFFFFFFFF);\r
- *Value = PciRead32 (PciAddress);\r
- PciWrite32 (PciAddress, *OriginalValue);\r
+ PciWrite32 (Address, 0xFFFFFFFF);\r
+ *Value = PciRead32 (Address);\r
+ PciWrite32 (Address, *OriginalValue);\r
\r
//\r
// Enable interrupt\r
IN UINTN BarOffsetEnd,\r
IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
- IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
- IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
- IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G\r
\r
)\r
{\r
//\r
Length = ((~Length) + 1) & 0xffffffff;\r
\r
- if ((Value & BIT3) == BIT3) {\r
- MemAperture = PMem;\r
- } else {\r
- MemAperture = Mem;\r
- }\r
+ MemAperture = Mem;\r
} else {\r
//\r
// 64bit\r
Length = LShiftU64 (1ULL, LowBit);\r
}\r
\r
- if ((Value & BIT3) == BIT3) {\r
- MemAperture = PMemAbove4G;\r
+ if (Base < BASE_4GB) {\r
+ MemAperture = Mem;\r
} else {\r
MemAperture = MemAbove4G;\r
}\r
}\r
}\r
\r
+STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };\r
+\r
/**\r
Scan for all root bridges in platform.\r
\r
PCI_ROOT_BRIDGE_APERTURE Io;\r
PCI_ROOT_BRIDGE_APERTURE Mem;\r
PCI_ROOT_BRIDGE_APERTURE MemAbove4G;\r
- PCI_ROOT_BRIDGE_APERTURE PMem;\r
- PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;\r
PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r
PCI_ROOT_BRIDGE *RootBridges;\r
UINTN BarOffsetEnd;\r
ZeroMem (&Io, sizeof (Io));\r
ZeroMem (&Mem, sizeof (Mem));\r
ZeroMem (&MemAbove4G, sizeof (MemAbove4G));\r
- ZeroMem (&PMem, sizeof (PMem));\r
- ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));\r
- Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;\r
+ Io.Base = Mem.Base = MemAbove4G.Base = MAX_UINT64;\r
//\r
// Scan all the PCI devices on the primary bus of the PCI root bridge\r
//\r
\r
//\r
// Get the Prefetchable Memory range that the PPB is decoding\r
+ // and merge it into Memory range\r
//\r
Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r
Base = ((UINT32)Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
Limit = (((UINT32)Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
<< 16) | 0xfffff;\r
- MemAperture = &PMem;\r
+ MemAperture = &Mem;\r
if (Value == BIT0) {\r
Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
- MemAperture = &PMemAbove4G;\r
+ MemAperture = &MemAbove4G;\r
}\r
\r
if ((Base > 0) && (Base < Limit)) {\r
BarOffsetEnd,\r
&Io,\r
&Mem,\r
- &MemAbove4G,\r
- &PMem,\r
- &PMemAbove4G\r
+ &MemAbove4G\r
);\r
\r
//\r
);\r
ASSERT (RootBridges != NULL);\r
\r
- AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);\r
-\r
InitRootBridge (\r
Attributes,\r
Attributes,\r
&Io,\r
&Mem,\r
&MemAbove4G,\r
- &PMem,\r
- &PMemAbove4G,\r
+ &mNonExistAperture,\r
+ &mNonExistAperture,\r
&RootBridges[*NumberOfRootBridges]\r
);\r
RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r