UefiCpuPkg/MpInitLib: use BSP to do extended topology check

During AP bringup, just after switching to long mode, APs will do some
cpuid calls to verify that the extended topology leaf (0xB) is available
so they can fetch their x2 APIC IDs from it. In the case of SEV-ES,
these cpuid instructions must be handled by direct use of the GHCB MSR
protocol to fetch the values from the hypervisor, since a #VC handler
is not yet available due to the AP's stack not being set up yet.

For SEV-SNP, rather than relying on the GHCB MSR protocol, it is
expected that these values would be obtained from the SEV-SNP CPUID
table instead. The actual x2 APIC ID (and 8-bit APIC IDs) would still
be fetched from hypervisor using the GHCB MSR protocol however, so
introducing support for the SEV-SNP CPUID table in that part of the AP
bring-up code would only be to handle the checks/validation of the
extended topology leaf.

Rather than introducing all the added complexity needed to handle these
checks via the CPUID table, instead let the BSP do the check in advance,
since it can make use of the #VC handler to avoid the need to scan the
SNP CPUID table directly, and add a flag in ExchangeInfo to communicate
the result of this check to APs.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Ray Ni <ray.ni@intel.com>
Suggested-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Michael Roth <michael.roth@amd.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>

diff --git a/UefiCpuPkg/Library/MpInitLib/AmdSev.c b/UefiCpuPkg/Library/MpInitLib/AmdSev.c
index 0e3c6e2310773bef131ba0eaa3dc8c1da19c6480..b4a344ee6b3363d4c5d20365dabf55f26d0dca15 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/AmdSev.c
+++ b/UefiCpuPkg/Library/MpInitLib/AmdSev.c
@@ -243,3 +243,24 @@ SevEsPlaceApHlt (
 \r
   MpInitLibSevEsAPReset (Ghcb, CpuMpData);\r
 }\r
+\r
+/**\r
+  The function fills the exchange data for the AP.\r
+\r
+  @param[in]   ExchangeInfo  The pointer to CPU Exchange Data structure\r
+**/\r
+VOID\r
+FillExchangeInfoDataSevEs (\r
+  IN volatile MP_CPU_EXCHANGE_INFO  *ExchangeInfo\r
+  )\r
+{\r
+  UINT32  StdRangeMax;\r
+\r
+  AsmCpuid (CPUID_SIGNATURE, &StdRangeMax, NULL, NULL, NULL);\r
+  if (StdRangeMax >= CPUID_EXTENDED_TOPOLOGY) {\r
+    CPUID_EXTENDED_TOPOLOGY_EBX  ExtTopoEbx;\r
+\r
+    AsmCpuid (CPUID_EXTENDED_TOPOLOGY, NULL, &ExtTopoEbx.Uint32, NULL, NULL);\r
+    ExchangeInfo->ExtTopoAvail = !!ExtTopoEbx.Bits.LogicalProcessors;\r
+  }\r
+}\r

diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
index 01668638f245c84983d3fd5ec8a0efd74917bcc3..aba53f57201c93a700fceca193869d602f6a509c 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
+++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
@@ -94,6 +94,7 @@ struc MP_CPU_EXCHANGE_INFO
   .SevEsIsEnabled:               CTYPE_BOOLEAN 1\r
   .SevSnpIsEnabled               CTYPE_BOOLEAN 1\r
   .GhcbBase:                     CTYPE_UINTN 1\r
+  .ExtTopoAvail:                 CTYPE_BOOLEAN 1\r
 endstruc\r
 \r
 MP_CPU_EXCHANGE_INFO_OFFSET equ (SwitchToRealProcEnd - RendezvousFunnelProcStart)\r

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 44a011ba75dea8362ebecc33205257a0f4098367..b73a6e9a0ffc0f49462f956505cecdeb617a92e5 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -900,6 +900,13 @@ FillExchangeInfoData (
   ExchangeInfo->SevSnpIsEnabled = CpuMpData->SevSnpIsEnabled;\r
   ExchangeInfo->GhcbBase        = (UINTN)CpuMpData->GhcbBase;\r
 \r
+  //\r
+  // Populate SEV-ES specific exchange data.\r
+  //\r
+  if (ExchangeInfo->SevSnpIsEnabled) {\r
+    FillExchangeInfoDataSevEs (ExchangeInfo);\r
+  }\r
+\r
   //\r
   // Get the BSP's data of GDT and IDT\r
   //\r

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h
index 56de3bfb1ccf71b4e1140adb76911ccc626f19e8..be67cd88ec46159864f9a59a526e6355df88bb5b 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -224,6 +224,7 @@ typedef struct {
   BOOLEAN            SevEsIsEnabled;\r
   BOOLEAN            SevSnpIsEnabled;\r
   UINTN              GhcbBase;\r
+  BOOLEAN            ExtTopoAvail;\r
 } MP_CPU_EXCHANGE_INFO;\r
 \r
 #pragma pack()\r
@@ -788,4 +789,14 @@ ConfidentialComputingGuestHas (
   CONFIDENTIAL_COMPUTING_GUEST_ATTR  Attr\r
   );\r
 \r
+/**\r
+  The function fills the exchange data for the AP.\r
+\r
+  @param[in]   ExchangeInfo  The pointer to CPU Exchange Data structure\r
+**/\r
+VOID\r
+FillExchangeInfoDataSevEs (\r
+  IN volatile MP_CPU_EXCHANGE_INFO  *ExchangeInfo\r
+  );\r
+\r
 #endif\r

diff --git a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm
index 0034920b2f6b1785e359b95c2e6a5865668b7fc0..8bb1161fa0f77fe4681eaa872e7e8dd844ebf80a 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm
+++ b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm
@@ -118,6 +118,32 @@ SevEsGetApicId:
     or         rax, rdx\r
     mov        rdi, rax             ; RDI now holds the original GHCB GPA\r
 \r
+    ;\r
+    ; For SEV-SNP, the recommended handling for getting the x2APIC ID\r
+    ; would be to use the SNP CPUID table to fetch CPUID.00H:EAX and\r
+    ; CPUID:0BH:EBX[15:0] instead of the GHCB MSR protocol vmgexits\r
+    ; below.\r
+    ;\r
+    ; To avoid the unecessary ugliness to accomplish that here, the BSP\r
+    ; has performed these checks in advance (where #VC handler handles\r
+    ; the CPUID table lookups automatically) and cached them in a flag\r
+    ; so those checks can be skipped here.\r
+    ;\r
+    mov        eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevSnpIsEnabled)]\r
+    cmp        al, 1\r
+    jne        CheckExtTopoAvail\r
+\r
+    ;\r
+    ; Even with SEV-SNP, the actual x2APIC ID in CPUID.0BH:EDX\r
+    ; fetched from the hypervisor the same way SEV-ES does it.\r
+    ;\r
+    mov        eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (ExtTopoAvail)]\r
+    cmp        al, 1\r
+    je         GetApicIdSevEs\r
+    ; The 8-bit APIC ID fallback is also the same as with SEV-ES\r
+    jmp        NoX2ApicSevEs\r
+\r
+CheckExtTopoAvail:\r
     mov        rdx, 0               ; CPUID function 0\r
     mov        rax, 0               ; RAX register requested\r
     or         rax, 4\r
@@ -136,6 +162,7 @@ SevEsGetApicId:
     test       edx, 0ffffh\r
     jz         NoX2ApicSevEs        ; CPUID.0BH:EBX[15:0] is zero\r
 \r
+GetApicIdSevEs:\r
     mov        rdx, 0bh             ; CPUID function 0x0b\r
     mov        rax, 0c0000000h      ; RDX register requested\r
     or         rax, 4\r