in the ARM Namespace\r
*/\r
typedef enum ArmObjectID {\r
- EArmObjReserved, ///< 0 - Reserved\r
- EArmObjBootArchInfo, ///< 1 - Boot Architecture Info\r
- EArmObjCpuInfo, ///< 2 - CPU Info\r
- EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info\r
- EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info\r
- EArmObjGicDInfo, ///< 5 - GIC Distributor Info\r
- EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info\r
- EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info\r
- EArmObjGicItsInfo, ///< 8 - GIC ITS Info\r
- EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info\r
- EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info\r
- EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info\r
- EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info\r
- EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info\r
- EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r
- EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info\r
- EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id\r
- EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT\r
- EArmObjItsGroup, ///< 18 - ITS Group\r
- EArmObjNamedComponent, ///< 19 - Named Component\r
- EArmObjRootComplex, ///< 20 - Root Complex\r
- EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2\r
- EArmObjSmmuV3, ///< 22 - SMMUv3\r
- EArmObjPmcg, ///< 23 - PMCG\r
- EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r
- EArmObjIdMappingArray, ///< 25 - ID Mapping Array\r
- EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r
- EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r
- EArmObjCacheInfo, ///< 28 - Cache Info\r
- EArmObjReserved29, ///< 29 - Reserved\r
- EArmObjCmRef, ///< 30 - CM Object Reference\r
- EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info\r
- EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi\r
- EArmObjDeviceHandlePci, ///< 33 - Device Handle Pci\r
- EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity\r
- EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info\r
- EArmObjCmn600Info, ///< 36 - CMN-600 Info\r
- EArmObjLpiInfo, ///< 37 - Lpi Info\r
- EArmObjPciAddressMapInfo, ///< 38 - Pci Address Map Info\r
- EArmObjPciInterruptMapInfo, ///< 39 - Pci Interrupt Map Info\r
- EArmObjRmr, ///< 40 - Reserved Memory Range Node\r
- EArmObjMemoryRangeDescriptor, ///< 41 - Memory Range Descriptor\r
- EArmObjCpcInfo, ///< 42 - Continuous Performance Control Info\r
+ EArmObjReserved, ///< 0 - Reserved\r
+ EArmObjBootArchInfo, ///< 1 - Boot Architecture Info\r
+ EArmObjCpuInfo, ///< 2 - CPU Info\r
+ EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info\r
+ EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info\r
+ EArmObjGicDInfo, ///< 5 - GIC Distributor Info\r
+ EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info\r
+ EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info\r
+ EArmObjGicItsInfo, ///< 8 - GIC ITS Info\r
+ EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info\r
+ EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info\r
+ EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info\r
+ EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info\r
+ EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info\r
+ EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r
+ EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info\r
+ EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id\r
+ EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT\r
+ EArmObjItsGroup, ///< 18 - ITS Group\r
+ EArmObjNamedComponent, ///< 19 - Named Component\r
+ EArmObjRootComplex, ///< 20 - Root Complex\r
+ EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2\r
+ EArmObjSmmuV3, ///< 22 - SMMUv3\r
+ EArmObjPmcg, ///< 23 - PMCG\r
+ EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r
+ EArmObjIdMappingArray, ///< 25 - ID Mapping Array\r
+ EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r
+ EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r
+ EArmObjCacheInfo, ///< 28 - Cache Info\r
+ EArmObjReserved29, ///< 29 - Reserved\r
+ EArmObjCmRef, ///< 30 - CM Object Reference\r
+ EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info\r
+ EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi\r
+ EArmObjDeviceHandlePci, ///< 33 - Device Handle Pci\r
+ EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity\r
+ EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info\r
+ EArmObjCmn600Info, ///< 36 - CMN-600 Info\r
+ EArmObjLpiInfo, ///< 37 - Lpi Info\r
+ EArmObjPciAddressMapInfo, ///< 38 - Pci Address Map Info\r
+ EArmObjPciInterruptMapInfo, ///< 39 - Pci Interrupt Map Info\r
+ EArmObjRmr, ///< 40 - Reserved Memory Range Node\r
+ EArmObjMemoryRangeDescriptor, ///< 41 - Memory Range Descriptor\r
+ EArmObjCpcInfo, ///< 42 - Continuous Performance Control Info\r
+ EArmObjPccSubspaceType0Info, ///< 43 - Pcc Subspace Type 0 Info\r
+ EArmObjPccSubspaceType1Info, ///< 44 - Pcc Subspace Type 2 Info\r
+ EArmObjPccSubspaceType2Info, ///< 45 - Pcc Subspace Type 2 Info\r
+ EArmObjPccSubspaceType3Info, ///< 46 - Pcc Subspace Type 3 Info\r
+ EArmObjPccSubspaceType4Info, ///< 47 - Pcc Subspace Type 4 Info\r
+ EArmObjPccSubspaceType5Info, ///< 48 - Pcc Subspace Type 5 Info\r
EArmObjMax\r
} EARM_OBJECT_ID;\r
\r
*/\r
typedef AML_CPC_INFO CM_ARM_CPC_INFO;\r
\r
+/** A structure that describes a\r
+ PCC Mailbox Register.\r
+*/\r
+typedef struct PccMailboxRegisterInfo {\r
+ /// GAS describing the Register.\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE Register;\r
+\r
+ /** Mask of bits to preserve when writing.\r
+\r
+ This mask is also used for registers. The Register is only read\r
+ and there is no write mask required. E.g.:\r
+ - Error Status mask (Cf. PCC Subspace types 3/4/5).\r
+ - Command Complete Check mask (Cf. PCC Subspace types 3/4/5).\r
+ */\r
+ UINT64 PreserveMask;\r
+\r
+ /// Mask of bits to set when writing.\r
+ UINT64 WriteMask;\r
+} PCC_MAILBOX_REGISTER_INFO;\r
+\r
+/** A structure that describes the\r
+ PCC Subspace CHannel Timings.\r
+*/\r
+typedef struct PccSubspaceChannelTimingInfo {\r
+ /// Expected latency to process a command, in microseconds.\r
+ UINT32 NominalLatency;\r
+\r
+ /** Maximum number of periodic requests that the subspace channel can\r
+ support, reported in commands per minute. 0 indicates no limitation.\r
+\r
+ This field is ignored for the PCC Subspace type 5 (HW Registers based).\r
+ */\r
+ UINT32 MaxPeriodicAccessRate;\r
+\r
+ /** Minimum amount of time that OSPM must wait after the completion\r
+ of a command before issuing the next command, in microseconds.\r
+ */\r
+ UINT16 MinRequestTurnaroundTime;\r
+} PCC_SUBSPACE_CHANNEL_TIMING_INFO;\r
+\r
+/** A structure that describes a\r
+ Generic PCC Subspace (Type 0).\r
+*/\r
+typedef struct CmArmPccSubspaceGenericInfo {\r
+ /** Subspace Id.\r
+\r
+ Cf. ACPI 6.4, s14.7 Referencing the PCC address space\r
+ Cf. s14.1.2 Platform Communications Channel Subspace Structures\r
+ The subspace ID of a PCC subspace is its index in the array of\r
+ subspace structures, starting with subspace 0.\r
+\r
+ At most 256 subspaces are supported.\r
+ */\r
+ UINT8 SubspaceId;\r
+\r
+ /// Table type (or subspace).\r
+ UINT8 Type;\r
+\r
+ /// Base address of the shared memory range.\r
+ /// This field is ignored for the PCC Subspace type 5 (HW Registers based).\r
+ UINT64 BaseAddress;\r
+\r
+ /// Address length.\r
+ UINT64 AddressLength;\r
+\r
+ /// Doorbell Register.\r
+ PCC_MAILBOX_REGISTER_INFO DoorbellReg;\r
+\r
+ /// Mailbox Timings.\r
+ PCC_SUBSPACE_CHANNEL_TIMING_INFO ChannelTiming;\r
+} PCC_SUBSPACE_GENERIC_INFO;\r
+\r
+/** A structure that describes a\r
+ PCC Subspace of type 0 (Generic).\r
+\r
+ ID: EArmObjPccSubspaceType0Info\r
+*/\r
+typedef PCC_SUBSPACE_GENERIC_INFO CM_ARM_PCC_SUBSPACE_TYPE0_INFO;\r
+\r
+/** A structure that describes a\r
+ PCC Subspace of type 1 (HW-Reduced).\r
+\r
+ ID: EArmObjPccSubspaceType1Info\r
+*/\r
+typedef struct CmArmPccSubspaceType1Info {\r
+ /** Generic Pcc information.\r
+\r
+ The Subspace of Type0 contains information that can be re-used\r
+ in other Subspace types.\r
+ */\r
+ PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;\r
+\r
+ /// Platform Interrupt.\r
+ CM_ARM_GENERIC_INTERRUPT PlatIrq;\r
+} CM_ARM_PCC_SUBSPACE_TYPE1_INFO;\r
+\r
+/** A structure that describes a\r
+ PCC Subspace of type 2 (HW-Reduced).\r
+\r
+ ID: EArmObjPccSubspaceType2Info\r
+*/\r
+typedef struct CmArmPccSubspaceType2Info {\r
+ /** Generic Pcc information.\r
+\r
+ The Subspace of Type0 contains information that can be re-used\r
+ in other Subspace types.\r
+ */\r
+ PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;\r
+\r
+ /// Platform Interrupt.\r
+ CM_ARM_GENERIC_INTERRUPT PlatIrq;\r
+\r
+ /// Platform Interrupt Register.\r
+ PCC_MAILBOX_REGISTER_INFO PlatIrqAckReg;\r
+} CM_ARM_PCC_SUBSPACE_TYPE2_INFO;\r
+\r
+/** A structure that describes a\r
+ PCC Subspace of type 3 (Extended)\r
+\r
+ ID: EArmObjPccSubspaceType3Info\r
+*/\r
+typedef struct CmArmPccSubspaceType3Info {\r
+ /** Generic Pcc information.\r
+\r
+ The Subspace of Type0 contains information that can be re-used\r
+ in other Subspace types.\r
+ */\r
+ PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;\r
+\r
+ /// Platform Interrupt.\r
+ CM_ARM_GENERIC_INTERRUPT PlatIrq;\r
+\r
+ /// Platform Interrupt Register.\r
+ PCC_MAILBOX_REGISTER_INFO PlatIrqAckReg;\r
+\r
+ /// Command Complete Check Register.\r
+ /// The WriteMask field is not used.\r
+ PCC_MAILBOX_REGISTER_INFO CmdCompleteCheckReg;\r
+\r
+ /// Command Complete Update Register.\r
+ PCC_MAILBOX_REGISTER_INFO CmdCompleteUpdateReg;\r
+\r
+ /// Error Status Register.\r
+ /// The WriteMask field is not used.\r
+ PCC_MAILBOX_REGISTER_INFO ErrorStatusReg;\r
+} CM_ARM_PCC_SUBSPACE_TYPE3_INFO;\r
+\r
+/** A structure that describes a\r
+ PCC Subspace of type 4 (Extended)\r
+\r
+ ID: EArmObjPccSubspaceType4Info\r
+*/\r
+typedef CM_ARM_PCC_SUBSPACE_TYPE3_INFO CM_ARM_PCC_SUBSPACE_TYPE4_INFO;\r
+\r
+/** A structure that describes a\r
+ PCC Subspace of type 5 (HW-Registers).\r
+\r
+ ID: EArmObjPccSubspaceType5Info\r
+*/\r
+typedef struct CmArmPccSubspaceType5Info {\r
+ /** Generic Pcc information.\r
+\r
+ The Subspace of Type0 contains information that can be re-used\r
+ in other Subspace types.\r
+\r
+ MaximumPeriodicAccessRate doesn't need to be populated for\r
+ this structure.\r
+ */\r
+ PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;\r
+\r
+ /// Version.\r
+ UINT16 Version;\r
+\r
+ /// Platform Interrupt.\r
+ CM_ARM_GENERIC_INTERRUPT PlatIrq;\r
+\r
+ /// Command Complete Check Register.\r
+ /// The WriteMask field is not used.\r
+ PCC_MAILBOX_REGISTER_INFO CmdCompleteCheckReg;\r
+\r
+ /// Error Status Register.\r
+ /// The WriteMask field is not used.\r
+ PCC_MAILBOX_REGISTER_INFO ErrorStatusReg;\r
+} CM_ARM_PCC_SUBSPACE_TYPE5_INFO;\r
+\r
#pragma pack()\r
\r
#endif // ARM_NAMESPACE_OBJECTS_H_\r
{ "NominalFrequencyInteger", 4, "0x%lx", NULL },\r
};\r
\r
+/** A parser for the PCC_MAILBOX_REGISTER_INFO struct.\r
+*/\r
+STATIC CONST CM_OBJ_PARSER CmArmMailboxRegisterInfoParser[] = {\r
+ { "Register", sizeof (EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE), NULL, NULL,\r
+ AcpiGenericAddressParser, ARRAY_SIZE (AcpiGenericAddressParser) },\r
+ { "PreserveMask", 8, "0x%llx", NULL },\r
+ { "WriteMask", 8, "0x%llx", NULL },\r
+};\r
+\r
+/** A parser for the PCC_SUBSPACE_CHANNEL_TIMING_INFO struct.\r
+*/\r
+STATIC CONST CM_OBJ_PARSER CmArmPccSubspaceChannelTimingInfoParser[] = {\r
+ { "NominalLatency", 4, "0x%x", NULL },\r
+ { "MaxPeriodicAccessRate", 4, "0x%x", NULL },\r
+ { "MinRequestTurnaroundTime", 2, "0x%x", NULL },\r
+};\r
+\r
+/** A parser for EArmObjPccSubspaceType0Info.\r
+*/\r
+STATIC CONST CM_OBJ_PARSER CmArmPccSubspaceType0InfoParser[] = {\r
+ { "SubspaceId", 1, "0x%x", NULL },\r
+ { "Type", 1, "0x%x", NULL },\r
+ { "BaseAddress", 8, "0x%llx", NULL },\r
+ { "AddressLength", 8, "0x%llx", NULL },\r
+ { "DoorbellReg", sizeof (PCC_MAILBOX_REGISTER_INFO),\r
+ NULL, NULL, CmArmMailboxRegisterInfoParser,\r
+ ARRAY_SIZE (CmArmMailboxRegisterInfoParser) },\r
+ { "ChannelTiming", sizeof (PCC_SUBSPACE_CHANNEL_TIMING_INFO),\r
+ NULL, NULL, CmArmPccSubspaceChannelTimingInfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceChannelTimingInfoParser) },\r
+};\r
+\r
+/** A parser for EArmObjPccSubspaceType1Info.\r
+*/\r
+STATIC CONST CM_OBJ_PARSER CmArmPccSubspaceType1InfoParser[] = {\r
+ { "GenericPccInfo", sizeof (PCC_SUBSPACE_GENERIC_INFO),\r
+ NULL, NULL, CmArmPccSubspaceType0InfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceType0InfoParser) },\r
+ { "PlatIrq", sizeof (CM_ARM_GENERIC_INTERRUPT),\r
+ NULL, NULL, CmArmGenericInterruptParser,\r
+ ARRAY_SIZE (CmArmGenericInterruptParser) },\r
+};\r
+\r
+/** A parser for EArmObjPccSubspaceType2Info.\r
+*/\r
+STATIC CONST CM_OBJ_PARSER CmArmPccSubspaceType2InfoParser[] = {\r
+ { "GenericPccInfo", sizeof (PCC_SUBSPACE_GENERIC_INFO),\r
+ NULL, NULL, CmArmPccSubspaceType0InfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceType0InfoParser) },\r
+ { "PlatIrq", sizeof (CM_ARM_GENERIC_INTERRUPT), NULL,NULL,\r
+ CmArmGenericInterruptParser, ARRAY_SIZE (CmArmGenericInterruptParser) },\r
+ { "PlatIrqAckReg", sizeof (PCC_MAILBOX_REGISTER_INFO),\r
+ NULL, NULL, CmArmMailboxRegisterInfoParser,\r
+ ARRAY_SIZE (CmArmMailboxRegisterInfoParser) },\r
+};\r
+\r
+/** A parser for EArmObjPccSubspaceType3Info or EArmObjPccSubspaceType4Info.\r
+*/\r
+STATIC CONST CM_OBJ_PARSER CmArmPccSubspaceType34InfoParser[] = {\r
+ { "GenericPccInfo", sizeof (PCC_SUBSPACE_GENERIC_INFO),\r
+ NULL, NULL, CmArmPccSubspaceType0InfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceType0InfoParser) },\r
+ { "PlatIrq", sizeof (CM_ARM_GENERIC_INTERRUPT), NULL,NULL,\r
+ CmArmGenericInterruptParser, ARRAY_SIZE (CmArmGenericInterruptParser) },\r
+ { "PlatIrqAckReg", sizeof (PCC_MAILBOX_REGISTER_INFO),\r
+ NULL, NULL, CmArmMailboxRegisterInfoParser,\r
+ ARRAY_SIZE (CmArmMailboxRegisterInfoParser) },\r
+ { "CmdCompleteCheckReg", sizeof (PCC_MAILBOX_REGISTER_INFO),\r
+ NULL, NULL, CmArmMailboxRegisterInfoParser,\r
+ ARRAY_SIZE (CmArmMailboxRegisterInfoParser) },\r
+ { "CmdCompleteUpdateReg", sizeof (PCC_MAILBOX_REGISTER_INFO),\r
+ NULL, NULL, CmArmMailboxRegisterInfoParser,\r
+ ARRAY_SIZE (CmArmMailboxRegisterInfoParser) },\r
+ { "ErrorStatusReg", sizeof (PCC_MAILBOX_REGISTER_INFO),\r
+ NULL, NULL, CmArmMailboxRegisterInfoParser,\r
+ ARRAY_SIZE (CmArmMailboxRegisterInfoParser) },\r
+};\r
+\r
+/** A parser for EArmObjPccSubspaceType5Info.\r
+*/\r
+STATIC CONST CM_OBJ_PARSER CmArmPccSubspaceType5InfoParser[] = {\r
+ { "GenericPccInfo", sizeof (PCC_SUBSPACE_GENERIC_INFO),\r
+ NULL, NULL, CmArmPccSubspaceType0InfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceType0InfoParser) },\r
+ { "Version", 2, "0x%x",NULL },\r
+ { "PlatIrq", sizeof (CM_ARM_GENERIC_INTERRUPT), NULL, NULL,\r
+ CmArmGenericInterruptParser, ARRAY_SIZE (CmArmGenericInterruptParser) },\r
+ { "CmdCompleteCheckReg", sizeof (PCC_MAILBOX_REGISTER_INFO),\r
+ NULL, NULL, CmArmMailboxRegisterInfoParser,\r
+ ARRAY_SIZE (CmArmMailboxRegisterInfoParser) },\r
+ { "ErrorStatusReg", sizeof (PCC_MAILBOX_REGISTER_INFO),\r
+ NULL, NULL, CmArmMailboxRegisterInfoParser,\r
+ ARRAY_SIZE (CmArmMailboxRegisterInfoParser) },\r
+};\r
+\r
/** A parser for Arm namespace objects.\r
*/\r
STATIC CONST CM_OBJ_PARSER_ARRAY ArmNamespaceObjectParser[] = {\r
ARRAY_SIZE (CmArmMemoryRangeDescriptorInfoParser) },\r
{ "EArmObjCpcInfo", CmArmCpcInfoParser,\r
ARRAY_SIZE (CmArmCpcInfoParser) },\r
+ { "EArmObjPccSubspaceType0Info", CmArmPccSubspaceType0InfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceType0InfoParser) },\r
+ { "EArmObjPccSubspaceType1Info", CmArmPccSubspaceType1InfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceType1InfoParser) },\r
+ { "EArmObjPccSubspaceType2Info", CmArmPccSubspaceType2InfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceType2InfoParser) },\r
+ { "EArmObjPccSubspaceType3Info", CmArmPccSubspaceType34InfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceType34InfoParser) },\r
+ { "EArmObjPccSubspaceType4Info", CmArmPccSubspaceType34InfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceType34InfoParser) },\r
+ { "EArmObjPccSubspaceType5Info", CmArmPccSubspaceType5InfoParser,\r
+ ARRAY_SIZE (CmArmPccSubspaceType5InfoParser) },\r
{ "EArmObjMax", NULL, 0 },\r
};\r
\r
projects / mirror_edk2.git / commitdiff