MdeModulePkg/XhciDxe: fix a bug on TRB check in async int transfer

The last TRB in transfer ring is a LINK type TRB, which shouldn't
be accounted as a valid item in IsAsyncIntTrb().

Without this fix, the original algo will bring issue on those URBs
whose TRBs crosses the transfer ring.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index 1130b6aac14bdbc6718e6d1f1f05fffc7565e091..b6078b1f0956572ded8dcc36aaf066431c1031be 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -1009,7 +1009,11 @@ IsAsyncIntTrb (
         return TRUE;\r
       }\r
       CheckedTrb++;\r
-      if ((UINTN)CheckedTrb >= ((UINTN) CheckedUrb->Ring->RingSeg0 + sizeof (TRB_TEMPLATE) * CheckedUrb->Ring->TrbNumber)) {\r
+      //\r
+      // If the checked TRB is the link TRB at the end of the transfer ring,\r
+      // recircle it to the head of the ring.\r
+      //\r
+      if (CheckedTrb->Type == TRB_TYPE_LINK) {\r
         CheckedTrb = (TRB_TEMPLATE*) CheckedUrb->Ring->RingSeg0;\r
       }\r
     }\r