--- /dev/null
+/** @file\r
+ CPUID leaf definitions.\r
+\r
+ Provides defines for CPUID leaf indexes. Data structures are provided for\r
+ registers returned by a CPUID leaf that contain one or more bit fields.\r
+ If a register returned is a single 32-bit value, then a data structure is\r
+ not provided for that register.\r
+\r
+ Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r
+\r
+**/\r
+\r
+#ifndef __AMD_CPUID_H__\r
+#define __AMD_CPUID_H__\r
+\r
+/**\r
+CPUID Signature Information\r
+\r
+@param EAX CPUID_SIGNATURE (0x00)\r
+\r
+@retval EAX Returns the highest value the CPUID instruction recognizes for\r
+ returning basic processor information. The value is returned is\r
+ processor specific.\r
+@retval EBX First 4 characters of a vendor identification string.\r
+@retval ECX Last 4 characters of a vendor identification string.\r
+@retval EDX Middle 4 characters of a vendor identification string.\r
+\r
+**/\r
+\r
+///\r
+/// @{ CPUID signature values returned by AMD processors\r
+///\r
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')\r
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')\r
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')\r
+///\r
+/// @}\r
+///\r
+\r
+\r
+/**\r
+ CPUID Extended Processor Signature and Features\r
+\r
+ @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)\r
+\r
+ @retval EAX Extended Family, Model, Stepping Identifiers\r
+ described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.\r
+ @retval EBX Brand Identifier\r
+ described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.\r
+ @retval ECX Extended Feature Identifiers\r
+ described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.\r
+ @retval EDX Extended Feature Identifiers\r
+ described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.\r
+**/\r
+\r
+/**\r
+ CPUID Extended Processor Signature and Features EAX for CPUID leaf\r
+ #CPUID_EXTENDED_CPU_SIG.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Stepping.\r
+ ///\r
+ UINT32 Stepping:4;\r
+ ///\r
+ /// [Bits 7:4] Base Model.\r
+ ///\r
+ UINT32 BaseModel:4;\r
+ ///\r
+ /// [Bits 11:8] Base Family.\r
+ ///\r
+ UINT32 BaseFamily:4;\r
+ ///\r
+ /// [Bit 15:12] Reserved.\r
+ ///\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 19:16] Extended Model.\r
+ ///\r
+ UINT32 ExtModel:4;\r
+ ///\r
+ /// [Bits 27:20] Extended Family.\r
+ ///\r
+ UINT32 ExtFamily:8;\r
+ ///\r
+ /// [Bit 31:28] Reserved.\r
+ ///\r
+ UINT32 Reserved2:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_AMD_EXTENDED_CPU_SIG_EAX;\r
+\r
+/**\r
+ CPUID Extended Processor Signature and Features EBX for CPUID leaf\r
+ #CPUID_EXTENDED_CPU_SIG.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 27:0] Reserved.\r
+ ///\r
+ UINT32 Reserved:28;\r
+ ///\r
+ /// [Bit 31:28] Package Type.\r
+ ///\r
+ UINT32 PkgType:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_AMD_EXTENDED_CPU_SIG_EBX;\r
+\r
+/**\r
+ CPUID Extended Processor Signature and Features ECX for CPUID leaf\r
+ #CPUID_EXTENDED_CPU_SIG.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r
+ ///\r
+ UINT32 LAHF_SAHF:1;\r
+ ///\r
+ /// [Bit 1] Core multi-processing legacy mode.\r
+ ///\r
+ UINT32 CmpLegacy:1;\r
+ ///\r
+ /// [Bit 2] Secure Virtual Mode feature.\r
+ ///\r
+ UINT32 SVM:1;\r
+ ///\r
+ /// [Bit 3] Extended APIC register space.\r
+ ///\r
+ UINT32 ExtApicSpace:1;\r
+ ///\r
+ /// [Bit 4] LOCK MOV CR0 means MOV CR8.\r
+ ///\r
+ UINT32 AltMovCr8:1;\r
+ ///\r
+ /// [Bit 5] LZCNT instruction support.\r
+ ///\r
+ UINT32 LZCNT:1;\r
+ ///\r
+ /// [Bit 6] SSE4A instruction support.\r
+ ///\r
+ UINT32 SSE4A:1;\r
+ ///\r
+ /// [Bit 7] Misaligned SSE Mode.\r
+ ///\r
+ UINT32 MisAlignSse:1;\r
+ ///\r
+ /// [Bit 8] ThreeDNow Prefetch instructions.\r
+ ///\r
+ UINT32 PREFETCHW:1;\r
+ ///\r
+ /// [Bit 9] OS Visible Work-around support.\r
+ ///\r
+ UINT32 OSVW:1;\r
+ ///\r
+ /// [Bit 10] Instruction Based Sampling.\r
+ ///\r
+ UINT32 IBS:1;\r
+ ///\r
+ /// [Bit 11] Extended Operation Support.\r
+ ///\r
+ UINT32 XOP:1;\r
+ ///\r
+ /// [Bit 12] SKINIT and STGI support.\r
+ ///\r
+ UINT32 SKINIT:1;\r
+ ///\r
+ /// [Bit 13] Watchdog Timer support.\r
+ ///\r
+ UINT32 WDT:1;\r
+ ///\r
+ /// [Bit 14] Reserved.\r
+ ///\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 15] Lightweight Profiling support.\r
+ ///\r
+ UINT32 LWP:1;\r
+ ///\r
+ /// [Bit 16] 4-Operand FMA instruction support.\r
+ ///\r
+ UINT32 FMA4:1;\r
+ ///\r
+ /// [Bit 17] Translation Cache Extension.\r
+ ///\r
+ UINT32 TCE:1;\r
+ ///\r
+ /// [Bit 21:18] Reserved.\r
+ ///\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 22] Topology Extensions support.\r
+ ///\r
+ UINT32 TopologyExtensions:1;\r
+ ///\r
+ /// [Bit 23] Core Performance Counter Extensions.\r
+ ///\r
+ UINT32 PerfCtrExtCore:1;\r
+ ///\r
+ /// [Bit 25:24] Reserved.\r
+ ///\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 26] Data Breakpoint Extension.\r
+ ///\r
+ UINT32 DataBreakpointExtension:1;\r
+ ///\r
+ /// [Bit 27] Performance Time-Stamp Counter.\r
+ ///\r
+ UINT32 PerfTsc:1;\r
+ ///\r
+ /// [Bit 28] L3 Performance Counter Extensions.\r
+ ///\r
+ UINT32 PerfCtrExtL3:1;\r
+ ///\r
+ /// [Bit 29] MWAITX and MONITORX capability.\r
+ ///\r
+ UINT32 MwaitExtended:1;\r
+ ///\r
+ /// [Bit 31:30] Reserved.\r
+ ///\r
+ UINT32 Reserved4:2;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_AMD_EXTENDED_CPU_SIG_ECX;\r
+\r
+/**\r
+ CPUID Extended Processor Signature and Features EDX for CPUID leaf\r
+ #CPUID_EXTENDED_CPU_SIG.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] x87 floating point unit on-chip.\r
+ ///\r
+ UINT32 FPU:1;\r
+ ///\r
+ /// [Bit 1] Virtual-mode enhancements.\r
+ ///\r
+ UINT32 VME:1;\r
+ ///\r
+ /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.\r
+ ///\r
+ UINT32 DE:1;\r
+ ///\r
+ /// [Bit 3] Page-size extensions (4 MB pages).\r
+ ///\r
+ UINT32 PSE:1;\r
+ ///\r
+ /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.\r
+ ///\r
+ UINT32 TSC:1;\r
+ ///\r
+ /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.\r
+ ///\r
+ UINT32 MSR:1;\r
+ ///\r
+ /// [Bit 6] Physical-address extensions (PAE).\r
+ ///\r
+ UINT32 PAE:1;\r
+ ///\r
+ /// [Bit 7] Machine check exception, CR4.MCE.\r
+ ///\r
+ UINT32 MCE:1;\r
+ ///\r
+ /// [Bit 8] CMPXCHG8B instruction.\r
+ ///\r
+ UINT32 CMPXCHG8B:1;\r
+ ///\r
+ /// [Bit 9] APIC exists and is enabled.\r
+ ///\r
+ UINT32 APIC:1;\r
+ ///\r
+ /// [Bit 10] Reserved.\r
+ ///\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 11] SYSCALL and SYSRET instructions.\r
+ ///\r
+ UINT32 SYSCALL_SYSRET:1;\r
+ ///\r
+ /// [Bit 12] Memory-type range registers.\r
+ ///\r
+ UINT32 MTRR:1;\r
+ ///\r
+ /// [Bit 13] Page global extension, CR4.PGE.\r
+ ///\r
+ UINT32 PGE:1;\r
+ ///\r
+ /// [Bit 14] Machine check architecture, MCG_CAP.\r
+ ///\r
+ UINT32 MCA:1;\r
+ ///\r
+ /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.\r
+ ///\r
+ UINT32 CMOV:1;\r
+ ///\r
+ /// [Bit 16] Page attribute table.\r
+ ///\r
+ UINT32 PAT:1;\r
+ ///\r
+ /// [Bit 17] Page-size extensions.\r
+ ///\r
+ UINT32 PSE36 : 1;\r
+ ///\r
+ /// [Bit 19:18] Reserved.\r
+ ///\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 20] No-execute page protection.\r
+ ///\r
+ UINT32 NX:1;\r
+ ///\r
+ /// [Bit 21] Reserved.\r
+ ///\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 22] AMD Extensions to MMX instructions.\r
+ ///\r
+ UINT32 MmxExt:1;\r
+ ///\r
+ /// [Bit 23] MMX instructions.\r
+ ///\r
+ UINT32 MMX:1;\r
+ ///\r
+ /// [Bit 24] FXSAVE and FXRSTOR instructions.\r
+ ///\r
+ UINT32 FFSR:1;\r
+ ///\r
+ /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.\r
+ ///\r
+ UINT32 FFXSR:1;\r
+ ///\r
+ /// [Bit 26] 1-GByte large page support.\r
+ ///\r
+ UINT32 Page1GB:1;\r
+ ///\r
+ /// [Bit 27] RDTSCP intructions.\r
+ ///\r
+ UINT32 RDTSCP:1;\r
+ ///\r
+ /// [Bit 28] Reserved.\r
+ ///\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 29] Long Mode.\r
+ ///\r
+ UINT32 LM:1;\r
+ ///\r
+ /// [Bit 30] 3DNow! instructions.\r
+ ///\r
+ UINT32 ThreeDNow:1;\r
+ ///\r
+ /// [Bit 31] AMD Extensions to 3DNow! instructions.\r
+ ///\r
+ UINT32 ThreeDNowExt:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_AMD_EXTENDED_CPU_SIG_EDX;\r
+\r
+\r
+/**\r
+CPUID Linear Physical Address Size\r
+\r
+@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)\r
+\r
+@retval EAX Linear/Physical Address Size described by the type\r
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.\r
+@retval EBX Linear/Physical Address Size described by the type\r
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.\r
+@retval ECX Linear/Physical Address Size described by the type\r
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.\r
+@retval EDX Reserved.\r
+**/\r
+\r
+/**\r
+ CPUID Linear Physical Address Size EAX for CPUID leaf\r
+ #CPUID_VIR_PHY_ADDRESS_SIZE.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Maximum physical byte address size in bits.\r
+ ///\r
+ UINT32 PhysicalAddressBits:8;\r
+ ///\r
+ /// [Bits 15:8] Maximum linear byte address size in bits.\r
+ ///\r
+ UINT32 LinearAddressBits:8;\r
+ ///\r
+ /// [Bits 23:16] Maximum guest physical byte address size in bits.\r
+ ///\r
+ UINT32 GuestPhysAddrSize:8;\r
+ ///\r
+ /// [Bit 31:24] Reserved.\r
+ ///\r
+ UINT32 Reserved:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;\r
+\r
+/**\r
+ CPUID Linear Physical Address Size EBX for CPUID leaf\r
+ #CPUID_VIR_PHY_ADDRESS_SIZE.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 0] Clear Zero Instruction.\r
+ ///\r
+ UINT32 CLZERO:1;\r
+ ///\r
+ /// [Bits 1] Instructions retired count support.\r
+ ///\r
+ UINT32 IRPerf:1;\r
+ ///\r
+ /// [Bits 2] Restore error pointers for XSave instructions.\r
+ ///\r
+ UINT32 XSaveErPtr:1;\r
+ ///\r
+ /// [Bit 31:3] Reserved.\r
+ ///\r
+ UINT32 Reserved:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;\r
+\r
+/**\r
+ CPUID Linear Physical Address Size ECX for CPUID leaf\r
+ #CPUID_VIR_PHY_ADDRESS_SIZE.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Number of threads - 1.\r
+ ///\r
+ UINT32 NC:8;\r
+ ///\r
+ /// [Bit 11:8] Reserved.\r
+ ///\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 15:12] APIC ID size.\r
+ ///\r
+ UINT32 ApicIdCoreIdSize:4;\r
+ ///\r
+ /// [Bits 17:16] Performance time-stamp counter size.\r
+ ///\r
+ UINT32 PerfTscSize:2;\r
+ ///\r
+ /// [Bit 31:18] Reserved.\r
+ ///\r
+ UINT32 Reserved2:14;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;\r
+\r
+\r
+/**\r
+ CPUID AMD Processor Topology\r
+\r
+ @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)\r
+\r
+ @retval EAX Extended APIC ID described by the type\r
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.\r
+ @retval EBX Core Indentifiers described by the type\r
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.\r
+ @retval ECX Node Indentifiers described by the type\r
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.\r
+ @retval EDX Reserved.\r
+**/\r
+#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E\r
+\r
+/**\r
+ CPUID AMD Processor Topology EAX for CPUID leaf\r
+ #CPUID_AMD_PROCESSOR_TOPOLOGY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 31:0] Extended APIC Id.\r
+ ///\r
+ UINT32 ExtendedApicId;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;\r
+\r
+/**\r
+ CPUID AMD Processor Topology EBX for CPUID leaf\r
+ #CPUID_AMD_PROCESSOR_TOPOLOGY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Core Id.\r
+ ///\r
+ UINT32 CoreId:8;\r
+ ///\r
+ /// [Bits 15:8] Threads per core.\r
+ ///\r
+ UINT32 ThreadsPerCore:8;\r
+ ///\r
+ /// [Bit 31:16] Reserved.\r
+ ///\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;\r
+\r
+/**\r
+ CPUID AMD Processor Topology ECX for CPUID leaf\r
+ #CPUID_AMD_PROCESSOR_TOPOLOGY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Node Id.\r
+ ///\r
+ UINT32 NodeId:8;\r
+ ///\r
+ /// [Bits 10:8] Nodes per processor.\r
+ ///\r
+ UINT32 NodesPerProcessor:3;\r
+ ///\r
+ /// [Bit 31:11] Reserved.\r
+ ///\r
+ UINT32 Reserved:21;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;\r
+\r
+\r
+/**\r
+ CPUID Memory Encryption Information\r
+\r
+ @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)\r
+\r
+ @retval EAX Returns the memory encryption feature support status.\r
+ @retval EBX If memory encryption feature is present then return\r
+ the page table bit number used to enable memory encryption support\r
+ and reducing of physical address space in bits.\r
+ @retval ECX Returns number of encrypted guest supported simultaneously.\r
+ @retval EDX Returns minimum SEV enabled and SEV disabled ASID.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);\r
+ @endcode\r
+**/\r
+\r
+#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F\r
+\r
+/**\r
+ CPUID Memory Encryption support information EAX for CPUID leaf\r
+ #CPUID_MEMORY_ENCRYPTION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Secure Memory Encryption (Sme) Support\r
+ ///\r
+ UINT32 SmeBit:1;\r
+\r
+ ///\r
+ /// [Bit 1] Secure Encrypted Virtualization (Sev) Support\r
+ ///\r
+ UINT32 SevBit:1;\r
+\r
+ ///\r
+ /// [Bit 2] Page flush MSR support\r
+ ///\r
+ UINT32 PageFlushMsrBit:1;\r
+\r
+ ///\r
+ /// [Bit 3] Encrypted state support\r
+ ///\r
+ UINT32 SevEsBit:1;\r
+\r
+ ///\r
+ /// [Bit 31:4] Reserved\r
+ ///\r
+ UINT32 ReservedBits:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MEMORY_ENCRYPTION_INFO_EAX;\r
+\r
+/**\r
+ CPUID Memory Encryption support information EBX for CPUID leaf\r
+ #CPUID_MEMORY_ENCRYPTION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 5:0] Page table bit number used to enable memory encryption\r
+ ///\r
+ UINT32 PtePosBits:6;\r
+\r
+ ///\r
+ /// [Bit 11:6] Reduction of system physical address space bits when\r
+ /// memory encryption is enabled\r
+ ///\r
+ UINT32 ReducedPhysBits:5;\r
+\r
+ ///\r
+ /// [Bit 31:12] Reserved\r
+ ///\r
+ UINT32 ReservedBits:21;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MEMORY_ENCRYPTION_INFO_EBX;\r
+\r
+/**\r
+ CPUID Memory Encryption support information ECX for CPUID leaf\r
+ #CPUID_MEMORY_ENCRYPTION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 31:0] Number of encrypted guest supported simultaneously\r
+ ///\r
+ UINT32 NumGuests;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MEMORY_ENCRYPTION_INFO_ECX;\r
+\r
+/**\r
+ CPUID Memory Encryption support information EDX for CPUID leaf\r
+ #CPUID_MEMORY_ENCRYPTION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID\r
+ ///\r
+ UINT32 MinAsid;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MEMORY_ENCRYPTION_INFO_EDX;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r
+\r
+**/\r
+\r
+#ifndef __FAM17_MSR_H__\r
+#define __FAM17_MSR_H__\r
+\r
+/**\r
+ Secure Encrypted Virtualization (SEV) status register\r
+\r
+**/\r
+#define MSR_SEV_STATUS 0xc0010131\r
+\r
+/**\r
+ MSR information returned for #MSR_SEV_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled\r
+ ///\r
+ UINT32 SevBit:1;\r
+\r
+ ///\r
+ /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled\r
+ ///\r
+ UINT32 SevEsBit:1;\r
+\r
+ UINT32 Reserved:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SEV_STATUS_REGISTER;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2017 - 2019, Advanced Micro Devices. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r
+\r
+**/\r
+\r
+#ifndef __AMD_MSR_H__\r
+#define __AMD_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+#include <Register/Amd/Fam17Msr.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Intel Architectural MSR Definitions.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __INTEL_ARCHITECTURAL_MSR_H__\r
+#define __INTEL_ARCHITECTURAL_MSR_H__\r
+\r
+/**\r
+ See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
+\r
+ @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);\r
+ AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.\r
+**/\r
+#define MSR_IA32_P5_MC_ADDR 0x00000000\r
+\r
+\r
+/**\r
+ See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
+\r
+ @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);\r
+ AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);\r
+ @endcode\r
+ @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.\r
+**/\r
+#define MSR_IA32_P5_MC_TYPE 0x00000001\r
+\r
+\r
+/**\r
+ See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced\r
+ at Display Family / Display Model 0F_03H.\r
+\r
+ @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);\r
+ AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.\r
+**/\r
+#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r
+\r
+\r
+/**\r
+ See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /\r
+ Display Model 05_01H.\r
+\r
+ @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);\r
+ AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);\r
+ @endcode\r
+ @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.\r
+**/\r
+#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r
+\r
+\r
+/**\r
+ Platform ID (RO) The operating system can use this MSR to determine "slot"\r
+ information for the processor and the proper microcode update to load.\r
+ Introduced at Display Family / Display Model 06_01H.\r
+\r
+ @param ECX MSR_IA32_PLATFORM_ID (0x00000017)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PLATFORM_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r
+ @endcode\r
+ @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r
+**/\r
+#define MSR_IA32_PLATFORM_ID 0x00000017\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PLATFORM_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:18;\r
+ ///\r
+ /// [Bits 52:50] Platform Id (RO) Contains information concerning the\r
+ /// intended platform for the processor.\r
+ /// 52 51 50\r
+ /// -- -- --\r
+ /// 0 0 0 Processor Flag 0.\r
+ /// 0 0 1 Processor Flag 1\r
+ /// 0 1 0 Processor Flag 2\r
+ /// 0 1 1 Processor Flag 3\r
+ /// 1 0 0 Processor Flag 4\r
+ /// 1 0 1 Processor Flag 5\r
+ /// 1 1 0 Processor Flag 6\r
+ /// 1 1 1 Processor Flag 7\r
+ ///\r
+ UINT32 PlatformId:3;\r
+ UINT32 Reserved3:11;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PLATFORM_ID_REGISTER;\r
+\r
+\r
+/**\r
+ 06_01H.\r
+\r
+ @param ECX MSR_IA32_APIC_BASE (0x0000001B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_APIC_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_APIC_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_APIC_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.\r
+**/\r
+#define MSR_IA32_APIC_BASE 0x0000001B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_APIC_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bit 8] BSP flag (R/W).\r
+ ///\r
+ UINT32 BSP:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display\r
+ /// Model 06_1AH.\r
+ ///\r
+ UINT32 EXTD:1;\r
+ ///\r
+ /// [Bit 11] APIC Global Enable (R/W).\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bits 31:12] APIC Base (R/W).\r
+ ///\r
+ UINT32 ApicBase:20;\r
+ ///\r
+ /// [Bits 63:32] APIC Base (R/W).\r
+ ///\r
+ UINT32 ApicBaseHi:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_APIC_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Control Features in Intel 64 Processor (R/W). If any one enumeration\r
+ condition for defined bit field holds.\r
+\r
+ @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_IA32_FEATURE_CONTROL 0x0000003A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from\r
+ /// being written, writes to this bit will result in GP(0). Note: Once the\r
+ /// Lock bit is set, the contents of this register cannot be modified.\r
+ /// Therefore the lock bit must be set after configuring support for Intel\r
+ /// Virtualization Technology and prior to transferring control to an\r
+ /// option ROM or the OS. Hence, once the Lock bit is set, the entire\r
+ /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD\r
+ /// is not deasserted. If any one enumeration condition for defined bit\r
+ /// field position greater than bit 0 holds.\r
+ ///\r
+ UINT32 Lock:1;\r
+ ///\r
+ /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a\r
+ /// system executive to use VMX in conjunction with SMX to support\r
+ /// Intel(R) Trusted Execution Technology. BIOS must set this bit only\r
+ /// when the CPUID function 1 returns VMX feature flag and SMX feature\r
+ /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&\r
+ /// CPUID.01H:ECX[6] = 1.\r
+ ///\r
+ UINT32 EnableVmxInsideSmx:1;\r
+ ///\r
+ /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX\r
+ /// for system executive that do not require SMX. BIOS must set this bit\r
+ /// only when the CPUID function 1 returns VMX feature flag set (ECX bit\r
+ /// 5). If CPUID.01H:ECX[5] = 1.\r
+ ///\r
+ UINT32 EnableVmxOutsideSmx:1;\r
+ UINT32 Reserved1:5;\r
+ ///\r
+ /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit\r
+ /// in the field represents an enable control for a corresponding SENTER\r
+ /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If\r
+ /// CPUID.01H:ECX[6] = 1.\r
+ ///\r
+ UINT32 SenterLocalFunctionEnables:7;\r
+ ///\r
+ /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable\r
+ /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit\r
+ /// 6] is set. If CPUID.01H:ECX[6] = 1.\r
+ ///\r
+ UINT32 SenterGlobalEnable:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r
+ /// enable runtime reconfiguration of SGX Launch Control via\r
+ /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r
+ ///\r
+ UINT32 SgxLaunchControlEnable:1;\r
+ ///\r
+ /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r
+ /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
+ ///\r
+ UINT32 SgxEnable:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 20] LMCE On (R/WL): When set, system software can program the\r
+ /// MSRs associated with LMCE to configure delivery of some machine check\r
+ /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.\r
+ ///\r
+ UINT32 LmceOn:1;\r
+ UINT32 Reserved4:11;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,\r
+ ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for\r
+ a logical processor. Reset value is Zero. A write to IA32_TSC will modify\r
+ the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does\r
+ not affect the internal invariant TSC hardware.\r
+\r
+ @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);\r
+ AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);\r
+ @endcode\r
+ @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.\r
+**/\r
+#define MSR_IA32_TSC_ADJUST 0x0000003B\r
+\r
+\r
+/**\r
+ BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a\r
+ microcode update to be loaded into the processor. See Section 9.11.6,\r
+ "Microcode Update Loader." A processor may prevent writing to this MSR when\r
+ loading guest states on VM entries or saving guest states on VM exits.\r
+ Introduced at Display Family / Display Model 06_01H.\r
+\r
+ @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = 0;\r
+ AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);\r
+ @endcode\r
+ @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.\r
+**/\r
+#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r
+\r
+\r
+/**\r
+ BIOS Update Signature (RO) Returns the microcode update signature following\r
+ the execution of CPUID.01H. A processor may prevent writing to this MSR when\r
+ loading guest states on VM entries or saving guest states on VM exits.\r
+ Introduced at Display Family / Display Model 06_01H.\r
+\r
+ @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r
+ @endcode\r
+ @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.\r
+**/\r
+#define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved:32;\r
+ ///\r
+ /// [Bits 63:32] Microcode update signature. This field contains the\r
+ /// signature of the currently loaded microcode update when read following\r
+ /// the execution of the CPUID instruction, function 1. It is required\r
+ /// that this register field be pre-loaded with zero prior to executing\r
+ /// the CPUID, function 1. If the field remains equal to zero, then there\r
+ /// is no microcode update loaded. Another nonzero value will be the\r
+ /// signature.\r
+ ///\r
+ UINT32 MicrocodeUpdateSignature:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_BIOS_SIGN_ID_REGISTER;\r
+\r
+\r
+/**\r
+ IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r
+ SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r
+ default value is the digest of Intel's signing key. Read permitted If\r
+ CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):\r
+ EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.\r
+\r
+ @param ECX MSR_IA32_SGXLEPUBKEYHASHn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);\r
+ AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);\r
+ @endcode\r
+ @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.\r
+ MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r
+#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r
+#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r
+#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r
+/// @}\r
+\r
+\r
+/**\r
+ SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r
+ 1.\r
+\r
+ @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r
+ AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.\r
+**/\r
+#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this\r
+ /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment\r
+ /// (see Section 34.15.6), the dual-monitor treatment cannot be activated\r
+ /// if the bit is 0. This bit is cleared when the logical processor is\r
+ /// reset.\r
+ ///\r
+ UINT32 Valid:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If\r
+ /// IA32_VMX_MISC[28].\r
+ ///\r
+ UINT32 BlockSmi:1;\r
+ UINT32 Reserved2:9;\r
+ ///\r
+ /// [Bits 31:12] MSEG Base (R/W).\r
+ ///\r
+ UINT32 MsegBase:20;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r
+\r
+/**\r
+ MSEG header that is located at the physical address specified by the MsegBase\r
+ field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
+**/\r
+typedef struct {\r
+ ///\r
+ /// Different processors may use different MSEG revision identifiers. These\r
+ /// identifiers enable software to avoid using an MSEG header formatted for\r
+ /// one processor on a processor that uses a different format. Software can\r
+ /// discover the MSEG revision identifier that a processor uses by reading\r
+ /// the VMX capability MSR IA32_VMX_MISC.\r
+ //\r
+ UINT32 MsegHeaderRevision;\r
+ ///\r
+ /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r
+ /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r
+ /// processor will be in IA-32e mode after the STM is activated.\r
+ ///\r
+ UINT32 MonitorFeatures;\r
+ UINT32 GdtrLimit;\r
+ UINT32 GdtrBaseOffset;\r
+ UINT32 CsSelector;\r
+ UINT32 EipOffset;\r
+ UINT32 EspOffset;\r
+ UINT32 Cr3Offset;\r
+ ///\r
+ /// Pad header so total size is 2KB\r
+ ///\r
+ UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
+} MSEG_HEADER;\r
+\r
+///\r
+/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r
+///\r
+#define STM_FEATURES_IA32E 0x1\r
+///\r
+/// @}\r
+///\r
+\r
+/**\r
+ Base address of the logical processor's SMRAM image (RO, SMM only). If\r
+ IA32_VMX_MISC[15].\r
+\r
+ @param ECX MSR_IA32_SMBASE (0x0000009E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_SMBASE);\r
+ @endcode\r
+ @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.\r
+**/\r
+#define MSR_IA32_SMBASE 0x0000009E\r
+\r
+\r
+/**\r
+ General Performance Counters (R/W).\r
+ MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.\r
+\r
+ @param ECX MSR_IA32_PMCn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_PMC0);\r
+ AsmWriteMsr64 (MSR_IA32_PMC0, Msr);\r
+ @endcode\r
+ @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.\r
+ MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.\r
+ MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.\r
+ MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.\r
+ MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.\r
+ MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.\r
+ MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.\r
+ MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_PMC0 0x000000C1\r
+#define MSR_IA32_PMC1 0x000000C2\r
+#define MSR_IA32_PMC2 0x000000C3\r
+#define MSR_IA32_PMC3 0x000000C4\r
+#define MSR_IA32_PMC4 0x000000C5\r
+#define MSR_IA32_PMC5 0x000000C6\r
+#define MSR_IA32_PMC6 0x000000C7\r
+#define MSR_IA32_PMC7 0x000000C8\r
+/// @}\r
+\r
+\r
+/**\r
+ TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.\r
+ C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative\r
+ to TSC freq.) when the logical processor is in C0. Cleared upon overflow /\r
+ wrap-around of IA32_APERF.\r
+\r
+ @param ECX MSR_IA32_MPERF (0x000000E7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MPERF);\r
+ AsmWriteMsr64 (MSR_IA32_MPERF, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.\r
+**/\r
+#define MSR_IA32_MPERF 0x000000E7\r
+\r
+\r
+/**\r
+ Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =\r
+ 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at\r
+ the coordinated clock frequency, when the logical processor is in C0.\r
+ Cleared upon overflow / wrap-around of IA32_MPERF.\r
+\r
+ @param ECX MSR_IA32_APERF (0x000000E8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_APERF);\r
+ AsmWriteMsr64 (MSR_IA32_APERF, Msr);\r
+ @endcode\r
+ @note MSR_IA32_APERF is defined as IA32_APERF in SDM.\r
+**/\r
+#define MSR_IA32_APERF 0x000000E8\r
+\r
+\r
+/**\r
+ MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".\r
+ Introduced at Display Family / Display Model 06_01H.\r
+\r
+ @param ECX MSR_IA32_MTRRCAP (0x000000FE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MTRRCAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MTRRCAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_MTRRCAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
+ @endcode\r
+ @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.\r
+**/\r
+#define MSR_IA32_MTRRCAP 0x000000FE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_MTRRCAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] VCNT: The number of variable memory type ranges in the\r
+ /// processor.\r
+ ///\r
+ UINT32 VCNT:8;\r
+ ///\r
+ /// [Bit 8] Fixed range MTRRs are supported when set.\r
+ ///\r
+ UINT32 FIX:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 10] WC Supported when set.\r
+ ///\r
+ UINT32 WC:1;\r
+ ///\r
+ /// [Bit 11] SMRR Supported when set.\r
+ ///\r
+ UINT32 SMRR:1;\r
+ UINT32 Reserved2:20;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_MTRRCAP_REGISTER;\r
+\r
+\r
+/**\r
+ SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
+\r
+ @param ECX MSR_IA32_SYSENTER_CS (0x00000174)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_SYSENTER_CS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);\r
+ AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.\r
+**/\r
+#define MSR_IA32_SYSENTER_CS 0x00000174\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_SYSENTER_CS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] CS Selector.\r
+ ///\r
+ UINT32 CS:16;\r
+ UINT32 Reserved1:16;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_SYSENTER_CS_REGISTER;\r
+\r
+\r
+/**\r
+ SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
+\r
+ @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);\r
+ AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);\r
+ @endcode\r
+ @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.\r
+**/\r
+#define MSR_IA32_SYSENTER_ESP 0x00000175\r
+\r
+\r
+/**\r
+ SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
+\r
+ @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);\r
+ AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);\r
+ @endcode\r
+ @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.\r
+**/\r
+#define MSR_IA32_SYSENTER_EIP 0x00000176\r
+\r
+\r
+/**\r
+ Global Machine Check Capability (RO). Introduced at Display Family / Display\r
+ Model 06_01H.\r
+\r
+ @param ECX MSR_IA32_MCG_CAP (0x00000179)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MCG_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MCG_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_MCG_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
+ @endcode\r
+ @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
+**/\r
+#define MSR_IA32_MCG_CAP 0x00000179\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_MCG_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Count: Number of reporting banks.\r
+ ///\r
+ UINT32 Count:8;\r
+ ///\r
+ /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.\r
+ ///\r
+ UINT32 MCG_CTL_P:1;\r
+ ///\r
+ /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present\r
+ /// if this bit is set.\r
+ ///\r
+ UINT32 MCG_EXT_P:1;\r
+ ///\r
+ /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.\r
+ /// Introduced at Display Family / Display Model 06_01H.\r
+ ///\r
+ UINT32 MCP_CMCI_P:1;\r
+ ///\r
+ /// [Bit 11] MCG_TES_P: Threshold-based error status register are present\r
+ /// if this bit is set.\r
+ ///\r
+ UINT32 MCG_TES_P:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state\r
+ /// registers present.\r
+ ///\r
+ UINT32 MCG_EXT_CNT:8;\r
+ ///\r
+ /// [Bit 24] MCG_SER_P: The processor supports software error recovery if\r
+ /// this bit is set.\r
+ ///\r
+ UINT32 MCG_SER_P:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform\r
+ /// firmware to be invoked when an error is detected so that it may\r
+ /// provide additional platform specific information in an ACPI format\r
+ /// "Generic Error Data Entry" that augments the data included in machine\r
+ /// check bank registers. Introduced at Display Family / Display Model\r
+ /// 06_3EH.\r
+ ///\r
+ UINT32 MCG_ELOG_P:1;\r
+ ///\r
+ /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended\r
+ /// state in IA32_MCG_STATUS and associated MSR necessary to configure\r
+ /// Local Machine Check Exception (LMCE). Introduced at Display Family /\r
+ /// Display Model 06_3EH.\r
+ ///\r
+ UINT32 MCG_LMCE_P:1;\r
+ UINT32 Reserved3:4;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_MCG_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ Global Machine Check Status (R/W0). Introduced at Display Family / Display\r
+ Model 06_01H.\r
+\r
+ @param ECX MSR_IA32_MCG_STATUS (0x0000017A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_MCG_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r
+ AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.\r
+**/\r
+#define MSR_IA32_MCG_STATUS 0x0000017A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_MCG_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display\r
+ /// Model 06_01H.\r
+ ///\r
+ UINT32 RIPV:1;\r
+ ///\r
+ /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display\r
+ /// Model 06_01H.\r
+ ///\r
+ UINT32 EIPV:1;\r
+ ///\r
+ /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family\r
+ /// / Display Model 06_01H.\r
+ ///\r
+ UINT32 MCIP:1;\r
+ ///\r
+ /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.\r
+ ///\r
+ UINT32 LMCE_S:1;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_MCG_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.\r
+\r
+ @param ECX MSR_IA32_MCG_CTL (0x0000017B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);\r
+ AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.\r
+**/\r
+#define MSR_IA32_MCG_CTL 0x0000017B\r
+\r
+\r
+/**\r
+ Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.\r
+\r
+ @param ECX MSR_IA32_PERFEVTSELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PERFEVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r
+ MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r
+ MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r
+ MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_PERFEVTSEL0 0x00000186\r
+#define MSR_IA32_PERFEVTSEL1 0x00000187\r
+#define MSR_IA32_PERFEVTSEL2 0x00000188\r
+#define MSR_IA32_PERFEVTSEL3 0x00000189\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to\r
+ #MSR_IA32_PERFEVTSEL3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
+ ///\r
+ UINT32 EventSelect:8;\r
+ ///\r
+ /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
+ /// detect on the selected event logic.\r
+ ///\r
+ UINT32 UMASK:8;\r
+ ///\r
+ /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
+ ///\r
+ UINT32 USR:1;\r
+ ///\r
+ /// [Bit 17] OS: Counts while in privilege level is ring 0.\r
+ ///\r
+ UINT32 OS:1;\r
+ ///\r
+ /// [Bit 18] Edge: Enables edge detection if set.\r
+ ///\r
+ UINT32 E:1;\r
+ ///\r
+ /// [Bit 19] PC: enables pin control.\r
+ ///\r
+ UINT32 PC:1;\r
+ ///\r
+ /// [Bit 20] INT: enables interrupt on counter overflow.\r
+ ///\r
+ UINT32 INT:1;\r
+ ///\r
+ /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
+ /// event conditions occurring across all logical processors sharing a\r
+ /// processor core. When set to 0, the counter only increments the\r
+ /// associated event conditions occurring in the logical processor which\r
+ /// programmed the MSR.\r
+ ///\r
+ UINT32 ANY:1;\r
+ ///\r
+ /// [Bit 22] EN: enables the corresponding performance counter to commence\r
+ /// counting when this bit is set.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bit 23] INV: invert the CMASK.\r
+ ///\r
+ UINT32 INV:1;\r
+ ///\r
+ /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
+ /// performance counter increments each cycle if the event count is\r
+ /// greater than or equal to the CMASK.\r
+ ///\r
+ UINT32 CMASK:8;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PERFEVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+ Current performance state(P-State) operating point (RO). Introduced at\r
+ Display Family / Display Model 0F_03H.\r
+\r
+ @param ECX MSR_IA32_PERF_STATUS (0x00000198)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PERF_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_IA32_PERF_STATUS 0x00000198\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PERF_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Current performance State Value.\r
+ ///\r
+ UINT32 State:16;\r
+ UINT32 Reserved1:16;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PERF_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ (R/W). Introduced at Display Family / Display Model 0F_03H.\r
+\r
+ @param ECX MSR_IA32_PERF_CTL (0x00000199)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PERF_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);\r
+ AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.\r
+**/\r
+#define MSR_IA32_PERF_CTL 0x00000199\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PERF_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Target performance State Value.\r
+ ///\r
+ UINT32 TargetState:16;\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH\r
+ /// (Mobile only).\r
+ ///\r
+ UINT32 IDA:1;\r
+ UINT32 Reserved2:31;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PERF_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r
+ Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r
+\r
+ @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_CLOCK_MODULATION_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r
+ AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
+**/\r
+#define MSR_IA32_CLOCK_MODULATION 0x0000019A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If\r
+ /// CPUID.06H:EAX[5] = 1.\r
+ ///\r
+ UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r
+ ///\r
+ /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r
+ /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 OnDemandClockModulationDutyCycle:3;\r
+ ///\r
+ /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r
+ /// If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 OnDemandClockModulationEnable:1;\r
+ UINT32 Reserved1:27;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_CLOCK_MODULATION_REGISTER;\r
+\r
+\r
+/**\r
+ Thermal Interrupt Control (R/W) Enables and disables the generation of an\r
+ interrupt on temperature transitions detected with the processor's thermal\r
+ sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r
+ If CPUID.01H:EDX[22] = 1\r
+\r
+ @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_THERM_INTERRUPT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);\r
+ AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.\r
+**/\r
+#define MSR_IA32_THERM_INTERRUPT 0x0000019B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 HighTempEnable:1;\r
+ ///\r
+ /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 LowTempEnable:1;\r
+ ///\r
+ /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 PROCHOT_Enable:1;\r
+ ///\r
+ /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 FORCEPR_Enable:1;\r
+ ///\r
+ /// [Bit 4] Critical Temperature Interrupt Enable.\r
+ /// If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 CriticalTempEnable:1;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 Threshold1:7;\r
+ ///\r
+ /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 Threshold1Enable:1;\r
+ ///\r
+ /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 Threshold2:7;\r
+ ///\r
+ /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 Threshold2Enable:1;\r
+ ///\r
+ /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.\r
+ ///\r
+ UINT32 PowerLimitNotificationEnable:1;\r
+ UINT32 Reserved2:7;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_THERM_INTERRUPT_REGISTER;\r
+\r
+\r
+/**\r
+ Thermal Status Information (RO) Contains status information about the\r
+ processor's thermal sensor and automatic thermal monitoring facilities. See\r
+ Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.\r
+\r
+ @param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_THERM_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);\r
+ @endcode\r
+ @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.\r
+**/\r
+#define MSR_IA32_THERM_STATUS 0x0000019C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_THERM_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 ThermalStatusLog:1;\r
+ ///\r
+ /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 PROCHOT_FORCEPR_Event:1;\r
+ ///\r
+ /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 PROCHOT_FORCEPR_Log:1;\r
+ ///\r
+ /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 CriticalTempStatus:1;\r
+ ///\r
+ /// [Bit 5] Critical Temperature Status log (R/WC0).\r
+ /// If CPUID.01H:EDX[22] = 1.\r
+ ///\r
+ UINT32 CriticalTempStatusLog:1;\r
+ ///\r
+ /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.\r
+ ///\r
+ UINT32 ThermalThreshold1Status:1;\r
+ ///\r
+ /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r
+ ///\r
+ UINT32 ThermalThreshold1Log:1;\r
+ ///\r
+ /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.\r
+ ///\r
+ UINT32 ThermalThreshold2Status:1;\r
+ ///\r
+ /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r
+ ///\r
+ UINT32 ThermalThreshold2Log:1;\r
+ ///\r
+ /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.\r
+ ///\r
+ UINT32 PowerLimitStatus:1;\r
+ ///\r
+ /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.\r
+ ///\r
+ UINT32 PowerLimitLog:1;\r
+ ///\r
+ /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r
+ ///\r
+ UINT32 CurrentLimitStatus:1;\r
+ ///\r
+ /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r
+ ///\r
+ UINT32 CurrentLimitLog:1;\r
+ ///\r
+ /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r
+ ///\r
+ UINT32 CrossDomainLimitStatus:1;\r
+ ///\r
+ /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r
+ ///\r
+ UINT32 CrossDomainLimitLog:1;\r
+ ///\r
+ /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.\r
+ ///\r
+ UINT32 DigitalReadout:7;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =\r
+ /// 1.\r
+ ///\r
+ UINT32 ResolutionInDegreesCelsius:4;\r
+ ///\r
+ /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.\r
+ ///\r
+ UINT32 ReadingValid:1;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_THERM_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for\r
+ /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings\r
+ /// are disabled. Introduced at Display Family / Display Model 0F_0H.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
+ /// this bit enables the thermal control circuit (TCC) portion of the\r
+ /// Intel Thermal Monitor feature. This allows the processor to\r
+ /// automatically reduce power consumption in response to TCC activation.\r
+ /// 0 = Disabled. Note: In some products clearing this bit might be\r
+ /// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r
+ /// thermal throttling will still be activated. The default value of this\r
+ /// field varies with product. See respective tables where default value is\r
+ /// listed. Introduced at Display Family / Display Model 0F_0H.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
+ /// monitoring enabled 0 = Performance monitoring disabled. Introduced at\r
+ /// Display Family / Display Model 0F_0H.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't\r
+ /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at\r
+ /// Display Family / Display Model 0F_0H.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
+ /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r
+ /// Family / Display Model 06_0FH.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved4:3;\r
+ ///\r
+ /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced\r
+ /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep\r
+ /// Technology enabled. If CPUID.01H: ECX[7] =1.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the\r
+ /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This\r
+ /// indicates that MONITOR/MWAIT are not supported. Software attempts to\r
+ /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit\r
+ /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit\r
+ /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit\r
+ /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it\r
+ /// in the default state. Writing this bit when the SSE3 feature flag is\r
+ /// set to 0 may generate a #GP exception. Introduced at Display Family /\r
+ /// Display Model 0F_03H.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ UINT32 Reserved6:3;\r
+ ///\r
+ /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r
+ /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r
+ /// question that allows users to specify when the installed OS does not\r
+ /// support CPUID functions greater than 2. Before setting this bit, BIOS\r
+ /// must execute the CPUID.0H and examine the maximum value returned in\r
+ /// EAX[7:0]. If the maximum value is greater than 2, this bit is\r
+ /// supported. Otherwise, this bit is not supported. Setting this bit when\r
+ /// the maximum value is not greater than 2 may generate a #GP exception.\r
+ /// Setting this bit may cause unexpected behavior in software that\r
+ /// depends on the availability of CPUID leaves greater than 2. Introduced\r
+ /// at Display Family / Display Model 0F_03H.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
+ /// disabled. xTPR messages are optional messages that allow the processor\r
+ /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved7:8;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit\r
+ /// feature (XD Bit) is disabled and the XD Bit extended feature flag will\r
+ /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the\r
+ /// Execute Disable Bit feature (if available) allows the OS to enable PAE\r
+ /// paging and take advantage of data only pages. BIOS must not alter the\r
+ /// contents of this bit location, if XD bit is not supported. Writing\r
+ /// this bit to 1 when the XD Bit extended feature flag is set to 0 may\r
+ /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved9:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.\r
+\r
+ @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);\r
+ AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
+**/\r
+#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest\r
+ /// performance. 15 indicates preference to maximize energy saving.\r
+ ///\r
+ UINT32 PowerPolicyPreference:4;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;\r
+\r
+\r
+/**\r
+ Package Thermal Status Information (RO) Contains status information about\r
+ the package's thermal sensor. See Section 14.8, "Package Level Thermal\r
+ Management.". If CPUID.06H: EAX[6] = 1.\r
+\r
+ @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);\r
+ @endcode\r
+ @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.\r
+**/\r
+#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Pkg Thermal Status (RO):.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ ///\r
+ /// [Bit 1] Pkg Thermal Status Log (R/W):.\r
+ ///\r
+ UINT32 ThermalStatusLog:1;\r
+ ///\r
+ /// [Bit 2] Pkg PROCHOT # event (RO).\r
+ ///\r
+ UINT32 PROCHOT_Event:1;\r
+ ///\r
+ /// [Bit 3] Pkg PROCHOT # log (R/WC0).\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 4] Pkg Critical Temperature Status (RO).\r
+ ///\r
+ UINT32 CriticalTempStatus:1;\r
+ ///\r
+ /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).\r
+ ///\r
+ UINT32 CriticalTempStatusLog:1;\r
+ ///\r
+ /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).\r
+ ///\r
+ UINT32 ThermalThreshold1Status:1;\r
+ ///\r
+ /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).\r
+ ///\r
+ UINT32 ThermalThreshold1Log:1;\r
+ ///\r
+ /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).\r
+ ///\r
+ UINT32 ThermalThreshold2Status:1;\r
+ ///\r
+ /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).\r
+ ///\r
+ UINT32 ThermalThreshold2Log:1;\r
+ ///\r
+ /// [Bit 10] Pkg Power Limitation Status (RO).\r
+ ///\r
+ UINT32 PowerLimitStatus:1;\r
+ ///\r
+ /// [Bit 11] Pkg Power Limitation log (R/WC0).\r
+ ///\r
+ UINT32 PowerLimitLog:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 22:16] Pkg Digital Readout (RO).\r
+ ///\r
+ UINT32 DigitalReadout:7;\r
+ UINT32 Reserved2:9;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of\r
+ an interrupt on temperature transitions detected with the package's thermal\r
+ sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:\r
+ EAX[6] = 1.\r
+\r
+ @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);\r
+ AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.\r
+**/\r
+#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Pkg High-Temperature Interrupt Enable.\r
+ ///\r
+ UINT32 HighTempEnable:1;\r
+ ///\r
+ /// [Bit 1] Pkg Low-Temperature Interrupt Enable.\r
+ ///\r
+ UINT32 LowTempEnable:1;\r
+ ///\r
+ /// [Bit 2] Pkg PROCHOT# Interrupt Enable.\r
+ ///\r
+ UINT32 PROCHOT_Enable:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 4] Pkg Overheat Interrupt Enable.\r
+ ///\r
+ UINT32 OverheatEnable:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 14:8] Pkg Threshold #1 Value.\r
+ ///\r
+ UINT32 Threshold1:7;\r
+ ///\r
+ /// [Bit 15] Pkg Threshold #1 Interrupt Enable.\r
+ ///\r
+ UINT32 Threshold1Enable:1;\r
+ ///\r
+ /// [Bits 22:16] Pkg Threshold #2 Value.\r
+ ///\r
+ UINT32 Threshold2:7;\r
+ ///\r
+ /// [Bit 23] Pkg Threshold #2 Interrupt Enable.\r
+ ///\r
+ UINT32 Threshold2Enable:1;\r
+ ///\r
+ /// [Bit 24] Pkg Power Limit Notification Enable.\r
+ ///\r
+ UINT32 PowerLimitNotificationEnable:1;\r
+ UINT32 Reserved3:7;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;\r
+\r
+\r
+/**\r
+ Trace/Profile Resource Control (R/W). Introduced at Display Family / Display\r
+ Model 06_0EH.\r
+\r
+ @param ECX MSR_IA32_DEBUGCTL (0x000001D9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_DEBUGCTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);\r
+ AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.\r
+**/\r
+#define MSR_IA32_DEBUGCTL 0x000001D9\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_DEBUGCTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a\r
+ /// running trace of the most recent branches taken by the processor in\r
+ /// the LBR stack. Introduced at Display Family / Display Model 06_01H.\r
+ ///\r
+ UINT32 LBR:1;\r
+ ///\r
+ /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat\r
+ /// EFLAGS.TF as single-step on branches instead of single-step on\r
+ /// instructions. Introduced at Display Family / Display Model 06_01H.\r
+ ///\r
+ UINT32 BTF:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be\r
+ /// sent. Introduced at Display Family / Display Model 06_0EH.\r
+ ///\r
+ UINT32 TR:1;\r
+ ///\r
+ /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to\r
+ /// be logged in a BTS buffer. Introduced at Display Family / Display\r
+ /// Model 06_0EH.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular\r
+ /// fashion. When this bit is set, an interrupt is generated by the BTS\r
+ /// facility when the BTS buffer is full. Introduced at Display Family /\r
+ /// Display Model 06_0EH.\r
+ ///\r
+ UINT32 BTINT:1;\r
+ ///\r
+ /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.\r
+ /// Introduced at Display Family / Display Model 06_0FH.\r
+ ///\r
+ UINT32 BTS_OFF_OS:1;\r
+ ///\r
+ /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.\r
+ /// Introduced at Display Family / Display Model 06_0FH.\r
+ ///\r
+ UINT32 BTS_OFF_USR:1;\r
+ ///\r
+ /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a\r
+ /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r
+ ///\r
+ UINT32 FREEZE_LBRS_ON_PMI:1;\r
+ ///\r
+ /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the\r
+ /// global counter control MSR are frozen (address 38FH) on a PMI request.\r
+ /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r
+ ///\r
+ UINT32 FREEZE_PERFMON_ON_PMI:1;\r
+ ///\r
+ /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to\r
+ /// receive and generate PMI on behalf of the uncore. Introduced at\r
+ /// Display Family / Display Model 06_1AH.\r
+ ///\r
+ UINT32 ENABLE_UNCORE_PMI:1;\r
+ ///\r
+ /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace\r
+ /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.\r
+ ///\r
+ UINT32 FREEZE_WHILE_SMM:1;\r
+ ///\r
+ /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If\r
+ /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).\r
+ ///\r
+ UINT32 RTM_DEBUG:1;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_DEBUGCTL_REGISTER;\r
+\r
+\r
+/**\r
+ SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.\r
+ If IA32_MTRRCAP.SMRR[11] = 1.\r
+\r
+ @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);\r
+ AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.\r
+**/\r
+#define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Type. Specifies memory type of the range.\r
+ ///\r
+ UINT32 Type:8;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r
+ ///\r
+ UINT32 PhysBase:20;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_SMRR_PHYSBASE_REGISTER;\r
+\r
+\r
+/**\r
+ SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If\r
+ IA32_MTRRCAP[SMRR] = 1.\r
+\r
+ @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);\r
+ AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.\r
+**/\r
+#define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:11;\r
+ ///\r
+ /// [Bit 11] Valid Enable range mask.\r
+ ///\r
+ UINT32 Valid:1;\r
+ ///\r
+ /// [Bits 31:12] PhysMask SMRR address range mask.\r
+ ///\r
+ UINT32 PhysMask:20;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_SMRR_PHYSMASK_REGISTER;\r
+\r
+\r
+/**\r
+ DCA Capability (R). If CPUID.01H: ECX[18] = 1.\r
+\r
+ @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);\r
+ @endcode\r
+ @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.\r
+**/\r
+#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r
+\r
+\r
+/**\r
+ If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.\r
+\r
+ @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);\r
+ AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);\r
+ @endcode\r
+ @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.\r
+**/\r
+#define MSR_IA32_CPU_DCA_CAP 0x000001F9\r
+\r
+\r
+/**\r
+ DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.\r
+\r
+ @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_DCA_0_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);\r
+ AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.\r
+**/\r
+#define MSR_IA32_DCA_0_CAP 0x000001FA\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_DCA_0_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no\r
+ /// defeatures are set.\r
+ ///\r
+ UINT32 DCA_ACTIVE:1;\r
+ ///\r
+ /// [Bits 2:1] TRANSACTION.\r
+ ///\r
+ UINT32 TRANSACTION:2;\r
+ ///\r
+ /// [Bits 6:3] DCA_TYPE.\r
+ ///\r
+ UINT32 DCA_TYPE:4;\r
+ ///\r
+ /// [Bits 10:7] DCA_QUEUE_SIZE.\r
+ ///\r
+ UINT32 DCA_QUEUE_SIZE:4;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW\r
+ /// side-effect.\r
+ ///\r
+ UINT32 DCA_DELAY:4;\r
+ UINT32 Reserved2:7;\r
+ ///\r
+ /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.\r
+ ///\r
+ UINT32 SW_BLOCK:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).\r
+ ///\r
+ UINT32 HW_BLOCK:1;\r
+ UINT32 Reserved4:5;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_DCA_0_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".\r
+ If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r
+\r
+ @param ECX MSR_IA32_MTRR_PHYSBASEn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.\r
+ MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r
+#define MSR_IA32_MTRR_PHYSBASE1 0x00000202\r
+#define MSR_IA32_MTRR_PHYSBASE2 0x00000204\r
+#define MSR_IA32_MTRR_PHYSBASE3 0x00000206\r
+#define MSR_IA32_MTRR_PHYSBASE4 0x00000208\r
+#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A\r
+#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C\r
+#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E\r
+#define MSR_IA32_MTRR_PHYSBASE8 0x00000210\r
+#define MSR_IA32_MTRR_PHYSBASE9 0x00000212\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to\r
+ #MSR_IA32_MTRR_PHYSBASE9\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Type. Specifies memory type of the range.\r
+ ///\r
+ UINT32 Type:8;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 31:12] PhysBase. MTRR physical Base Address.\r
+ ///\r
+ UINT32 PhysBase:20;\r
+ ///\r
+ /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.\r
+ /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r
+ /// maximum physical address range supported by the processor. It is\r
+ /// reported by CPUID leaf function 80000008H. If CPUID does not support\r
+ /// leaf 80000008H, the processor supports 36-bit physical address size,\r
+ /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r
+ ///\r
+ UINT32 PhysBaseHi:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_MTRR_PHYSBASE_REGISTER;\r
+\r
+\r
+/**\r
+ MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".\r
+ If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r
+\r
+ @param ECX MSR_IA32_MTRR_PHYSMASKn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.\r
+ MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r
+#define MSR_IA32_MTRR_PHYSMASK1 0x00000203\r
+#define MSR_IA32_MTRR_PHYSMASK2 0x00000205\r
+#define MSR_IA32_MTRR_PHYSMASK3 0x00000207\r
+#define MSR_IA32_MTRR_PHYSMASK4 0x00000209\r
+#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B\r
+#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D\r
+#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F\r
+#define MSR_IA32_MTRR_PHYSMASK8 0x00000211\r
+#define MSR_IA32_MTRR_PHYSMASK9 0x00000213\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to\r
+ #MSR_IA32_MTRR_PHYSMASK9\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:11;\r
+ ///\r
+ /// [Bit 11] Valid Enable range mask.\r
+ ///\r
+ UINT32 V:1;\r
+ ///\r
+ /// [Bits 31:12] PhysMask. MTRR address range mask.\r
+ ///\r
+ UINT32 PhysMask:20;\r
+ ///\r
+ /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.\r
+ /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r
+ /// maximum physical address range supported by the processor. It is\r
+ /// reported by CPUID leaf function 80000008H. If CPUID does not support\r
+ /// leaf 80000008H, the processor supports 36-bit physical address size,\r
+ /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r
+ ///\r
+ UINT32 PhysMaskHi:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_MTRR_PHYSMASK_REGISTER;\r
+\r
+\r
+/**\r
+ MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r
+\r
+\r
+/**\r
+ MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r
+\r
+\r
+/**\r
+ MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r
+\r
+\r
+/**\r
+ See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r
+\r
+\r
+/**\r
+ MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r
+\r
+\r
+/**\r
+ MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r
+\r
+\r
+/**\r
+ MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r
+\r
+\r
+/**\r
+ MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r
+\r
+\r
+/**\r
+ MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r
+\r
+\r
+/**\r
+ MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r
+\r
+\r
+/**\r
+ MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r
+\r
+\r
+/**\r
+ IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.\r
+\r
+ @param ECX MSR_IA32_PAT (0x00000277)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PAT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PAT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PAT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);\r
+ AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PAT is defined as IA32_PAT in SDM.\r
+**/\r
+#define MSR_IA32_PAT 0x00000277\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PAT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] PA0.\r
+ ///\r
+ UINT32 PA0:3;\r
+ UINT32 Reserved1:5;\r
+ ///\r
+ /// [Bits 10:8] PA1.\r
+ ///\r
+ UINT32 PA1:3;\r
+ UINT32 Reserved2:5;\r
+ ///\r
+ /// [Bits 18:16] PA2.\r
+ ///\r
+ UINT32 PA2:3;\r
+ UINT32 Reserved3:5;\r
+ ///\r
+ /// [Bits 26:24] PA3.\r
+ ///\r
+ UINT32 PA3:3;\r
+ UINT32 Reserved4:5;\r
+ ///\r
+ /// [Bits 34:32] PA4.\r
+ ///\r
+ UINT32 PA4:3;\r
+ UINT32 Reserved5:5;\r
+ ///\r
+ /// [Bits 42:40] PA5.\r
+ ///\r
+ UINT32 PA5:3;\r
+ UINT32 Reserved6:5;\r
+ ///\r
+ /// [Bits 50:48] PA6.\r
+ ///\r
+ UINT32 PA6:3;\r
+ UINT32 Reserved7:5;\r
+ ///\r
+ /// [Bits 58:56] PA7.\r
+ ///\r
+ UINT32 PA7:3;\r
+ UINT32 Reserved8:5;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PAT_REGISTER;\r
+\r
+\r
+/**\r
+ Provides the programming interface to use corrected MC error signaling\r
+ capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.\r
+\r
+ @param ECX MSR_IA32_MCn_CTL2\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MC_CTL2_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MC_CTL2_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_MC_CTL2_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);\r
+ AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.\r
+ MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.\r
+ MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.\r
+ MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.\r
+ MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r
+ MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.\r
+ MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.\r
+ MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.\r
+ MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.\r
+ MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.\r
+ MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.\r
+ MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.\r
+ MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.\r
+ MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.\r
+ MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.\r
+ MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.\r
+ MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.\r
+ MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.\r
+ MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.\r
+ MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.\r
+ MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.\r
+ MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.\r
+ MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.\r
+ MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.\r
+ MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.\r
+ MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.\r
+ MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.\r
+ MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.\r
+ MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.\r
+ MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.\r
+ MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.\r
+ MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_MC0_CTL2 0x00000280\r
+#define MSR_IA32_MC1_CTL2 0x00000281\r
+#define MSR_IA32_MC2_CTL2 0x00000282\r
+#define MSR_IA32_MC3_CTL2 0x00000283\r
+#define MSR_IA32_MC4_CTL2 0x00000284\r
+#define MSR_IA32_MC5_CTL2 0x00000285\r
+#define MSR_IA32_MC6_CTL2 0x00000286\r
+#define MSR_IA32_MC7_CTL2 0x00000287\r
+#define MSR_IA32_MC8_CTL2 0x00000288\r
+#define MSR_IA32_MC9_CTL2 0x00000289\r
+#define MSR_IA32_MC10_CTL2 0x0000028A\r
+#define MSR_IA32_MC11_CTL2 0x0000028B\r
+#define MSR_IA32_MC12_CTL2 0x0000028C\r
+#define MSR_IA32_MC13_CTL2 0x0000028D\r
+#define MSR_IA32_MC14_CTL2 0x0000028E\r
+#define MSR_IA32_MC15_CTL2 0x0000028F\r
+#define MSR_IA32_MC16_CTL2 0x00000290\r
+#define MSR_IA32_MC17_CTL2 0x00000291\r
+#define MSR_IA32_MC18_CTL2 0x00000292\r
+#define MSR_IA32_MC19_CTL2 0x00000293\r
+#define MSR_IA32_MC20_CTL2 0x00000294\r
+#define MSR_IA32_MC21_CTL2 0x00000295\r
+#define MSR_IA32_MC22_CTL2 0x00000296\r
+#define MSR_IA32_MC23_CTL2 0x00000297\r
+#define MSR_IA32_MC24_CTL2 0x00000298\r
+#define MSR_IA32_MC25_CTL2 0x00000299\r
+#define MSR_IA32_MC26_CTL2 0x0000029A\r
+#define MSR_IA32_MC27_CTL2 0x0000029B\r
+#define MSR_IA32_MC28_CTL2 0x0000029C\r
+#define MSR_IA32_MC29_CTL2 0x0000029D\r
+#define MSR_IA32_MC30_CTL2 0x0000029E\r
+#define MSR_IA32_MC31_CTL2 0x0000029F\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2\r
+ to #MSR_IA32_MC31_CTL2\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] Corrected error count threshold.\r
+ ///\r
+ UINT32 CorrectedErrorCountThreshold:15;\r
+ UINT32 Reserved1:15;\r
+ ///\r
+ /// [Bit 30] CMCI_EN.\r
+ ///\r
+ UINT32 CMCI_EN:1;\r
+ UINT32 Reserved2:1;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_MC_CTL2_REGISTER;\r
+\r
+\r
+/**\r
+ MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.\r
+\r
+ @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
+ AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.\r
+**/\r
+#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Default Memory Type.\r
+ ///\r
+ UINT32 Type:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] Fixed Range MTRR Enable.\r
+ ///\r
+ UINT32 FE:1;\r
+ ///\r
+ /// [Bit 11] MTRR Enable.\r
+ ///\r
+ UINT32 E:1;\r
+ UINT32 Reserved2:20;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_MTRR_DEF_TYPE_REGISTER;\r
+\r
+\r
+/**\r
+ Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If\r
+ CPUID.0AH: EDX[4:0] > 0.\r
+\r
+ @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);\r
+ AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.\r
+**/\r
+#define MSR_IA32_FIXED_CTR0 0x00000309\r
+\r
+\r
+/**\r
+ Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r
+ CPUID.0AH: EDX[4:0] > 1.\r
+\r
+ @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);\r
+ AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.\r
+**/\r
+#define MSR_IA32_FIXED_CTR1 0x0000030A\r
+\r
+\r
+/**\r
+ Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r
+ CPUID.0AH: EDX[4:0] > 2.\r
+\r
+ @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);\r
+ AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.\r
+**/\r
+#define MSR_IA32_FIXED_CTR2 0x0000030B\r
+\r
+\r
+/**\r
+ RO. If CPUID.01H: ECX[15] = 1.\r
+\r
+ @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);\r
+ AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.\r
+**/\r
+#define MSR_IA32_PERF_CAPABILITIES 0x00000345\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 5:0] LBR format.\r
+ ///\r
+ UINT32 LBR_FMT:6;\r
+ ///\r
+ /// [Bit 6] PEBS Trap.\r
+ ///\r
+ UINT32 PEBS_TRAP:1;\r
+ ///\r
+ /// [Bit 7] PEBSSaveArchRegs.\r
+ ///\r
+ UINT32 PEBS_ARCH_REG:1;\r
+ ///\r
+ /// [Bits 11:8] PEBS Record Format.\r
+ ///\r
+ UINT32 PEBS_REC_FMT:4;\r
+ ///\r
+ /// [Bit 12] 1: Freeze while SMM is supported.\r
+ ///\r
+ UINT32 SMM_FREEZE:1;\r
+ ///\r
+ /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.\r
+ ///\r
+ UINT32 FW_WRITE:1;\r
+ UINT32 Reserved1:18;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PERF_CAPABILITIES_REGISTER;\r
+\r
+\r
+/**\r
+ Fixed-Function Performance Counter Control (R/W) Counter increments while\r
+ the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with\r
+ the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]\r
+ > 1.\r
+\r
+ @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);\r
+ AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.\r
+**/\r
+#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.\r
+ ///\r
+ UINT32 EN0_OS:1;\r
+ ///\r
+ /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.\r
+ ///\r
+ UINT32 EN0_Usr:1;\r
+ ///\r
+ /// [Bit 2] AnyThread: When set to 1, it enables counting the associated\r
+ /// event conditions occurring across all logical processors sharing a\r
+ /// processor core. When set to 0, the counter only increments the\r
+ /// associated event conditions occurring in the logical processor which\r
+ /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
+ ///\r
+ UINT32 AnyThread0:1;\r
+ ///\r
+ /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.\r
+ ///\r
+ UINT32 EN0_PMI:1;\r
+ ///\r
+ /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.\r
+ ///\r
+ UINT32 EN1_OS:1;\r
+ ///\r
+ /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.\r
+ ///\r
+ UINT32 EN1_Usr:1;\r
+ ///\r
+ /// [Bit 6] AnyThread: When set to 1, it enables counting the associated\r
+ /// event conditions occurring across all logical processors sharing a\r
+ /// processor core. When set to 0, the counter only increments the\r
+ /// associated event conditions occurring in the logical processor which\r
+ /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
+ ///\r
+ UINT32 AnyThread1:1;\r
+ ///\r
+ /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.\r
+ ///\r
+ UINT32 EN1_PMI:1;\r
+ ///\r
+ /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.\r
+ ///\r
+ UINT32 EN2_OS:1;\r
+ ///\r
+ /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.\r
+ ///\r
+ UINT32 EN2_Usr:1;\r
+ ///\r
+ /// [Bit 10] AnyThread: When set to 1, it enables counting the associated\r
+ /// event conditions occurring across all logical processors sharing a\r
+ /// processor core. When set to 0, the counter only increments the\r
+ /// associated event conditions occurring in the logical processor which\r
+ /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
+ ///\r
+ UINT32 AnyThread2:1;\r
+ ///\r
+ /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.\r
+ ///\r
+ UINT32 EN2_PMI:1;\r
+ UINT32 Reserved1:20;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_FIXED_CTR_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.\r
+\r
+ @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);\r
+ @endcode\r
+ @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:\r
+ /// EAX[15:8] > 0.\r
+ ///\r
+ UINT32 Ovf_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:\r
+ /// EAX[15:8] > 1.\r
+ ///\r
+ UINT32 Ovf_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:\r
+ /// EAX[15:8] > 2.\r
+ ///\r
+ UINT32 Ovf_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:\r
+ /// EAX[15:8] > 3.\r
+ ///\r
+ UINT32 Ovf_PMC3:1;\r
+ UINT32 Reserved1:28;\r
+ ///\r
+ /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If\r
+ /// CPUID.0AH: EAX[7:0] > 1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr0:1;\r
+ ///\r
+ /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If\r
+ /// CPUID.0AH: EAX[7:0] > 1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr1:1;\r
+ ///\r
+ /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If\r
+ /// CPUID.0AH: EAX[7:0] > 1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr2:1;\r
+ UINT32 Reserved2:20;\r
+ ///\r
+ /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory\r
+ /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r
+ /// && IA32_RTIT_CTL.ToPA = 1.\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 58] LBR_Frz: LBRs are frozen due to -\r
+ /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If\r
+ /// CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 LBR_Frz:1;\r
+ ///\r
+ /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due\r
+ /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU\r
+ /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 CTR_Frz:1;\r
+ ///\r
+ /// [Bit 60] ASCI: Data in the performance counters in the core PMU may\r
+ /// include contributions from the direct or indirect operation intel SGX\r
+ /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.\r
+ ///\r
+ UINT32 ASCI:1;\r
+ ///\r
+ /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:\r
+ /// EAX[7:0] > 2.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:\r
+ /// EAX[7:0] > 0.\r
+ ///\r
+ UINT32 OvfBuf:1;\r
+ ///\r
+ /// [Bit 63] CondChgd: status bits of this register has changed. If\r
+ /// CPUID.0AH: EAX[7:0] > 0.\r
+ ///\r
+ UINT32 CondChgd:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Global Performance Counter Control (R/W) Counter increments while the result\r
+ of ANDing respective enable bit in this MSR with the corresponding OS or USR\r
+ bits in the general-purpose or fixed counter control MSR is true. If\r
+ CPUID.0AH: EAX[7:0] > 0.\r
+\r
+ @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);\r
+ AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
+**/\r
+#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.\r
+ /// Enable bitmask. Only the first n-1 bits are valid.\r
+ /// Bits n..31 are reserved.\r
+ ///\r
+ UINT32 EN_PMCn:32;\r
+ ///\r
+ /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.\r
+ /// Enable bitmask. Only the first n-1 bits are valid.\r
+ /// Bits 31:n are reserved.\r
+ ///\r
+ UINT32 EN_FIXED_CTRn:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >\r
+ 0 && CPUID.0AH: EAX[7:0] <= 3.\r
+\r
+ @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r
+ /// Clear bitmask. Only the first n-1 bits are valid.\r
+ /// Bits 31:n are reserved.\r
+ ///\r
+ UINT32 Ovf_PMCn:32;\r
+ ///\r
+ /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r
+ /// If CPUID.0AH: EDX[4:0] > n.\r
+ /// Clear bitmask. Only the first n-1 bits are valid.\r
+ /// Bits 22:n are reserved.\r
+ ///\r
+ UINT32 Ovf_FIXED_CTRn:23;\r
+ ///\r
+ /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r
+ /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved2:5;\r
+ ///\r
+ /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r
+ /// Display Model 06_2EH.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r
+ ///\r
+ UINT32 OvfBuf:1;\r
+ ///\r
+ /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r
+ ///\r
+ UINT32 CondChgd:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:\r
+ EAX[7:0] > 3.\r
+\r
+ @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);\r
+ AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
+**/\r
+#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r
+ /// Clear bitmask. Only the first n-1 bits are valid.\r
+ /// Bits 31:n are reserved.\r
+ ///\r
+ UINT32 Ovf_PMCn:32;\r
+ ///\r
+ /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r
+ /// If CPUID.0AH: EDX[4:0] > n.\r
+ /// Clear bitmask. Only the first n-1 bits are valid.\r
+ /// Bits 22:n are reserved.\r
+ ///\r
+ UINT32 Ovf_FIXED_CTRn:23;\r
+ ///\r
+ /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r
+ /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 LBR_Frz:1;\r
+ ///\r
+ /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 CTR_Frz:1;\r
+ ///\r
+ /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 ASCI:1;\r
+ ///\r
+ /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r
+ /// Display Model 06_2EH.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r
+ ///\r
+ UINT32 OvfBuf:1;\r
+ ///\r
+ /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r
+ ///\r
+ UINT32 CondChgd:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
+\r
+\r
+/**\r
+ Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:\r
+ EAX[7:0] > 3.\r
+\r
+ @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);\r
+ AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
+**/\r
+#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.\r
+ /// Set bitmask. Only the first n-1 bits are valid.\r
+ /// Bits 31:n are reserved.\r
+ ///\r
+ UINT32 Ovf_PMCn:32;\r
+ ///\r
+ /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.\r
+ /// If CPUID.0AH: EAX[7:0] > n.\r
+ /// Set bitmask. Only the first n-1 bits are valid.\r
+ /// Bits 22:n are reserved.\r
+ ///\r
+ UINT32 Ovf_FIXED_CTRn:23;\r
+ ///\r
+ /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 LBR_Frz:1;\r
+ ///\r
+ /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 CTR_Frz:1;\r
+ ///\r
+ /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 ASCI:1;\r
+ ///\r
+ /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.\r
+ ///\r
+ UINT32 OvfBuf:1;\r
+ UINT32 Reserved3:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
+\r
+\r
+/**\r
+ Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >\r
+ 3.\r
+\r
+ @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);\r
+ @endcode\r
+ @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.\r
+**/\r
+#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.\r
+ /// Status bitmask. Only the first n-1 bits are valid.\r
+ /// Bits 31:n are reserved.\r
+ ///\r
+ UINT32 IA32_PERFEVTSELn:32;\r
+ ///\r
+ /// [Bits 62:32] IA32_FIXED_CTRn in use.\r
+ /// If CPUID.0AH: EAX[7:0] > n.\r
+ /// Status bitmask. Only the first n-1 bits are valid.\r
+ /// Bits 30:n are reserved.\r
+ ///\r
+ UINT32 IA32_FIXED_CTRn:31;\r
+ ///\r
+ /// [Bit 63] PMI in use.\r
+ ///\r
+ UINT32 PMI:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;\r
+\r
+\r
+/**\r
+ PEBS Control (R/W).\r
+\r
+ @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.\r
+**/\r
+#define MSR_IA32_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /\r
+ /// Display Model 06_0FH.\r
+ ///\r
+ UINT32 Enable:1;\r
+ ///\r
+ /// [Bits 3:1] Reserved or Model specific.\r
+ ///\r
+ UINT32 Reserved1:3;\r
+ UINT32 Reserved2:28;\r
+ ///\r
+ /// [Bits 35:32] Reserved or Model specific.\r
+ ///\r
+ UINT32 Reserved3:4;\r
+ UINT32 Reserved4:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ MCn_CTL. If IA32_MCG_CAP.CNT > n.\r
+\r
+ @param ECX MSR_IA32_MCn_CTL\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);\r
+ AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.\r
+ MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.\r
+ MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.\r
+ MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.\r
+ MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r
+ MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.\r
+ MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.\r
+ MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.\r
+ MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.\r
+ MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.\r
+ MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.\r
+ MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.\r
+ MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.\r
+ MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.\r
+ MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.\r
+ MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.\r
+ MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.\r
+ MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.\r
+ MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.\r
+ MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.\r
+ MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.\r
+ MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.\r
+ MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.\r
+ MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.\r
+ MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.\r
+ MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.\r
+ MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.\r
+ MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.\r
+ MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_MC0_CTL 0x00000400\r
+#define MSR_IA32_MC1_CTL 0x00000404\r
+#define MSR_IA32_MC2_CTL 0x00000408\r
+#define MSR_IA32_MC3_CTL 0x0000040C\r
+#define MSR_IA32_MC4_CTL 0x00000410\r
+#define MSR_IA32_MC5_CTL 0x00000414\r
+#define MSR_IA32_MC6_CTL 0x00000418\r
+#define MSR_IA32_MC7_CTL 0x0000041C\r
+#define MSR_IA32_MC8_CTL 0x00000420\r
+#define MSR_IA32_MC9_CTL 0x00000424\r
+#define MSR_IA32_MC10_CTL 0x00000428\r
+#define MSR_IA32_MC11_CTL 0x0000042C\r
+#define MSR_IA32_MC12_CTL 0x00000430\r
+#define MSR_IA32_MC13_CTL 0x00000434\r
+#define MSR_IA32_MC14_CTL 0x00000438\r
+#define MSR_IA32_MC15_CTL 0x0000043C\r
+#define MSR_IA32_MC16_CTL 0x00000440\r
+#define MSR_IA32_MC17_CTL 0x00000444\r
+#define MSR_IA32_MC18_CTL 0x00000448\r
+#define MSR_IA32_MC19_CTL 0x0000044C\r
+#define MSR_IA32_MC20_CTL 0x00000450\r
+#define MSR_IA32_MC21_CTL 0x00000454\r
+#define MSR_IA32_MC22_CTL 0x00000458\r
+#define MSR_IA32_MC23_CTL 0x0000045C\r
+#define MSR_IA32_MC24_CTL 0x00000460\r
+#define MSR_IA32_MC25_CTL 0x00000464\r
+#define MSR_IA32_MC26_CTL 0x00000468\r
+#define MSR_IA32_MC27_CTL 0x0000046C\r
+#define MSR_IA32_MC28_CTL 0x00000470\r
+/// @}\r
+\r
+\r
+/**\r
+ MCn_STATUS. If IA32_MCG_CAP.CNT > n.\r
+\r
+ @param ECX MSR_IA32_MCn_STATUS\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);\r
+ AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.\r
+ MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.\r
+ MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.\r
+ MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.\r
+ MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.\r
+ MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.\r
+ MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.\r
+ MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.\r
+ MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.\r
+ MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.\r
+ MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.\r
+ MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.\r
+ MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.\r
+ MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.\r
+ MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.\r
+ MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.\r
+ MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.\r
+ MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.\r
+ MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.\r
+ MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.\r
+ MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.\r
+ MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.\r
+ MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.\r
+ MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.\r
+ MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.\r
+ MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.\r
+ MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.\r
+ MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.\r
+ MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_MC0_STATUS 0x00000401\r
+#define MSR_IA32_MC1_STATUS 0x00000405\r
+#define MSR_IA32_MC2_STATUS 0x00000409\r
+#define MSR_IA32_MC3_STATUS 0x0000040D\r
+#define MSR_IA32_MC4_STATUS 0x00000411\r
+#define MSR_IA32_MC5_STATUS 0x00000415\r
+#define MSR_IA32_MC6_STATUS 0x00000419\r
+#define MSR_IA32_MC7_STATUS 0x0000041D\r
+#define MSR_IA32_MC8_STATUS 0x00000421\r
+#define MSR_IA32_MC9_STATUS 0x00000425\r
+#define MSR_IA32_MC10_STATUS 0x00000429\r
+#define MSR_IA32_MC11_STATUS 0x0000042D\r
+#define MSR_IA32_MC12_STATUS 0x00000431\r
+#define MSR_IA32_MC13_STATUS 0x00000435\r
+#define MSR_IA32_MC14_STATUS 0x00000439\r
+#define MSR_IA32_MC15_STATUS 0x0000043D\r
+#define MSR_IA32_MC16_STATUS 0x00000441\r
+#define MSR_IA32_MC17_STATUS 0x00000445\r
+#define MSR_IA32_MC18_STATUS 0x00000449\r
+#define MSR_IA32_MC19_STATUS 0x0000044D\r
+#define MSR_IA32_MC20_STATUS 0x00000451\r
+#define MSR_IA32_MC21_STATUS 0x00000455\r
+#define MSR_IA32_MC22_STATUS 0x00000459\r
+#define MSR_IA32_MC23_STATUS 0x0000045D\r
+#define MSR_IA32_MC24_STATUS 0x00000461\r
+#define MSR_IA32_MC25_STATUS 0x00000465\r
+#define MSR_IA32_MC26_STATUS 0x00000469\r
+#define MSR_IA32_MC27_STATUS 0x0000046D\r
+#define MSR_IA32_MC28_STATUS 0x00000471\r
+/// @}\r
+\r
+\r
+/**\r
+ MCn_ADDR. If IA32_MCG_CAP.CNT > n.\r
+\r
+ @param ECX MSR_IA32_MCn_ADDR\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);\r
+ AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.\r
+ MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.\r
+ MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.\r
+ MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.\r
+ MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.\r
+ MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.\r
+ MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.\r
+ MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.\r
+ MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.\r
+ MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.\r
+ MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.\r
+ MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.\r
+ MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.\r
+ MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.\r
+ MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.\r
+ MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.\r
+ MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.\r
+ MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.\r
+ MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.\r
+ MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.\r
+ MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.\r
+ MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.\r
+ MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.\r
+ MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.\r
+ MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.\r
+ MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.\r
+ MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.\r
+ MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.\r
+ MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_MC0_ADDR 0x00000402\r
+#define MSR_IA32_MC1_ADDR 0x00000406\r
+#define MSR_IA32_MC2_ADDR 0x0000040A\r
+#define MSR_IA32_MC3_ADDR 0x0000040E\r
+#define MSR_IA32_MC4_ADDR 0x00000412\r
+#define MSR_IA32_MC5_ADDR 0x00000416\r
+#define MSR_IA32_MC6_ADDR 0x0000041A\r
+#define MSR_IA32_MC7_ADDR 0x0000041E\r
+#define MSR_IA32_MC8_ADDR 0x00000422\r
+#define MSR_IA32_MC9_ADDR 0x00000426\r
+#define MSR_IA32_MC10_ADDR 0x0000042A\r
+#define MSR_IA32_MC11_ADDR 0x0000042E\r
+#define MSR_IA32_MC12_ADDR 0x00000432\r
+#define MSR_IA32_MC13_ADDR 0x00000436\r
+#define MSR_IA32_MC14_ADDR 0x0000043A\r
+#define MSR_IA32_MC15_ADDR 0x0000043E\r
+#define MSR_IA32_MC16_ADDR 0x00000442\r
+#define MSR_IA32_MC17_ADDR 0x00000446\r
+#define MSR_IA32_MC18_ADDR 0x0000044A\r
+#define MSR_IA32_MC19_ADDR 0x0000044E\r
+#define MSR_IA32_MC20_ADDR 0x00000452\r
+#define MSR_IA32_MC21_ADDR 0x00000456\r
+#define MSR_IA32_MC22_ADDR 0x0000045A\r
+#define MSR_IA32_MC23_ADDR 0x0000045E\r
+#define MSR_IA32_MC24_ADDR 0x00000462\r
+#define MSR_IA32_MC25_ADDR 0x00000466\r
+#define MSR_IA32_MC26_ADDR 0x0000046A\r
+#define MSR_IA32_MC27_ADDR 0x0000046E\r
+#define MSR_IA32_MC28_ADDR 0x00000472\r
+/// @}\r
+\r
+\r
+/**\r
+ MCn_MISC. If IA32_MCG_CAP.CNT > n.\r
+\r
+ @param ECX MSR_IA32_MCn_MISC\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);\r
+ AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);\r
+ @endcode\r
+ @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.\r
+ MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.\r
+ MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.\r
+ MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.\r
+ MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.\r
+ MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.\r
+ MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
+ MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.\r
+ MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.\r
+ MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.\r
+ MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.\r
+ MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.\r
+ MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.\r
+ MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.\r
+ MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.\r
+ MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.\r
+ MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.\r
+ MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.\r
+ MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.\r
+ MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.\r
+ MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.\r
+ MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.\r
+ MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.\r
+ MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.\r
+ MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.\r
+ MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.\r
+ MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.\r
+ MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.\r
+ MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_MC0_MISC 0x00000403\r
+#define MSR_IA32_MC1_MISC 0x00000407\r
+#define MSR_IA32_MC2_MISC 0x0000040B\r
+#define MSR_IA32_MC3_MISC 0x0000040F\r
+#define MSR_IA32_MC4_MISC 0x00000413\r
+#define MSR_IA32_MC5_MISC 0x00000417\r
+#define MSR_IA32_MC6_MISC 0x0000041B\r
+#define MSR_IA32_MC7_MISC 0x0000041F\r
+#define MSR_IA32_MC8_MISC 0x00000423\r
+#define MSR_IA32_MC9_MISC 0x00000427\r
+#define MSR_IA32_MC10_MISC 0x0000042B\r
+#define MSR_IA32_MC11_MISC 0x0000042F\r
+#define MSR_IA32_MC12_MISC 0x00000433\r
+#define MSR_IA32_MC13_MISC 0x00000437\r
+#define MSR_IA32_MC14_MISC 0x0000043B\r
+#define MSR_IA32_MC15_MISC 0x0000043F\r
+#define MSR_IA32_MC16_MISC 0x00000443\r
+#define MSR_IA32_MC17_MISC 0x00000447\r
+#define MSR_IA32_MC18_MISC 0x0000044B\r
+#define MSR_IA32_MC19_MISC 0x0000044F\r
+#define MSR_IA32_MC20_MISC 0x00000453\r
+#define MSR_IA32_MC21_MISC 0x00000457\r
+#define MSR_IA32_MC22_MISC 0x0000045B\r
+#define MSR_IA32_MC23_MISC 0x0000045F\r
+#define MSR_IA32_MC24_MISC 0x00000463\r
+#define MSR_IA32_MC25_MISC 0x00000467\r
+#define MSR_IA32_MC26_MISC 0x0000046B\r
+#define MSR_IA32_MC27_MISC 0x0000046F\r
+#define MSR_IA32_MC28_MISC 0x00000473\r
+/// @}\r
+\r
+\r
+/**\r
+ Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic\r
+ VMX Information.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_BASIC (0x00000480)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_VMX_BASIC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r
+ @endcode\r
+ @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r
+**/\r
+#define MSR_IA32_VMX_BASIC 0x00000480\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 30:0] VMCS revision identifier used by the processor. Processors\r
+ /// that use the same VMCS revision identifier use the same size for VMCS\r
+ /// regions (see subsequent item on bits 44:32).\r
+ ///\r
+ /// @note Earlier versions of this manual specified that the VMCS revision\r
+ /// identifier was a 32-bit field in bits 31:0 of this MSR. For all\r
+ /// processors produced prior to this change, bit 31 of this MSR was read\r
+ /// as 0.\r
+ ///\r
+ UINT32 VmcsRevisonId:31;\r
+ UINT32 MustBeZero:1;\r
+ ///\r
+ /// [Bit 44:32] Reports the number of bytes that software should allocate\r
+ /// for the VMXON region and any VMCS region. It is a value greater than\r
+ /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r
+ ///\r
+ UINT32 VmcsSize:13;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 48] Indicates the width of the physical addresses that may be used\r
+ /// for the VMXON region, each VMCS, and data structures referenced by\r
+ /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX\r
+ /// transitions). If the bit is 0, these addresses are limited to the\r
+ /// processor's physical-address width. If the bit is 1, these addresses\r
+ /// are limited to 32 bits. This bit is always 0 for processors that\r
+ /// support Intel 64 architecture.\r
+ ///\r
+ /// @note On processors that support Intel 64 architecture, the pointer\r
+ /// must not set bits beyond the processor's physical address width.\r
+ ///\r
+ UINT32 VmcsAddressWidth:1;\r
+ ///\r
+ /// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r
+ /// dual-monitor treatment of system-management interrupts and\r
+ /// system-management mode. See Section 34.15 for details of this treatment.\r
+ ///\r
+ UINT32 DualMonitor:1;\r
+ ///\r
+ /// [Bit 53:50] report the memory type that should be used for the VMCS,\r
+ /// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r
+ /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG\r
+ /// header. If software needs to access these data structures (e.g., to\r
+ /// modify the contents of the MSR bitmaps), it can configure the paging\r
+ /// structures to map them into the linear-address space. If it does so,\r
+ /// it should establish mappings that use the memory type reported bits\r
+ /// 53:50 in this MSR.\r
+ ///\r
+ /// As of this writing, all processors that support VMX operation indicate\r
+ /// the write-back type.\r
+ ///\r
+ /// If software needs to access these data structures (e.g., to modify\r
+ /// the contents of the MSR bitmaps), it can configure the paging\r
+ /// structures to map them into the linear-address space. If it does so,\r
+ /// it should establish mappings that use the memory type reported in this\r
+ /// MSR.\r
+ ///\r
+ /// @note Alternatively, software may map any of these regions or\r
+ /// structures with the UC memory type. (This may be necessary for the MSEG\r
+ /// header.) Doing so is discouraged unless necessary as it will cause the\r
+ /// performance of software accesses to those structures to suffer.\r
+ ///\r
+ ///\r
+ UINT32 MemoryType:4;\r
+ ///\r
+ /// [Bit 54] If bit 54 is read as 1, the processor reports information in\r
+ /// the VM-exit instruction-information field on VM exitsdue to execution\r
+ /// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r
+ /// is done only if this bit is read as 1.\r
+ ///\r
+ UINT32 InsOutsReporting:1;\r
+ ///\r
+ /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r
+ /// be cleared to 0. See Appendix A.2 for details. It also reports support\r
+ /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,\r
+ /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and\r
+ /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r
+ /// Appendix A.4, and Appendix A.5 for details.\r
+ ///\r
+ UINT32 VmxControls:1;\r
+ UINT32 Reserved2:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_VMX_BASIC_REGISTER;\r
+\r
+///\r
+/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType\r
+///\r
+#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00\r
+#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06\r
+///\r
+/// @}\r
+///\r
+\r
+\r
+/**\r
+ Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r
+ Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);\r
+ @endcode\r
+ @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.\r
+**/\r
+#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r
+\r
+\r
+/**\r
+ Capability Reporting Register of Primary Processor-based VM-execution\r
+ Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r
+ Controls.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);\r
+ @endcode\r
+ @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.\r
+**/\r
+#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r
+\r
+\r
+/**\r
+ Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,\r
+ "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);\r
+ @endcode\r
+ @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.\r
+**/\r
+#define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r
+\r
+\r
+/**\r
+ Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,\r
+ "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);\r
+ @endcode\r
+ @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.\r
+**/\r
+#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r
+\r
+\r
+/**\r
+ Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,\r
+ "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_MISC (0x00000485)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ IA32_VMX_MISC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
+ @endcode\r
+ @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r
+**/\r
+#define MSR_IA32_VMX_MISC 0x00000485\r
+\r
+/**\r
+ MSR information returned for MSR index #IA32_VMX_MISC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Reports a value X that specifies the relationship between the\r
+ /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).\r
+ /// Specifically, the VMX-preemption timer (if it is active) counts down by\r
+ /// 1 every time bit X in the TSC changes due to a TSC increment.\r
+ ///\r
+ UINT32 VmxTimerRatio:5;\r
+ ///\r
+ /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r
+ /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r
+ /// details. This bit is read as 1 on any logical processor that supports\r
+ /// the 1-setting of the "unrestricted guest" VM-execution control.\r
+ ///\r
+ UINT32 VmExitEferLma:1;\r
+ ///\r
+ /// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r
+ ///\r
+ UINT32 HltActivityStateSupported:1;\r
+ ///\r
+ /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r
+ ///\r
+ UINT32 ShutdownActivityStateSupported:1;\r
+ ///\r
+ /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r
+ ///\r
+ UINT32 WaitForSipiActivityStateSupported:1;\r
+ UINT32 Reserved1:5;\r
+ ///\r
+ /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r
+ /// in VMX operation. If the processor supports Intel PT but does not allow\r
+ /// it to be used in VMX operation, execution of VMXON clears\r
+ /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);\r
+ /// any attempt to set that bit while in VMX operation (including VMX root\r
+ /// operation) using the WRMSR instruction causes a general-protection\r
+ /// exception.\r
+ ///\r
+ UINT32 ProcessorTraceSupported:1;\r
+ ///\r
+ /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r
+ /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r
+ /// See Section 34.15.6.3.\r
+ ///\r
+ UINT32 SmBaseMsrSupported:1;\r
+ ///\r
+ /// [Bits 24:16] Indicate the number of CR3-target values supported by the\r
+ /// processor. This number is a value between 0 and 256, inclusive (bit 24\r
+ /// is set if and only if bits 23:16 are clear).\r
+ ///\r
+ UINT32 NumberOfCr3TargetValues:9;\r
+ ///\r
+ /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum\r
+ /// number of MSRs that should appear in the VM-exit MSR-store list, the\r
+ /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if\r
+ /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the\r
+ /// recommended maximum number of MSRs to be included in each list. If the\r
+ /// limit is exceeded, undefined processor behavior may result (including a\r
+ /// machine check during the VMX transition).\r
+ ///\r
+ UINT32 MsrStoreListMaximum:3;\r
+ ///\r
+ /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set\r
+ /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1\r
+ /// (see Section 34.14.4).\r
+ ///\r
+ UINT32 BlockSmiSupported:1;\r
+ ///\r
+ /// [Bit 29] read as 1, software can use VMWRITE to write to any supported\r
+ /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit\r
+ /// information fields.\r
+ ///\r
+ UINT32 VmWriteSupported:1;\r
+ ///\r
+ /// [Bit 30] If read as 1, VM entry allows injection of a software\r
+ /// interrupt, software exception, or privileged software exception with an\r
+ /// instruction length of 0.\r
+ ///\r
+ UINT32 VmInjectSupported:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r
+ /// processor.\r
+ ///\r
+ UINT32 MsegRevisionIdentifier:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} IA32_VMX_MISC_REGISTER;\r
+\r
+\r
+/**\r
+ Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r
+ "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);\r
+ @endcode\r
+ @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.\r
+**/\r
+#define MSR_IA32_VMX_CR0_FIXED0 0x00000486\r
+\r
+\r
+/**\r
+ Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,\r
+ "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);\r
+ @endcode\r
+ @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.\r
+**/\r
+#define MSR_IA32_VMX_CR0_FIXED1 0x00000487\r
+\r
+\r
+/**\r
+ Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,\r
+ "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);\r
+ @endcode\r
+ @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.\r
+**/\r
+#define MSR_IA32_VMX_CR4_FIXED0 0x00000488\r
+\r
+\r
+/**\r
+ Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,\r
+ "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);\r
+ @endcode\r
+ @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.\r
+**/\r
+#define MSR_IA32_VMX_CR4_FIXED1 0x00000489\r
+\r
+\r
+/**\r
+ Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix\r
+ A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.\r
+\r
+ @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);\r
+ @endcode\r
+ @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.\r
+**/\r
+#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A\r
+\r
+\r
+/**\r
+ Capability Reporting Register of Secondary Processor-based VM-execution\r
+ Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution\r
+ Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).\r
+\r
+ @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);\r
+ @endcode\r
+ @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.\r
+**/\r
+#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B\r
+\r
+\r
+/**\r
+ Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,\r
+ "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C\r
+ TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).\r
+\r
+ @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);\r
+ @endcode\r
+ @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.\r
+**/\r
+#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C\r
+\r
+\r
+/**\r
+ Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)\r
+ See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (\r
+ CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
+\r
+ @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);\r
+ @endcode\r
+ @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.\r
+**/\r
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D\r
+\r
+\r
+/**\r
+ Capability Reporting Register of Primary Processor-based VM-execution Flex\r
+ Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r
+ Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
+\r
+ @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);\r
+ @endcode\r
+ @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.\r
+**/\r
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E\r
+\r
+\r
+/**\r
+ Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix\r
+ A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
+\r
+ @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);\r
+ @endcode\r
+ @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.\r
+**/\r
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F\r
+\r
+\r
+/**\r
+ Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix\r
+ A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
+\r
+ @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);\r
+ @endcode\r
+ @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.\r
+**/\r
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490\r
+\r
+\r
+/**\r
+ Capability Reporting Register of VMfunction Controls (R/O). If(\r
+ CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
+\r
+ @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);\r
+ @endcode\r
+ @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.\r
+**/\r
+#define MSR_IA32_VMX_VMFUNC 0x00000491\r
+\r
+\r
+/**\r
+ Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&\r
+ IA32_PERF_CAPABILITIES[ 13] = 1.\r
+\r
+ @param ECX MSR_IA32_A_PMCn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);\r
+ AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);\r
+ @endcode\r
+ @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.\r
+ MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.\r
+ MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.\r
+ MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.\r
+ MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.\r
+ MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.\r
+ MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.\r
+ MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_A_PMC0 0x000004C1\r
+#define MSR_IA32_A_PMC1 0x000004C2\r
+#define MSR_IA32_A_PMC2 0x000004C3\r
+#define MSR_IA32_A_PMC3 0x000004C4\r
+#define MSR_IA32_A_PMC4 0x000004C5\r
+#define MSR_IA32_A_PMC5 0x000004C6\r
+#define MSR_IA32_A_PMC6 0x000004C7\r
+#define MSR_IA32_A_PMC7 0x000004C8\r
+/// @}\r
+\r
+\r
+/**\r
+ (R/W). If IA32_MCG_CAP.LMCE_P =1.\r
+\r
+ @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_MCG_EXT_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);\r
+ AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.\r
+**/\r
+#define MSR_IA32_MCG_EXT_CTL 0x000004D0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LMCE_EN.\r
+ ///\r
+ UINT32 LMCE_EN:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_MCG_EXT_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,\r
+ ECX=0H): EBX[2] = 1.\r
+\r
+ @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);\r
+ @endcode\r
+ @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.\r
+**/\r
+#define MSR_IA32_SGX_SVN_STATUS 0x00000500\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated\r
+ /// Code Modules (ACMs)".\r
+ ///\r
+ UINT32 Lock:1;\r
+ UINT32 Reserved1:15;\r
+ ///\r
+ /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with\r
+ /// Authenticated Code Modules (ACMs)".\r
+ ///\r
+ UINT32 SGX_SVN_SINIT:8;\r
+ UINT32 Reserved2:8;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_SGX_SVN_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r
+ && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)\r
+ ) ).\r
+\r
+ @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r
+ AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.\r
+**/\r
+#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved:7;\r
+ ///\r
+ /// [Bits 31:7] Base physical address.\r
+ ///\r
+ UINT32 Base:25;\r
+ ///\r
+ /// [Bits 63:32] Base physical address.\r
+ ///\r
+ UINT32 BaseHi:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,\r
+ ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)\r
+ (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).\r
+\r
+ @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r
+ AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.\r
+**/\r
+#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved:7;\r
+ ///\r
+ /// [Bits 31:7] MaskOrTableOffset.\r
+ ///\r
+ UINT32 MaskOrTableOffset:25;\r
+ ///\r
+ /// [Bits 63:32] Output Offset.\r
+ ///\r
+ UINT32 OutputOffset:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r
+\r
+/**\r
+ Format of ToPA table entries.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 END:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 INT:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 STOP:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 6:9] Indicates the size of the associated output region. See Section\r
+ /// 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 Size:4;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 12:31] Output Region Base Physical Address low part.\r
+ /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.\r
+ /// ATTENTION: The size of the address field is determined by the processor's\r
+ /// physical-address width (MAXPHYADDR) in bits, as reported in\r
+ /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r
+ /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
+ /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 Base:20;\r
+ ///\r
+ /// [Bit 32:63] Output Region Base Physical Address high part.\r
+ /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.\r
+ /// ATTENTION: The size of the address field is determined by the processor's\r
+ /// physical-address width (MAXPHYADDR) in bits, as reported in\r
+ /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r
+ /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
+ /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
+ ///\r
+ UINT32 BaseHi:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} RTIT_TOPA_TABLE_ENTRY;\r
+\r
+///\r
+/// The size of the associated output region usd by Topa.\r
+///\r
+typedef enum {\r
+ RtitTopaMemorySize4K = 0,\r
+ RtitTopaMemorySize8K,\r
+ RtitTopaMemorySize16K,\r
+ RtitTopaMemorySize32K,\r
+ RtitTopaMemorySize64K,\r
+ RtitTopaMemorySize128K,\r
+ RtitTopaMemorySize256K,\r
+ RtitTopaMemorySize512K,\r
+ RtitTopaMemorySize1M,\r
+ RtitTopaMemorySize2M,\r
+ RtitTopaMemorySize4M,\r
+ RtitTopaMemorySize8M,\r
+ RtitTopaMemorySize16M,\r
+ RtitTopaMemorySize32M,\r
+ RtitTopaMemorySize64M,\r
+ RtitTopaMemorySize128M\r
+} RTIT_TOPA_MEMORY_SIZE;\r
+\r
+/**\r
+ Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
+\r
+ @param ECX MSR_IA32_RTIT_CTL (0x00000570)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_RTIT_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
+ AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r
+**/\r
+#define MSR_IA32_RTIT_CTL 0x00000570\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] TraceEn.\r
+ ///\r
+ UINT32 TraceEn:1;\r
+ ///\r
+ /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
+ ///\r
+ UINT32 CYCEn:1;\r
+ ///\r
+ /// [Bit 2] OS.\r
+ ///\r
+ UINT32 OS:1;\r
+ ///\r
+ /// [Bit 3] User.\r
+ ///\r
+ UINT32 User:1;\r
+ ///\r
+ /// [Bit 4] PwrEvtEn.\r
+ ///\r
+ UINT32 PwrEvtEn:1;\r
+ ///\r
+ /// [Bit 5] FUPonPTW.\r
+ ///\r
+ UINT32 FUPonPTW:1;\r
+ ///\r
+ /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r
+ ///\r
+ UINT32 FabricEn:1;\r
+ ///\r
+ /// [Bit 7] CR3 filter.\r
+ ///\r
+ UINT32 CR3:1;\r
+ ///\r
+ /// [Bit 8] ToPA.\r
+ ///\r
+ UINT32 ToPA:1;\r
+ ///\r
+ /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r
+ ///\r
+ UINT32 MTCEn:1;\r
+ ///\r
+ /// [Bit 10] TSCEn.\r
+ ///\r
+ UINT32 TSCEn:1;\r
+ ///\r
+ /// [Bit 11] DisRETC.\r
+ ///\r
+ UINT32 DisRETC:1;\r
+ ///\r
+ /// [Bit 12] PTWEn.\r
+ ///\r
+ UINT32 PTWEn:1;\r
+ ///\r
+ /// [Bit 13] BranchEn.\r
+ ///\r
+ UINT32 BranchEn:1;\r
+ ///\r
+ /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r
+ ///\r
+ UINT32 MTCFreq:4;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
+ ///\r
+ UINT32 CYCThresh:4;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
+ ///\r
+ UINT32 PSBFreq:4;\r
+ UINT32 Reserved5:4;\r
+ ///\r
+ /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).\r
+ ///\r
+ UINT32 ADDR0_CFG:4;\r
+ ///\r
+ /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).\r
+ ///\r
+ UINT32 ADDR1_CFG:4;\r
+ ///\r
+ /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).\r
+ ///\r
+ UINT32 ADDR2_CFG:4;\r
+ ///\r
+ /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).\r
+ ///\r
+ UINT32 ADDR3_CFG:4;\r
+ UINT32 Reserved6:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_RTIT_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
+\r
+ @param ECX MSR_IA32_RTIT_STATUS (0x00000571)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_RTIT_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);\r
+ AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.\r
+**/\r
+#define MSR_IA32_RTIT_STATUS 0x00000571\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_RTIT_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] FilterEn, (writes ignored).\r
+ /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).\r
+ ///\r
+ UINT32 FilterEn:1;\r
+ ///\r
+ /// [Bit 1] ContexEn, (writes ignored).\r
+ ///\r
+ UINT32 ContexEn:1;\r
+ ///\r
+ /// [Bit 2] TriggerEn, (writes ignored).\r
+ ///\r
+ UINT32 TriggerEn:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 4] Error.\r
+ ///\r
+ UINT32 Error:1;\r
+ ///\r
+ /// [Bit 5] Stopped.\r
+ ///\r
+ UINT32 Stopped:1;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).\r
+ ///\r
+ UINT32 PacketByteCnt:17;\r
+ UINT32 Reserved3:15;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_RTIT_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Trace Filter CR3 Match Register (R/W).\r
+ If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
+\r
+ @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);\r
+ AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.\r
+**/\r
+#define MSR_IA32_RTIT_CR3_MATCH 0x00000572\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved:5;\r
+ ///\r
+ /// [Bits 31:5] CR3[63:5] value to match.\r
+ ///\r
+ UINT32 Cr3:27;\r
+ ///\r
+ /// [Bits 63:32] CR3[63:5] value to match.\r
+ ///\r
+ UINT32 Cr3Hi:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_RTIT_CR3_MATCH_REGISTER;\r
+\r
+\r
+/**\r
+ Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r
+\r
+ @param ECX MSR_IA32_RTIT_ADDRn_A\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_RTIT_ADDR_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);\r
+ AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.\r
+ MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.\r
+ MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.\r
+ MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_RTIT_ADDR0_A 0x00000580\r
+#define MSR_IA32_RTIT_ADDR1_A 0x00000582\r
+#define MSR_IA32_RTIT_ADDR2_A 0x00000584\r
+#define MSR_IA32_RTIT_ADDR3_A 0x00000586\r
+/// @}\r
+\r
+\r
+/**\r
+ Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r
+\r
+ @param ECX MSR_IA32_RTIT_ADDRn_B\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_RTIT_ADDR_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);\r
+ AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.\r
+ MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.\r
+ MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.\r
+ MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_RTIT_ADDR0_B 0x00000581\r
+#define MSR_IA32_RTIT_ADDR1_B 0x00000583\r
+#define MSR_IA32_RTIT_ADDR2_B 0x00000585\r
+#define MSR_IA32_RTIT_ADDR3_B 0x00000587\r
+/// @}\r
+\r
+\r
+/**\r
+ MSR information returned for MSR indexes\r
+ #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and\r
+ #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Virtual Address.\r
+ ///\r
+ UINT32 VirtualAddress:32;\r
+ ///\r
+ /// [Bits 47:32] Virtual Address.\r
+ ///\r
+ UINT32 VirtualAddressHi:16;\r
+ ///\r
+ /// [Bits 63:48] SignExt_VA.\r
+ ///\r
+ UINT32 SignExt_VA:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_RTIT_ADDR_REGISTER;\r
+\r
+\r
+/**\r
+ DS Save Area (R/W) Points to the linear address of the first byte of the DS\r
+ buffer management area, which is used to manage the BTS and PEBS buffers.\r
+ See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(\r
+ CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS\r
+ buffer management area, if IA-32e mode is active.\r
+\r
+ @param ECX MSR_IA32_DS_AREA (0x00000600)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_DS_AREA_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_DS_AREA_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);\r
+ AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);\r
+ @endcode\r
+ @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.\r
+**/\r
+#define MSR_IA32_DS_AREA 0x00000600\r
+\r
+\r
+/**\r
+ TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =\r
+ 1.\r
+\r
+ @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);\r
+ AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);\r
+ @endcode\r
+ @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.\r
+**/\r
+#define MSR_IA32_TSC_DEADLINE 0x000006E0\r
+\r
+\r
+/**\r
+ Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.\r
+\r
+ @param ECX MSR_IA32_PM_ENABLE (0x00000770)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PM_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);\r
+ AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.\r
+**/\r
+#define MSR_IA32_PM_ENABLE 0x00000770\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PM_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If\r
+ /// CPUID.06H:EAX.[7] = 1.\r
+ ///\r
+ UINT32 HWP_ENABLE:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PM_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.\r
+\r
+ @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);\r
+ @endcode\r
+ @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.\r
+**/\r
+#define MSR_IA32_HWP_CAPABILITIES 0x00000771\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance\r
+ /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
+ ///\r
+ UINT32 Highest_Performance:8;\r
+ ///\r
+ /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP\r
+ /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
+ ///\r
+ UINT32 Guaranteed_Performance:8;\r
+ ///\r
+ /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP\r
+ /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
+ ///\r
+ UINT32 Most_Efficient_Performance:8;\r
+ ///\r
+ /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance\r
+ /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
+ ///\r
+ UINT32 Lowest_Performance:8;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_HWP_CAPABILITIES_REGISTER;\r
+\r
+\r
+/**\r
+ Power Management Control Hints for All Logical Processors in a Package\r
+ (R/W). If CPUID.06H:EAX.[11] = 1.\r
+\r
+ @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);\r
+ AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.\r
+**/\r
+#define MSR_IA32_HWP_REQUEST_PKG 0x00000772\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r
+ /// CPUID.06H:EAX.[11] = 1.\r
+ ///\r
+ UINT32 Minimum_Performance:8;\r
+ ///\r
+ /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r
+ /// CPUID.06H:EAX.[11] = 1.\r
+ ///\r
+ UINT32 Maximum_Performance:8;\r
+ ///\r
+ /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r
+ /// If CPUID.06H:EAX.[11] = 1.\r
+ ///\r
+ UINT32 Desired_Performance:8;\r
+ ///\r
+ /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r
+ /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.\r
+ ///\r
+ UINT32 Energy_Performance_Preference:8;\r
+ ///\r
+ /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r
+ /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.\r
+ ///\r
+ UINT32 Activity_Window:10;\r
+ UINT32 Reserved:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_HWP_REQUEST_PKG_REGISTER;\r
+\r
+\r
+/**\r
+ Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.\r
+\r
+ @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_HWP_INTERRUPT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);\r
+ AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.\r
+**/\r
+#define MSR_IA32_HWP_INTERRUPT 0x00000773\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP\r
+ /// Notifications". If CPUID.06H:EAX.[8] = 1.\r
+ ///\r
+ UINT32 EN_Guaranteed_Performance_Change:1;\r
+ ///\r
+ /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".\r
+ /// If CPUID.06H:EAX.[8] = 1.\r
+ ///\r
+ UINT32 EN_Excursion_Minimum:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_HWP_INTERRUPT_REGISTER;\r
+\r
+\r
+/**\r
+ Power Management Control Hints to a Logical Processor (R/W). If\r
+ CPUID.06H:EAX.[7] = 1.\r
+\r
+ @param ECX MSR_IA32_HWP_REQUEST (0x00000774)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_HWP_REQUEST_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);\r
+ AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.\r
+**/\r
+#define MSR_IA32_HWP_REQUEST 0x00000774\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_HWP_REQUEST\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r
+ /// CPUID.06H:EAX.[7] = 1.\r
+ ///\r
+ UINT32 Minimum_Performance:8;\r
+ ///\r
+ /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r
+ /// CPUID.06H:EAX.[7] = 1.\r
+ ///\r
+ UINT32 Maximum_Performance:8;\r
+ ///\r
+ /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r
+ /// If CPUID.06H:EAX.[7] = 1.\r
+ ///\r
+ UINT32 Desired_Performance:8;\r
+ ///\r
+ /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r
+ /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.\r
+ ///\r
+ UINT32 Energy_Performance_Preference:8;\r
+ ///\r
+ /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r
+ /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.\r
+ ///\r
+ UINT32 Activity_Window:10;\r
+ ///\r
+ /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If\r
+ /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.\r
+ ///\r
+ UINT32 Package_Control:1;\r
+ UINT32 Reserved:21;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_HWP_REQUEST_REGISTER;\r
+\r
+\r
+/**\r
+ Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If\r
+ CPUID.06H:EAX.[7] = 1.\r
+\r
+ @param ECX MSR_IA32_HWP_STATUS (0x00000777)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_HWP_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);\r
+ AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.\r
+**/\r
+#define MSR_IA32_HWP_STATUS 0x00000777\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_HWP_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,\r
+ /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.\r
+ ///\r
+ UINT32 Guaranteed_Performance_Change:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP\r
+ /// Feedback". If CPUID.06H:EAX.[7] = 1.\r
+ ///\r
+ UINT32 Excursion_To_Minimum:1;\r
+ UINT32 Reserved2:29;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_HWP_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1\r
+ && IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_APICID (0x00000802)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_APICID 0x00000802\r
+\r
+\r
+/**\r
+ x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_VERSION 0x00000803\r
+\r
+\r
+/**\r
+ x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_TPR (0x00000808)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_TPR 0x00000808\r
+\r
+\r
+/**\r
+ x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_PPR 0x0000080A\r
+\r
+\r
+/**\r
+ x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]\r
+ = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = 0;\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_EOI 0x0000080B\r
+\r
+\r
+/**\r
+ x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_LDR 0x0000080D\r
+\r
+\r
+/**\r
+ x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1\r
+ && IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_SIVR 0x0000080F\r
+\r
+\r
+/**\r
+ x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).\r
+ If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_ISRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.\r
+ MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.\r
+ MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.\r
+ MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.\r
+ MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.\r
+ MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.\r
+ MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.\r
+ MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_X2APIC_ISR0 0x00000810\r
+#define MSR_IA32_X2APIC_ISR1 0x00000811\r
+#define MSR_IA32_X2APIC_ISR2 0x00000812\r
+#define MSR_IA32_X2APIC_ISR3 0x00000813\r
+#define MSR_IA32_X2APIC_ISR4 0x00000814\r
+#define MSR_IA32_X2APIC_ISR5 0x00000815\r
+#define MSR_IA32_X2APIC_ISR6 0x00000816\r
+#define MSR_IA32_X2APIC_ISR7 0x00000817\r
+/// @}\r
+\r
+\r
+/**\r
+ x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).\r
+ If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_TMRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.\r
+ MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.\r
+ MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.\r
+ MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.\r
+ MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.\r
+ MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.\r
+ MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.\r
+ MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_X2APIC_TMR0 0x00000818\r
+#define MSR_IA32_X2APIC_TMR1 0x00000819\r
+#define MSR_IA32_X2APIC_TMR2 0x0000081A\r
+#define MSR_IA32_X2APIC_TMR3 0x0000081B\r
+#define MSR_IA32_X2APIC_TMR4 0x0000081C\r
+#define MSR_IA32_X2APIC_TMR5 0x0000081D\r
+#define MSR_IA32_X2APIC_TMR6 0x0000081E\r
+#define MSR_IA32_X2APIC_TMR7 0x0000081F\r
+/// @}\r
+\r
+\r
+/**\r
+ x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).\r
+ If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_IRRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.\r
+ MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.\r
+ MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.\r
+ MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.\r
+ MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.\r
+ MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.\r
+ MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.\r
+ MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_IA32_X2APIC_IRR0 0x00000820\r
+#define MSR_IA32_X2APIC_IRR1 0x00000821\r
+#define MSR_IA32_X2APIC_IRR2 0x00000822\r
+#define MSR_IA32_X2APIC_IRR3 0x00000823\r
+#define MSR_IA32_X2APIC_IRR4 0x00000824\r
+#define MSR_IA32_X2APIC_IRR5 0x00000825\r
+#define MSR_IA32_X2APIC_IRR6 0x00000826\r
+#define MSR_IA32_X2APIC_IRR7 0x00000827\r
+/// @}\r
+\r
+\r
+/**\r
+ x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_ESR (0x00000828)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_ESR 0x00000828\r
+\r
+\r
+/**\r
+ x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If\r
+ CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F\r
+\r
+\r
+/**\r
+ x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_ICR (0x00000830)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_ICR 0x00000830\r
+\r
+\r
+/**\r
+ x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832\r
+\r
+\r
+/**\r
+ x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =\r
+ 1 && IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833\r
+\r
+\r
+/**\r
+ x2APIC LVT Performance Monitor Interrupt Register (R/W). If\r
+ CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_LVT_PMI 0x00000834\r
+\r
+\r
+/**\r
+ x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835\r
+\r
+\r
+/**\r
+ x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836\r
+\r
+\r
+/**\r
+ x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837\r
+\r
+\r
+/**\r
+ x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838\r
+\r
+\r
+/**\r
+ x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839\r
+\r
+\r
+/**\r
+ x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E\r
+\r
+\r
+/**\r
+ x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&\r
+ IA32_APIC_BASE.[10] = 1.\r
+\r
+ @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = 0;\r
+ AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);\r
+ @endcode\r
+ @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.\r
+**/\r
+#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F\r
+\r
+\r
+/**\r
+ Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.\r
+\r
+ @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);\r
+ AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.\r
+**/\r
+#define MSR_IA32_DEBUG_INTERFACE 0x00000C80\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.\r
+ /// Default is 0. If CPUID.01H:ECX.[11] = 1.\r
+ ///\r
+ UINT32 Enable:1;\r
+ UINT32 Reserved1:29;\r
+ ///\r
+ /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The\r
+ /// lock bit is set automatically on the first SMI assertion even if not\r
+ /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.\r
+ ///\r
+ UINT32 Lock:1;\r
+ ///\r
+ /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to\r
+ /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.\r
+ ///\r
+ UINT32 DebugOccurred:1;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_DEBUG_INTERFACE_REGISTER;\r
+\r
+\r
+/**\r
+ L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).\r
+\r
+ @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_L3_QOS_CFG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);\r
+ AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
+**/\r
+#define MSR_IA32_L3_QOS_CFG 0x00000C81\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate\r
+ /// in Code and Data Prioritization (CDP) mode.\r
+ ///\r
+ UINT32 Enable:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_L3_QOS_CFG_REGISTER;\r
+\r
+/**\r
+ L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).\r
+\r
+ @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_L2_QOS_CFG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);\r
+ AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.\r
+**/\r
+#define MSR_IA32_L2_QOS_CFG 0x00000C82\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate\r
+ /// in Code and Data Prioritization (CDP) mode.\r
+ ///\r
+ UINT32 Enable:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_L2_QOS_CFG_REGISTER;\r
+\r
+/**\r
+ Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]\r
+ = 1 ).\r
+\r
+ @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_QM_EVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);\r
+ AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
+**/\r
+#define MSR_IA32_QM_EVTSEL 0x00000C8D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_QM_EVTSEL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via\r
+ /// IA32_QM_CTR.\r
+ ///\r
+ UINT32 EventID:8;\r
+ UINT32 Reserved:24;\r
+ ///\r
+ /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to\r
+ /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (\r
+ /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r
+ ///\r
+ UINT32 ResourceMonitoringID:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_QM_EVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+ Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1\r
+ ).\r
+\r
+ @param ECX MSR_IA32_QM_CTR (0x00000C8E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_QM_CTR_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_QM_CTR_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_QM_CTR_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);\r
+ @endcode\r
+ @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.\r
+**/\r
+#define MSR_IA32_QM_CTR 0x00000C8E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_QM_CTR\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Resource Monitored Data.\r
+ ///\r
+ UINT32 ResourceMonitoredData:32;\r
+ ///\r
+ /// [Bits 61:32] Resource Monitored Data.\r
+ ///\r
+ UINT32 ResourceMonitoredDataHi:30;\r
+ ///\r
+ /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not\r
+ /// available or not monitored for this resource or RMID.\r
+ ///\r
+ UINT32 Unavailable:1;\r
+ ///\r
+ /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was\r
+ /// written to IA32_PQR_QM_EVTSEL.\r
+ ///\r
+ UINT32 Error:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_QM_CTR_REGISTER;\r
+\r
+\r
+/**\r
+ Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]\r
+ =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).\r
+\r
+ @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PQR_ASSOC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);\r
+ AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
+**/\r
+#define MSR_IA32_PQR_ASSOC 0x00000C8F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PQR_ASSOC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware\r
+ /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`\r
+ /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r
+ ///\r
+ UINT32 ResourceMonitoringID:32;\r
+ ///\r
+ /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on\r
+ /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,\r
+ /// ECX=0):EBX.[15] = 1 ).\r
+ ///\r
+ UINT32 COS:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PQR_ASSOC_REGISTER;\r
+\r
+\r
+/**\r
+ Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,\r
+ ECX=0H):EBX[14] = 1).\r
+\r
+ @param ECX MSR_IA32_BNDCFGS (0x00000D90)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_BNDCFGS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_BNDCFGS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_BNDCFGS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);\r
+ AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.\r
+**/\r
+#define MSR_IA32_BNDCFGS 0x00000D90\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_BNDCFGS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] EN: Enable Intel MPX in supervisor mode.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch\r
+ /// instructions in the absence of the BND prefix.\r
+ ///\r
+ UINT32 BNDPRESERVE:1;\r
+ UINT32 Reserved:10;\r
+ ///\r
+ /// [Bits 31:12] Base Address of Bound Directory.\r
+ ///\r
+ UINT32 Base:20;\r
+ ///\r
+ /// [Bits 63:32] Base Address of Bound Directory.\r
+ ///\r
+ UINT32 BaseHi:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_BNDCFGS_REGISTER;\r
+\r
+\r
+/**\r
+ Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.\r
+\r
+ @param ECX MSR_IA32_XSS (0x00000DA0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_XSS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_XSS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_XSS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);\r
+ AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_XSS is defined as IA32_XSS in SDM.\r
+**/\r
+#define MSR_IA32_XSS 0x00000DA0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_XSS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bit 8] Trace Packet Configuration State (R/W).\r
+ ///\r
+ UINT32 TracePacketConfigurationState:1;\r
+ UINT32 Reserved2:23;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_XSS_REGISTER;\r
+\r
+\r
+/**\r
+ Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.\r
+\r
+ @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PKG_HDC_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);\r
+ AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.\r
+**/\r
+#define MSR_IA32_PKG_HDC_CTL 0x00000DB0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled\r
+ /// logical processors in the package. See Section 14.5.2, "Package level\r
+ /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.\r
+ ///\r
+ UINT32 HDC_Pkg_Enable:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PKG_HDC_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.\r
+\r
+ @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PM_CTL1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_PM_CTL1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_PM_CTL1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);\r
+ AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.\r
+**/\r
+#define MSR_IA32_PM_CTL1 0x00000DB1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_PM_CTL1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for\r
+ /// package level HDC control. See Section 14.5.3.\r
+ /// If CPUID.06H:EAX.[13] = 1.\r
+ ///\r
+ UINT32 HDC_Allow_Block:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_PM_CTL1_REGISTER;\r
+\r
+\r
+/**\r
+ Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.\r
+ Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical\r
+ processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.\r
+\r
+ @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);\r
+ @endcode\r
+ @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.\r
+**/\r
+#define MSR_IA32_THREAD_STALL 0x00000DB2\r
+\r
+\r
+/**\r
+ Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]\r
+ CPUID.80000001H:EDX.[2 9]).\r
+\r
+ @param ECX MSR_IA32_EFER (0xC0000080)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_EFER_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_EFER_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_EFER_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r
+ AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_EFER is defined as IA32_EFER in SDM.\r
+**/\r
+#define MSR_IA32_EFER 0xC0000080\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_EFER\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET\r
+ /// instructions in 64-bit mode.\r
+ ///\r
+ UINT32 SCE:1;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode\r
+ /// operation.\r
+ ///\r
+ UINT32 LME:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode\r
+ /// is active when set.\r
+ ///\r
+ UINT32 LMA:1;\r
+ ///\r
+ /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).\r
+ ///\r
+ UINT32 NXE:1;\r
+ UINT32 Reserved3:20;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_EFER_REGISTER;\r
+\r
+\r
+/**\r
+ System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r
+\r
+ @param ECX MSR_IA32_STAR (0xC0000081)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_STAR);\r
+ AsmWriteMsr64 (MSR_IA32_STAR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_STAR is defined as IA32_STAR in SDM.\r
+**/\r
+#define MSR_IA32_STAR 0xC0000081\r
+\r
+\r
+/**\r
+ IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r
+\r
+ @param ECX MSR_IA32_LSTAR (0xC0000082)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_LSTAR);\r
+ AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.\r
+**/\r
+#define MSR_IA32_LSTAR 0xC0000082\r
+\r
+/**\r
+ IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL\r
+ instruction is not recognized in compatibility mode. If\r
+ CPUID.80000001:EDX.[29] = 1.\r
+\r
+ @param ECX MSR_IA32_CSTAR (0xC0000083)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_CSTAR);\r
+ AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);\r
+ @endcode\r
+ @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.\r
+**/\r
+#define MSR_IA32_CSTAR 0xC0000083\r
+\r
+/**\r
+ System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r
+\r
+ @param ECX MSR_IA32_FMASK (0xC0000084)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_FMASK);\r
+ AsmWriteMsr64 (MSR_IA32_FMASK, Msr);\r
+ @endcode\r
+ @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.\r
+**/\r
+#define MSR_IA32_FMASK 0xC0000084\r
+\r
+\r
+/**\r
+ Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
+\r
+ @param ECX MSR_IA32_FS_BASE (0xC0000100)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);\r
+ AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);\r
+ @endcode\r
+ @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.\r
+**/\r
+#define MSR_IA32_FS_BASE 0xC0000100\r
+\r
+\r
+/**\r
+ Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
+\r
+ @param ECX MSR_IA32_GS_BASE (0xC0000101)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);\r
+ AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);\r
+ @endcode\r
+ @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.\r
+**/\r
+#define MSR_IA32_GS_BASE 0xC0000101\r
+\r
+\r
+/**\r
+ Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
+\r
+ @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);\r
+ AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);\r
+ @endcode\r
+ @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.\r
+**/\r
+#define MSR_IA32_KERNEL_GS_BASE 0xC0000102\r
+\r
+\r
+/**\r
+ Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.\r
+\r
+ @param ECX MSR_IA32_TSC_AUX (0xC0000103)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IA32_TSC_AUX_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IA32_TSC_AUX_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IA32_TSC_AUX_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);\r
+ AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.\r
+**/\r
+#define MSR_IA32_TSC_AUX 0xC0000103\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_TSC_AUX\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] AUX: Auxiliary signature of TSC.\r
+ ///\r
+ UINT32 AUX:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IA32_TSC_AUX_REGISTER;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ IA32 Local APIC Definitions.\r
+\r
+ Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef __INTEL_LOCAL_APIC_H__\r
+#define __INTEL_LOCAL_APIC_H__\r
+\r
+//\r
+// Definition for Local APIC registers and related values\r
+//\r
+#define XAPIC_ID_OFFSET 0x20\r
+#define XAPIC_VERSION_OFFSET 0x30\r
+#define XAPIC_EOI_OFFSET 0x0b0\r
+#define XAPIC_ICR_DFR_OFFSET 0x0e0\r
+#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r
+#define XAPIC_ICR_LOW_OFFSET 0x300\r
+#define XAPIC_ICR_HIGH_OFFSET 0x310\r
+#define XAPIC_LVT_TIMER_OFFSET 0x320\r
+#define XAPIC_LVT_LINT0_OFFSET 0x350\r
+#define XAPIC_LVT_LINT1_OFFSET 0x360\r
+#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r
+#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r
+#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
+\r
+#define X2APIC_MSR_BASE_ADDRESS 0x800\r
+#define X2APIC_MSR_ICR_ADDRESS 0x830\r
+\r
+#define LOCAL_APIC_DELIVERY_MODE_FIXED 0\r
+#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r
+#define LOCAL_APIC_DELIVERY_MODE_SMI 2\r
+#define LOCAL_APIC_DELIVERY_MODE_NMI 4\r
+#define LOCAL_APIC_DELIVERY_MODE_INIT 5\r
+#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6\r
+#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7\r
+\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
+\r
+//\r
+// Local APIC Version Register.\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Version:8; ///< The version numbers of the local APIC.\r
+ UINT32 Reserved0:8; ///< Reserved.\r
+ UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.\r
+ UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.\r
+ UINT32 Reserved1:7; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_VERSION;\r
+\r
+//\r
+// Low half of Interrupt Command Register (ICR).\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
+ UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.\r
+ UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.\r
+ UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r
+ UINT32 Reserved0:1; ///< Reserved.\r
+ UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r
+ UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r
+ UINT32 Reserved1:2; ///< Reserved.\r
+ UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.\r
+ UINT32 Reserved2:12; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_ICR_LOW;\r
+\r
+//\r
+// High half of Interrupt Command Register (ICR)\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Reserved0:24; ///< Reserved.\r
+ UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.\r
+ } Bits;\r
+ UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.\r
+} LOCAL_APIC_ICR_HIGH;\r
+\r
+//\r
+// Spurious-Interrupt Vector Register (SVR)\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 SpuriousVector:8; ///< Spurious Vector.\r
+ UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.\r
+ UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.\r
+ UINT32 Reserved0:2; ///< Reserved.\r
+ UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.\r
+ UINT32 Reserved1:19; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_SVR;\r
+\r
+//\r
+// Divide Configuration Register (DCR)\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.\r
+ UINT32 Reserved0:1; ///< Always 0.\r
+ UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.\r
+ UINT32 Reserved1:28; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_DCR;\r
+\r
+//\r
+// LVT Timer Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
+ UINT32 Reserved0:4; ///< Reserved.\r
+ UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
+ UINT32 Reserved1:3; ///< Reserved.\r
+ UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
+ UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.\r
+ UINT32 Reserved2:14; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_LVT_TIMER;\r
+\r
+//\r
+// LVT LINT0/LINT1 Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
+ UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
+ UINT32 Reserved0:1; ///< Reserved.\r
+ UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
+ UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.\r
+ UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r
+ UINT32 TriggerMode:1; ///< 0:edge, 1:level.\r
+ UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
+ UINT32 Reserved1:15; ///< Reserved.\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_LVT_LINT;\r
+\r
+//\r
+// MSI Address Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Reserved0:2; ///< Reserved\r
+ UINT32 DestinationMode:1; ///< Specifies the Destination Mode.\r
+ UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.\r
+ UINT32 Reserved1:8; ///< Reserved.\r
+ UINT32 DestinationId:8; ///< Specifies the Destination ID.\r
+ UINT32 BaseAddress:12; ///< Must be 0FEEH\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_MSI_ADDRESS;\r
+\r
+//\r
+// MSI Address Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH\r
+ UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
+ UINT32 Reserved0:3; ///< Reserved.\r
+ UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.\r
+ UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.\r
+ UINT32 Reserved1:16; ///< Reserved.\r
+ UINT32 Reserved2:32; ///< Reserved.\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} LOCAL_APIC_MSI_DATA;\r
+\r
+#endif\r
+\r
--- /dev/null
+/** @file\r
+ Microcode Definitions.\r
+\r
+ Microcode Definitions based on contents of the\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+ Volume 3A, Section 9.11 Microcode Definitions\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A,\r
+ June 2016, Chapter 9 Processor Management and Initialization, Section 9-11.\r
+\r
+**/\r
+\r
+#ifndef __INTEL_MICROCODE_H__\r
+#define __INTEL_MICROCODE_H__\r
+\r
+///\r
+/// CPU Microcode Date in BCD format\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 Year:16;\r
+ UINT32 Day:8;\r
+ UINT32 Month:8;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} CPU_MICROCODE_DATE;\r
+\r
+///\r
+/// CPU Microcode Processor Signature format\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 Stepping:4;\r
+ UINT32 Model:4;\r
+ UINT32 Family:4;\r
+ UINT32 Type:2;\r
+ UINT32 Reserved1:2;\r
+ UINT32 ExtendedModel:4;\r
+ UINT32 ExtendedFamily:8;\r
+ UINT32 Reserved2:4;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} CPU_MICROCODE_PROCESSOR_SIGNATURE;\r
+\r
+#pragma pack (1)\r
+\r
+///\r
+/// Microcode Update Format definition\r
+///\r
+typedef struct {\r
+ ///\r
+ /// Version number of the update header\r
+ ///\r
+ UINT32 HeaderVersion;\r
+ ///\r
+ /// Unique version number for the update, the basis for the update\r
+ /// signature provided by the processor to indicate the current update\r
+ /// functioning within the processor. Used by the BIOS to authenticate\r
+ /// the update and verify that the processor loads successfully. The\r
+ /// value in this field cannot be used for processor stepping identification\r
+ /// alone. This is a signed 32-bit number.\r
+ ///\r
+ UINT32 UpdateRevision;\r
+ ///\r
+ /// Date of the update creation in binary format: mmddyyyy (e.g.\r
+ /// 07/18/98 is 07181998H).\r
+ ///\r
+ CPU_MICROCODE_DATE Date;\r
+ ///\r
+ /// Extended family, extended model, type, family, model, and stepping\r
+ /// of processor that requires this particular update revision (e.g.,\r
+ /// 00000650H). Each microcode update is designed specifically for a\r
+ /// given extended family, extended model, type, family, model, and\r
+ /// stepping of the processor.\r
+ /// The BIOS uses the processor signature field in conjunction with the\r
+ /// CPUID instruction to determine whether or not an update is\r
+ /// appropriate to load on a processor. The information encoded within\r
+ /// this field exactly corresponds to the bit representations returned by\r
+ /// the CPUID instruction.\r
+ ///\r
+ CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;\r
+ ///\r
+ /// Checksum of Update Data and Header. Used to verify the integrity of\r
+ /// the update header and data. Checksum is correct when the\r
+ /// summation of all the DWORDs (including the extended Processor\r
+ /// Signature Table) that comprise the microcode update result in\r
+ /// 00000000H.\r
+ ///\r
+ UINT32 Checksum;\r
+ ///\r
+ /// Version number of the loader program needed to correctly load this\r
+ /// update. The initial version is 00000001H\r
+ ///\r
+ UINT32 LoaderRevision;\r
+ ///\r
+ /// Platform type information is encoded in the lower 8 bits of this 4-\r
+ /// byte field. Each bit represents a particular platform type for a given\r
+ /// CPUID. The BIOS uses the processor flags field in conjunction with\r
+ /// the platform Id bits in MSR (17H) to determine whether or not an\r
+ /// update is appropriate to load on a processor. Multiple bits may be set\r
+ /// representing support for multiple platform IDs.\r
+ ///\r
+ UINT32 ProcessorFlags;\r
+ ///\r
+ /// Specifies the size of the encrypted data in bytes, and must be a\r
+ /// multiple of DWORDs. If this value is 00000000H, then the microcode\r
+ /// update encrypted data is 2000 bytes (or 500 DWORDs).\r
+ ///\r
+ UINT32 DataSize;\r
+ ///\r
+ /// Specifies the total size of the microcode update in bytes. It is the\r
+ /// summation of the header size, the encrypted data size and the size of\r
+ /// the optional extended signature table. This value is always a multiple\r
+ /// of 1024.\r
+ ///\r
+ UINT32 TotalSize;\r
+ ///\r
+ /// Reserved fields for future expansion.\r
+ ///\r
+ UINT8 Reserved[12];\r
+} CPU_MICROCODE_HEADER;\r
+\r
+///\r
+/// Extended Signature Table Header Field Definitions\r
+///\r
+typedef struct {\r
+ ///\r
+ /// Specifies the number of extended signature structures (Processor\r
+ /// Signature[n], processor flags[n] and checksum[n]) that exist in this\r
+ /// microcode update\r
+ ///\r
+ UINT32 ExtendedSignatureCount;\r
+ ///\r
+ /// Checksum of update extended processor signature table. Used to\r
+ /// verify the integrity of the extended processor signature table.\r
+ /// Checksum is correct when the summation of the DWORDs that\r
+ /// comprise the extended processor signature table results in\r
+ /// 00000000H.\r
+ ///\r
+ UINT32 ExtendedChecksum;\r
+ ///\r
+ /// Reserved fields.\r
+ ///\r
+ UINT8 Reserved[12];\r
+} CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
+\r
+///\r
+/// Extended Signature Table Field Definitions\r
+///\r
+typedef struct {\r
+ ///\r
+ /// Extended family, extended model, type, family, model, and stepping\r
+ /// of processor that requires this particular update revision (e.g.,\r
+ /// 00000650H). Each microcode update is designed specifically for a\r
+ /// given extended family, extended model, type, family, model, and\r
+ /// stepping of the processor.\r
+ /// The BIOS uses the processor signature field in conjunction with the\r
+ /// CPUID instruction to determine whether or not an update is\r
+ /// appropriate to load on a processor. The information encoded within\r
+ /// this field exactly corresponds to the bit representations returned by\r
+ /// the CPUID instruction.\r
+ ///\r
+ CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;\r
+ ///\r
+ /// Platform type information is encoded in the lower 8 bits of this 4-\r
+ /// byte field. Each bit represents a particular platform type for a given\r
+ /// CPUID. The BIOS uses the processor flags field in conjunction with\r
+ /// the platform Id bits in MSR (17H) to determine whether or not an\r
+ /// update is appropriate to load on a processor. Multiple bits may be set\r
+ /// representing support for multiple platform IDs.\r
+ ///\r
+ UINT32 ProcessorFlag;\r
+ ///\r
+ /// Used by utility software to decompose a microcode update into\r
+ /// multiple microcode updates where each of the new updates is\r
+ /// constructed without the optional Extended Processor Signature\r
+ /// Table.\r
+ /// To calculate the Checksum, substitute the Primary Processor\r
+ /// Signature entry and the Processor Flags entry with the\r
+ /// corresponding Extended Patch entry. Delete the Extended Processor\r
+ /// Signature Table entries. The Checksum is correct when the\r
+ /// summation of all DWORDs that comprise the created Extended\r
+ /// Processor Patch results in 00000000H.\r
+ ///\r
+ UINT32 Checksum;\r
+} CPU_MICROCODE_EXTENDED_TABLE;\r
+\r
+#pragma pack ()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 ~ 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __INTEL_MSR_H__\r
+#define __INTEL_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+#include <Register/Intel/Msr/Core2Msr.h>\r
+#include <Register/Intel/Msr/AtomMsr.h>\r
+#include <Register/Intel/Msr/SilvermontMsr.h>\r
+#include <Register/Intel/Msr/GoldmontMsr.h>\r
+#include <Register/Intel/Msr/GoldmontPlusMsr.h>\r
+#include <Register/Intel/Msr/NehalemMsr.h>\r
+#include <Register/Intel/Msr/Xeon5600Msr.h>\r
+#include <Register/Intel/Msr/XeonE7Msr.h>\r
+#include <Register/Intel/Msr/SandyBridgeMsr.h>\r
+#include <Register/Intel/Msr/IvyBridgeMsr.h>\r
+#include <Register/Intel/Msr/HaswellMsr.h>\r
+#include <Register/Intel/Msr/HaswellEMsr.h>\r
+#include <Register/Intel/Msr/BroadwellMsr.h>\r
+#include <Register/Intel/Msr/XeonDMsr.h>\r
+#include <Register/Intel/Msr/SkylakeMsr.h>\r
+#include <Register/Intel/Msr/XeonPhiMsr.h>\r
+#include <Register/Intel/Msr/Pentium4Msr.h>\r
+#include <Register/Intel/Msr/CoreMsr.h>\r
+#include <Register/Intel/Msr/PentiumMMsr.h>\r
+#include <Register/Intel/Msr/P6Msr.h>\r
+#include <Register/Intel/Msr/PentiumMsr.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for the Intel(R) Atom(TM) Processor Family.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __ATOM_MSR_H__\r
+#define __ATOM_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel(R) Atom(TM) Processor Family?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x1C || \\r
+ DisplayModel == 0x26 || \\r
+ DisplayModel == 0x27 || \\r
+ DisplayModel == 0x35 || \\r
+ DisplayModel == 0x36 \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Shared. Model Specific Platform ID (R).\r
+\r
+ @param ECX MSR_ATOM_PLATFORM_ID (0x00000017)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_ATOM_PLATFORM_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);\r
+ @endcode\r
+ @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
+**/\r
+#define MSR_ATOM_PLATFORM_ID 0x00000017\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
+ ///\r
+ UINT32 MaximumQualifiedRatio:5;\r
+ UINT32 Reserved2:19;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_ATOM_PLATFORM_ID_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
+ processor features; (R) indicates current processor configuration.\r
+\r
+ @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);\r
+ AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
+**/\r
+#define MSR_ATOM_EBL_CR_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
+ /// Always 0.\r
+ ///\r
+ UINT32 DataErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
+ /// Always 0.\r
+ ///\r
+ UINT32 ResponseErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
+ ///\r
+ UINT32 AERR_DriveEnable:1;\r
+ ///\r
+ /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =\r
+ /// Disabled Always 0.\r
+ ///\r
+ UINT32 BERR_Enable:1;\r
+ UINT32 Reserved2:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
+ ///\r
+ UINT32 BINIT_DriverEnable:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 ExecuteBIST:1;\r
+ ///\r
+ /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
+ /// Always 0.\r
+ ///\r
+ UINT32 AERR_ObservationEnabled:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
+ /// Always 0.\r
+ ///\r
+ UINT32 BINIT_ObservationEnabled:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
+ ///\r
+ UINT32 ResetVector:1;\r
+ UINT32 Reserved7:1;\r
+ ///\r
+ /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.\r
+ ///\r
+ UINT32 APICClusterID:2;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.\r
+ ///\r
+ UINT32 SymmetricArbitrationID:2;\r
+ ///\r
+ /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
+ ///\r
+ UINT32 IntegerBusFrequencyRatio:5;\r
+ UINT32 Reserved9:5;\r
+ UINT32 Reserved10:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_ATOM_EBL_CR_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
+ record registers on the last branch record stack. The From_IP part of the\r
+ stack contains pointers to the source instruction . See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.5.\r
+\r
+ @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);\r
+ AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);\r
+ @endcode\r
+ @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040\r
+#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041\r
+#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042\r
+#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043\r
+#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044\r
+#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045\r
+#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046\r
+#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
+ record registers on the last branch record stack. The To_IP part of the\r
+ stack contains pointers to the destination instruction.\r
+\r
+ @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);\r
+ AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);\r
+ @endcode\r
+ @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
+ MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060\r
+#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061\r
+#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062\r
+#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063\r
+#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064\r
+#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065\r
+#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066\r
+#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067\r
+/// @}\r
+\r
+\r
+/**\r
+ Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
+ bus clock speed for processors based on Intel Atom microarchitecture:.\r
+\r
+ @param ECX MSR_ATOM_FSB_FREQ (0x000000CD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_FSB_FREQ_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_FSB_FREQ_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_ATOM_FSB_FREQ_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);\r
+ @endcode\r
+ @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
+**/\r
+#define MSR_ATOM_FSB_FREQ 0x000000CD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_ATOM_FSB_FREQ\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] - Scalable Bus Speed\r
+ ///\r
+ /// Atom Processor Family\r
+ /// ---------------------\r
+ /// 111B: 083 MHz (FSB 333)\r
+ /// 101B: 100 MHz (FSB 400)\r
+ /// 001B: 133 MHz (FSB 533)\r
+ /// 011B: 167 MHz (FSB 667)\r
+ ///\r
+ /// 133.33 MHz should be utilized if performing calculation with\r
+ /// System Bus Speed when encoding is 001B.\r
+ /// 166.67 MHz should be utilized if performing calculation with\r
+ /// System Bus Speed when\r
+ /// encoding is 011B.\r
+ ///\r
+ UINT32 ScalableBusSpeed:3;\r
+ UINT32 Reserved1:29;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_ATOM_FSB_FREQ_REGISTER;\r
+\r
+\r
+/**\r
+ Shared.\r
+\r
+ @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);\r
+ AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
+**/\r
+#define MSR_ATOM_BBL_CR_CTL3 0x0000011E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
+ /// Indicates if the L2 is hardware-disabled.\r
+ ///\r
+ UINT32 L2HardwareEnabled:1;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r
+ /// Disabled (default) Until this bit is set the processor will not\r
+ /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
+ ///\r
+ UINT32 L2Enabled:1;\r
+ UINT32 Reserved2:14;\r
+ ///\r
+ /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
+ ///\r
+ UINT32 L2NotPresent:1;\r
+ UINT32 Reserved3:8;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_ATOM_BBL_CR_CTL3_REGISTER;\r
+\r
+\r
+/**\r
+ Shared.\r
+\r
+ @param ECX MSR_ATOM_PERF_STATUS (0x00000198)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_PERF_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_PERF_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_ATOM_PERF_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);\r
+ AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_ATOM_PERF_STATUS 0x00000198\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_ATOM_PERF_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Current Performance State Value.\r
+ ///\r
+ UINT32 CurrentPerformanceStateValue:16;\r
+ UINT32 Reserved1:16;\r
+ UINT32 Reserved2:8;\r
+ ///\r
+ /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r
+ /// configured for the processor.\r
+ ///\r
+ UINT32 MaximumBusRatio:5;\r
+ UINT32 Reserved3:19;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_ATOM_PERF_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Shared.\r
+\r
+ @param ECX MSR_ATOM_THERM2_CTL (0x0000019D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_THERM2_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_THERM2_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_ATOM_THERM2_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);\r
+ AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
+**/\r
+#define MSR_ATOM_THERM2_CTL 0x0000019D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_ATOM_THERM2_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
+ /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
+ /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
+ /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
+ /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r
+ ///\r
+ UINT32 TM_SELECT:1;\r
+ UINT32 Reserved2:15;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_ATOM_THERM2_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fast-Strings Enable See Table 2-2.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
+ /// Table 2-2. Default value is 0.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
+ /// the processor to indicate a pending break event within the processor 0\r
+ /// = Indicates compatible FERR# signaling behavior This bit must be set\r
+ /// to 1 to support XAPIC interrupt model usage.\r
+ ///\r
+ UINT32 FERR:1;\r
+ ///\r
+ /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ ///\r
+ /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
+ /// thermal sensor indicates that the die temperature is at the\r
+ /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r
+ /// TM2 will reduce the bus to core ratio and voltage according to the\r
+ /// value last written to MSR_THERM2_CTL bits 15:0.\r
+ /// When this bit is clear (0, default), the processor does not change\r
+ /// the VID signals or the bus to core ratio when the processor enters a\r
+ /// thermally managed state. The BIOS must enable this feature if the\r
+ /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is\r
+ /// not set, this feature is not supported and BIOS must not alter the\r
+ /// contents of the TM2 bit location. The processor is operating out of\r
+ /// specification if both this bit and the TM1 bit are set to 0.\r
+ ///\r
+ UINT32 TM2:1;\r
+ UINT32 Reserved5:2;\r
+ ///\r
+ /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ UINT32 Reserved7:1;\r
+ ///\r
+ /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r
+ /// (R/WO) When set, this bit causes the following bits to become\r
+ /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this\r
+ /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must\r
+ /// be set before an Enhanced Intel SpeedStep Technology transition is\r
+ /// requested. This bit is cleared on reset.\r
+ ///\r
+ UINT32 EISTLock:1;\r
+ UINT32 Reserved8:1;\r
+ ///\r
+ /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved9:8;\r
+ UINT32 Reserved10:2;\r
+ ///\r
+ /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved11:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)\r
+ that points to the MSR containing the most recent branch record. See\r
+ MSR_LASTBRANCH_0_FROM_IP (at 40H).\r
+\r
+ @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
+ last branch instruction that the processor executed prior to the last\r
+ exception that was generated or the last interrupt that was handled.\r
+\r
+ @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);\r
+ @endcode\r
+ @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
+**/\r
+#define MSR_ATOM_LER_FROM_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
+ to the target of the last branch instruction that the processor executed\r
+ prior to the last exception that was generated or the last interrupt that\r
+ was handled.\r
+\r
+ @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);\r
+ @endcode\r
+ @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
+**/\r
+#define MSR_ATOM_LER_TO_LIP 0x000001DE\r
+\r
+\r
+/**\r
+ Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
+ (PEBS).".\r
+\r
+ @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_ATOM_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
+**/\r
+#define MSR_ATOM_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 Enable:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_ATOM_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Package C2 Residency Note: C-state values are processor specific\r
+ C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
+ C-States. Package. Package C2 Residency Counter. (R/O) Time that this\r
+ package is in processor-specific C2 states since last reset. Counts at 1 Mhz\r
+ frequency.\r
+\r
+ @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
+**/\r
+#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8\r
+\r
+\r
+/**\r
+ Package. Package C4 Residency Note: C-state values are processor specific\r
+ C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
+ C-States. Package. Package C4 Residency Counter. (R/O) Time that this\r
+ package is in processor-specific C4 states since last reset. Counts at 1 Mhz\r
+ frequency.\r
+\r
+ @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.\r
+**/\r
+#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9\r
+\r
+\r
+/**\r
+ Package. Package C6 Residency Note: C-state values are processor specific\r
+ C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
+ C-States. Package. Package C6 Residency Counter. (R/O) Time that this\r
+ package is in processor-specific C6 states since last reset. Counts at 1 Mhz\r
+ frequency.\r
+\r
+ @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __BROADWELL_MSR_H__\r
+#define __BROADWELL_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel processors based on the Broadwell microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x3D || \\r
+ DisplayModel == 0x47 || \\r
+ DisplayModel == 0x4F || \\r
+ DisplayModel == 0x56 \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
+ Facilities.".\r
+\r
+ @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Ovf_PMC0.\r
+ ///\r
+ UINT32 Ovf_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Ovf_PMC1.\r
+ ///\r
+ UINT32 Ovf_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Ovf_PMC2.\r
+ ///\r
+ UINT32 Ovf_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Ovf_PMC3.\r
+ ///\r
+ UINT32 Ovf_PMC3:1;\r
+ UINT32 Reserved1:28;\r
+ ///\r
+ /// [Bit 32] Ovf_FixedCtr0.\r
+ ///\r
+ UINT32 Ovf_FixedCtr0:1;\r
+ ///\r
+ /// [Bit 33] Ovf_FixedCtr1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr1:1;\r
+ ///\r
+ /// [Bit 34] Ovf_FixedCtr2.\r
+ ///\r
+ UINT32 Ovf_FixedCtr2:1;\r
+ UINT32 Reserved2:20;\r
+ ///\r
+ /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
+ /// Addresses (ToPA).".\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved3:5;\r
+ ///\r
+ /// [Bit 61] Ovf_Uncore.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Ovf_BufDSSAVE.\r
+ ///\r
+ UINT32 OvfBuf:1;\r
+ ///\r
+ /// [Bit 63] CondChgd.\r
+ ///\r
+ UINT32 CondChgd:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
+\r
+ @param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
+**/\r
+#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power) for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 0000b:\r
+ /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
+ /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r
+ ///\r
+ UINT32 Limit:4;\r
+ UINT32 Reserved1:6;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:9;\r
+ ///\r
+ /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C3AutoDemotion:1;\r
+ ///\r
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C1AutoDemotion:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r
+ ///\r
+ UINT32 CStateAutoDemotion:1;\r
+ ///\r
+ /// [Bit 30] Enable Package C-State Undemotion (R/W).\r
+ ///\r
+ UINT32 CStateUndemotion:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+ @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
+ /// limit of 5core active.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
+ /// limit of 6core active.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
+ fields represent the widest possible range of uncore frequencies. Writing to\r
+ these fields allows software to control the minimum and the maximum\r
+ frequency that hardware will select.\r
+\r
+ @param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 MAX_RATIO:7;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 MIN_RATIO:7;\r
+ UINT32 Reserved3:17;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __CORE2_MSR_H__\r
+#define __CORE2_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel(R) Core(TM) 2 Processor Family?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x0F || \\r
+ DisplayModel == 0x17 \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Shared. Model Specific Platform ID (R).\r
+\r
+ @param ECX MSR_CORE2_PLATFORM_ID (0x00000017)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_PLATFORM_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);\r
+ @endcode\r
+ @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
+**/\r
+#define MSR_CORE2_PLATFORM_ID 0x00000017\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
+ ///\r
+ UINT32 MaximumQualifiedRatio:5;\r
+ UINT32 Reserved2:19;\r
+ UINT32 Reserved3:18;\r
+ ///\r
+ /// [Bits 52:50] See Table 2-2.\r
+ ///\r
+ UINT32 PlatformId:3;\r
+ UINT32 Reserved4:11;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_PLATFORM_ID_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
+ processor features; (R) indicates current processor configuration.\r
+\r
+ @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_EBL_CR_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);\r
+ AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
+**/\r
+#define MSR_CORE2_EBL_CR_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
+ /// Note: Not all processor implements R/W.\r
+ ///\r
+ UINT32 DataErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
+ /// Note: Not all processor implements R/W.\r
+ ///\r
+ UINT32 ResponseErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
+ /// all processor implements R/W.\r
+ ///\r
+ UINT32 MCERR_DriveEnable:1;\r
+ ///\r
+ /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r
+ /// Not all processor implements R/W.\r
+ ///\r
+ UINT32 AddressParityEnable:1;\r
+ UINT32 Reserved2:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
+ /// all processor implements R/W.\r
+ ///\r
+ UINT32 BINIT_DriverEnable:1;\r
+ ///\r
+ /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 OutputTriStateEnable:1;\r
+ ///\r
+ /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 ExecuteBIST:1;\r
+ ///\r
+ /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 MCERR_ObservationEnabled:1;\r
+ ///\r
+ /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.\r
+ ///\r
+ UINT32 IntelTXTCapableChipset:1;\r
+ ///\r
+ /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 BINIT_ObservationEnabled:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
+ ///\r
+ UINT32 ResetVector:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bits 17:16] APIC Cluster ID (R/O).\r
+ ///\r
+ UINT32 APICClusterID:2;\r
+ ///\r
+ /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =\r
+ /// Non-integer ratio.\r
+ ///\r
+ UINT32 NonIntegerBusRatio:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bits 21:20] Symmetric Arbitration ID (R/O).\r
+ ///\r
+ UINT32 SymmetricArbitrationID:2;\r
+ ///\r
+ /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
+ ///\r
+ UINT32 IntegerBusFrequencyRatio:5;\r
+ UINT32 Reserved7:5;\r
+ UINT32 Reserved8:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_EBL_CR_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.\r
+\r
+ @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_CORE2_FEATURE_CONTROL 0x0000003A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock\r
+ /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read\r
+ /// visible and writeable while in SMM.\r
+ ///\r
+ UINT32 SMRREnable:1;\r
+ UINT32 Reserved2:28;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch\r
+ record registers on the last branch record stack. The From_IP part of the\r
+ stack contains pointers to the source instruction. See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.5.\r
+\r
+ @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);\r
+ AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);\r
+ @endcode\r
+ @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040\r
+#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041\r
+#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042\r
+#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch\r
+ record registers on the last branch record stack. This To_IP part of the\r
+ stack contains pointers to the destination instruction.\r
+\r
+ @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);\r
+ AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);\r
+ @endcode\r
+ @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060\r
+#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061\r
+#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062\r
+#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique. System Management Mode Base Address register (WO in SMM)\r
+ Model-specific implementation of SMRR-like interface, read visible and write\r
+ only in SMM.\r
+\r
+ @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = 0;\r
+ AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.\r
+**/\r
+#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:12;\r
+ ///\r
+ /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r
+ ///\r
+ UINT32 PhysBase:20;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_SMRR_PHYSBASE_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. System Management Mode Physical Address Mask register (WO in SMM)\r
+ Model-specific implementation of SMRR-like interface, read visible and write\r
+ only in SMM.\r
+\r
+ @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = 0;\r
+ AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.\r
+**/\r
+#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:11;\r
+ ///\r
+ /// [Bit 11] Valid. Physical address base and range mask are valid.\r
+ ///\r
+ UINT32 Valid:1;\r
+ ///\r
+ /// [Bits 31:12] PhysMask. SMRR physical address range mask.\r
+ ///\r
+ UINT32 PhysMask:20;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_SMRR_PHYSMASK_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
+ bus clock speed for processors based on Intel Core microarchitecture:.\r
+\r
+ @param ECX MSR_CORE2_FSB_FREQ (0x000000CD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_FSB_FREQ_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_FSB_FREQ_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_FSB_FREQ_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);\r
+ @endcode\r
+ @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
+**/\r
+#define MSR_CORE2_FSB_FREQ 0x000000CD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_FSB_FREQ\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] - Scalable Bus Speed\r
+ /// 101B: 100 MHz (FSB 400)\r
+ /// 001B: 133 MHz (FSB 533)\r
+ /// 011B: 167 MHz (FSB 667)\r
+ /// 010B: 200 MHz (FSB 800)\r
+ /// 000B: 267 MHz (FSB 1067)\r
+ /// 100B: 333 MHz (FSB 1333)\r
+ ///\r
+ /// 133.33 MHz should be utilized if performing calculation with System\r
+ /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if\r
+ /// performing calculation with System Bus Speed when encoding is 011B.\r
+ /// 266.67 MHz should be utilized if performing calculation with System\r
+ /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if\r
+ /// performing calculation with System Bus Speed when encoding is 100B.\r
+ ///\r
+ UINT32 ScalableBusSpeed:3;\r
+ UINT32 Reserved1:29;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_FSB_FREQ_REGISTER;\r
+\r
+/**\r
+ Shared.\r
+\r
+ @param ECX MSR_CORE2_PERF_STATUS (0x00000198)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PERF_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PERF_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_PERF_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_CORE2_PERF_STATUS 0x00000198\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_PERF_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Current Performance State Value.\r
+ ///\r
+ UINT32 CurrentPerformanceStateValue:16;\r
+ UINT32 Reserved1:15;\r
+ ///\r
+ /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default\r
+ /// is cleared.\r
+ ///\r
+ UINT32 XEOperation:1;\r
+ UINT32 Reserved2:8;\r
+ ///\r
+ /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r
+ /// configured for the processor.\r
+ ///\r
+ UINT32 MaximumBusRatio:5;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio\r
+ /// is enabled. Applies processors based on Enhanced Intel Core\r
+ /// microarchitecture.\r
+ ///\r
+ UINT32 NonIntegerBusRatio:1;\r
+ UINT32 Reserved4:17;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_PERF_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE2_THERM2_CTL (0x0000019D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_THERM2_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_THERM2_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_THERM2_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);\r
+ AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
+**/\r
+#define MSR_CORE2_THERM2_CTL 0x0000019D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_THERM2_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
+ /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
+ /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
+ /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
+ /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r
+ ///\r
+ UINT32 TM_SELECT:1;\r
+ UINT32 Reserved2:15;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_THERM2_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fast-Strings Enable See Table 2-2.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the\r
+ /// hardware prefetcher operation on streams of data. When clear\r
+ /// (default), enables the prefetch queue. Disabling of the hardware\r
+ /// prefetcher may impact processor performance.\r
+ ///\r
+ UINT32 HardwarePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
+ /// the processor to indicate a pending break event within the processor 0\r
+ /// = Indicates compatible FERR# signaling behavior This bit must be set\r
+ /// to 1 to support XAPIC interrupt model usage.\r
+ ///\r
+ UINT32 FERR:1;\r
+ ///\r
+ /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ ///\r
+ /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
+ /// thermal sensor indicates that the die temperature is at the\r
+ /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r
+ /// TM2 will reduce the bus to core ratio and voltage according to the\r
+ /// value last written to MSR_THERM2_CTL bits 15:0.\r
+ /// When this bit is clear (0, default), the processor does not change\r
+ /// the VID signals or the bus to core ratio when the processor enters a\r
+ /// thermally managed state. The BIOS must enable this feature if the\r
+ /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is\r
+ /// not set, this feature is not supported and BIOS must not alter the\r
+ /// contents of the TM2 bit location. The processor is operating out of\r
+ /// specification if both this bit and the TM1 bit are set to 0.\r
+ ///\r
+ UINT32 TM2:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ ///\r
+ /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set\r
+ /// to 1, the processor fetches the cache line that contains data\r
+ /// currently required by the processor. When set to 0, the processor\r
+ /// fetches cache lines that comprise a cache line pair (128 bytes).\r
+ /// Single processor platforms should not set this bit. Server platforms\r
+ /// should set or clear this bit based on platform performance observed in\r
+ /// validation and testing. BIOS may contain a setup option that controls\r
+ /// the setting of this bit.\r
+ ///\r
+ UINT32 AdjacentCacheLinePrefetchDisable:1;\r
+ ///\r
+ /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r
+ /// (R/WO) When set, this bit causes the following bits to become\r
+ /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this\r
+ /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must\r
+ /// be set before an Enhanced Intel SpeedStep Technology transition is\r
+ /// requested. This bit is cleared on reset.\r
+ ///\r
+ UINT32 EISTLock:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved7:8;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved9:2;\r
+ ///\r
+ /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU\r
+ /// L1 data cache prefetcher is disabled. The default value after reset is\r
+ /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is\r
+ /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple\r
+ /// loads from the same line done within a time limit, the DCU prefetcher\r
+ /// assumes the next line will be required. The next line is prefetched in\r
+ /// to the L1 data cache from memory or L2.\r
+ ///\r
+ UINT32 DCUPrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that\r
+ /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled\r
+ /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).\r
+ /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]\r
+ /// reports the processor's support of IDA is enabled. Note: the power-on\r
+ /// default value is used by BIOS to detect hardware support of IDA. If\r
+ /// power-on default value is 1, IDA is available in the processor. If\r
+ /// power-on default value is 0, IDA is not available.\r
+ ///\r
+ UINT32 IDADisable:1;\r
+ ///\r
+ /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP\r
+ /// prefetcher is disabled. The default value after reset is 0. BIOS may\r
+ /// write '1' to disable this feature. The IP prefetcher is an L1 data\r
+ /// cache prefetcher. The IP prefetcher looks for sequential load history\r
+ /// to determine whether to prefetch the next expected data into the L1\r
+ /// cache from memory or L2.\r
+ ///\r
+ UINT32 IPPrefetcherDisable:1;\r
+ UINT32 Reserved10:24;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
+ that points to the MSR containing the most recent branch record. See\r
+ MSR_LASTBRANCH_0_FROM_IP (at 40H).\r
+\r
+ @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
+ last branch instruction that the processor executed prior to the last\r
+ exception that was generated or the last interrupt that was handled.\r
+\r
+ @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);\r
+ @endcode\r
+ @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
+**/\r
+#define MSR_CORE2_LER_FROM_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
+ to the target of the last branch instruction that the processor executed\r
+ prior to the last exception that was generated or the last interrupt that\r
+ was handled.\r
+\r
+ @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);\r
+ @endcode\r
+ @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
+**/\r
+#define MSR_CORE2_LER_TO_LIP 0x000001DE\r
+\r
+\r
+/**\r
+ Unique. Fixed-Function Performance Counter Register n (R/W).\r
+\r
+ @param ECX MSR_CORE2_PERF_FIXED_CTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.\r
+ MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.\r
+ MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.\r
+ @{\r
+**/\r
+#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309\r
+#define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A\r
+#define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique. RO. This applies to processors that do not support architectural\r
+ perfmon version 2.\r
+\r
+ @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.\r
+**/\r
+#define MSR_CORE2_PERF_CAPABILITIES 0x00000345\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 5:0] LBR Format. See Table 2-2.\r
+ ///\r
+ UINT32 LBR_FMT:6;\r
+ ///\r
+ /// [Bit 6] PEBS Record Format.\r
+ ///\r
+ UINT32 PEBS_FMT:1;\r
+ ///\r
+ /// [Bit 7] PEBSSaveArchRegs. See Table 2-2.\r
+ ///\r
+ UINT32 PEBS_ARCH_REG:1;\r
+ UINT32 Reserved1:24;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_PERF_CAPABILITIES_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Fixed-Function-Counter Control Register (R/W).\r
+\r
+ @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.\r
+**/\r
+#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D\r
+\r
+\r
+/**\r
+ Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
+\r
+ @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E\r
+\r
+\r
+/**\r
+ Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
+\r
+ @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.\r
+**/\r
+#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F\r
+\r
+\r
+/**\r
+ Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
+\r
+ @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390\r
+\r
+\r
+/**\r
+ Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
+ (PEBS).".\r
+\r
+ @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
+**/\r
+#define MSR_CORE2_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 Enable:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon\r
+ processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
+\r
+ @param ECX MSR_CORE2_EMON_L3_CTR_CTLn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);\r
+ AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);\r
+ @endcode\r
+ @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC\r
+#define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD\r
+#define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE\r
+#define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF\r
+#define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0\r
+#define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1\r
+#define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2\r
+#define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor\r
+ 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
+\r
+ @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);\r
+ AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);\r
+ @endcode\r
+ @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.\r
+**/\r
+#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel Core Solo and Intel Core Duo Processors.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __CORE_MSR_H__\r
+#define __CORE_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel Core Solo and Intel Core Duo Processors?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x0E \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.\r
+\r
+ @param ECX MSR_CORE_P5_MC_ADDR (0x00000000)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);\r
+ AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
+**/\r
+#define MSR_CORE_P5_MC_ADDR 0x00000000\r
+\r
+\r
+/**\r
+ Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.\r
+\r
+ @param ECX MSR_CORE_P5_MC_TYPE (0x00000001)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);\r
+ AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);\r
+ @endcode\r
+ @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
+**/\r
+#define MSR_CORE_P5_MC_TYPE 0x00000001\r
+\r
+\r
+/**\r
+ Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
+ processor features; (R) indicates current processor configuration.\r
+\r
+ @param ECX MSR_CORE_EBL_CR_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE_EBL_CR_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);\r
+ AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
+**/\r
+#define MSR_CORE_EBL_CR_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
+ /// Note: Not all processor implements R/W.\r
+ ///\r
+ UINT32 DataErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
+ /// Note: Not all processor implements R/W.\r
+ ///\r
+ UINT32 ResponseErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
+ /// all processor implements R/W.\r
+ ///\r
+ UINT32 MCERR_DriveEnable:1;\r
+ ///\r
+ /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r
+ /// Not all processor implements R/W.\r
+ ///\r
+ UINT32 AddressParityEnable:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
+ /// all processor implements R/W.\r
+ ///\r
+ UINT32 BINIT_DriverEnable:1;\r
+ ///\r
+ /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 OutputTriStateEnable:1;\r
+ ///\r
+ /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 ExecuteBIST:1;\r
+ ///\r
+ /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 MCERR_ObservationEnabled:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 BINIT_ObservationEnabled:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
+ ///\r
+ UINT32 ResetVector:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bits 17:16] APIC Cluster ID (R/O).\r
+ ///\r
+ UINT32 APICClusterID:2;\r
+ ///\r
+ /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.\r
+ ///\r
+ UINT32 SystemBusFrequency:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bits 21:20] Symmetric Arbitration ID (R/O).\r
+ ///\r
+ UINT32 SymmetricArbitrationID:2;\r
+ ///\r
+ /// [Bits 26:22] Clock Frequency Ratio (R/O).\r
+ ///\r
+ UINT32 ClockFrequencyRatio:5;\r
+ UINT32 Reserved7:5;\r
+ UINT32 Reserved8:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE_EBL_CR_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record n (R/W) One of 8 last branch record registers on\r
+ the last branch record stack: bits 31-0 hold the 'from' address and bits\r
+ 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at\r
+ 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording\r
+ (Pentium M Processors).".\r
+\r
+ @param ECX MSR_CORE_LASTBRANCH_n\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);\r
+ AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);\r
+ @endcode\r
+ @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
+ MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
+ MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
+ MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
+ MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
+ MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
+ MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
+ MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_CORE_LASTBRANCH_0 0x00000040\r
+#define MSR_CORE_LASTBRANCH_1 0x00000041\r
+#define MSR_CORE_LASTBRANCH_2 0x00000042\r
+#define MSR_CORE_LASTBRANCH_3 0x00000043\r
+#define MSR_CORE_LASTBRANCH_4 0x00000044\r
+#define MSR_CORE_LASTBRANCH_5 0x00000045\r
+#define MSR_CORE_LASTBRANCH_6 0x00000046\r
+#define MSR_CORE_LASTBRANCH_7 0x00000047\r
+/// @}\r
+\r
+\r
+/**\r
+ Shared. Scalable Bus Speed (RO) This field indicates the scalable bus\r
+ clock speed:.\r
+\r
+ @param ECX MSR_CORE_FSB_FREQ (0x000000CD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE_FSB_FREQ_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE_FSB_FREQ_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE_FSB_FREQ_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);\r
+ @endcode\r
+ @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
+**/\r
+#define MSR_CORE_FSB_FREQ 0x000000CD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE_FSB_FREQ\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] - Scalable Bus Speed\r
+ /// 101B: 100 MHz (FSB 400)\r
+ /// 001B: 133 MHz (FSB 533)\r
+ /// 011B: 167 MHz (FSB 667)\r
+ ///\r
+ /// 133.33 MHz should be utilized if performing calculation with System Bus\r
+ /// Speed when encoding is 101B. 166.67 MHz should be utilized if\r
+ /// performing calculation with System Bus Speed when encoding is 001B.\r
+ ///\r
+ UINT32 ScalableBusSpeed:3;\r
+ UINT32 Reserved1:29;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE_FSB_FREQ_REGISTER;\r
+\r
+\r
+/**\r
+ Shared.\r
+\r
+ @param ECX MSR_CORE_BBL_CR_CTL3 (0x0000011E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE_BBL_CR_CTL3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);\r
+ AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
+**/\r
+#define MSR_CORE_BBL_CR_CTL3 0x0000011E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
+ /// Indicates if the L2 is hardware-disabled.\r
+ ///\r
+ UINT32 L2HardwareEnabled:1;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
+ /// Disabled (default) Until this bit is set the processor will not\r
+ /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
+ ///\r
+ UINT32 L2Enabled:1;\r
+ UINT32 Reserved2:14;\r
+ ///\r
+ /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
+ ///\r
+ UINT32 L2NotPresent:1;\r
+ UINT32 Reserved3:8;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE_BBL_CR_CTL3_REGISTER;\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_THERM2_CTL (0x0000019D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE_THERM2_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE_THERM2_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE_THERM2_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);\r
+ AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
+**/\r
+#define MSR_CORE_THERM2_CTL 0x0000019D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE_THERM2_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
+ /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
+ /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
+ /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
+ /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
+ ///\r
+ UINT32 TM_SELECT:1;\r
+ UINT32 Reserved2:15;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE_THERM2_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_CORE_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
+ /// the processor to indicate a pending break event within the processor 0\r
+ /// = Indicates compatible FERR# signaling behavior This bit must be set\r
+ /// to 1 to support XAPIC interrupt model usage.\r
+ ///\r
+ UINT32 FERR:1;\r
+ ///\r
+ /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
+ ///\r
+ UINT32 BTS:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
+ /// thermal sensor indicates that the die temperature is at the\r
+ /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r
+ /// TM2 will reduce the bus to core ratio and voltage according to the\r
+ /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear\r
+ /// (0, default), the processor does not change the VID signals or the bus\r
+ /// to core ratio when the processor enters a thermal managed state. If\r
+ /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID\r
+ /// with EAX = 1, then this feature is not supported and BIOS must not\r
+ /// alter the contents of this bit location. The processor is operating\r
+ /// out of spec if both this bit and the TM1 bit are set to disabled\r
+ /// states.\r
+ ///\r
+ UINT32 TM2:1;\r
+ UINT32 Reserved5:2;\r
+ ///\r
+ /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
+ /// Enhanced Intel SpeedStep Technology enabled.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ UINT32 Reserved7:1;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this\r
+ /// bit may cause behavior in software that depends on the availability of\r
+ /// CPUID leaves greater than 2.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ UINT32 Reserved9:9;\r
+ UINT32 Reserved10:2;\r
+ ///\r
+ /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved11:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
+ that points to the MSR containing the most recent branch record. See\r
+ MSR_LASTBRANCH_0_FROM_IP (at 40H).\r
+\r
+ @param ECX MSR_CORE_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_CORE_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
+ last branch instruction that the processor executed prior to the last\r
+ exception that was generated or the last interrupt that was handled.\r
+\r
+ @param ECX MSR_CORE_LER_FROM_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);\r
+ @endcode\r
+ @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
+**/\r
+#define MSR_CORE_LER_FROM_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
+ to the target of the last branch instruction that the processor executed\r
+ prior to the last exception that was generated or the last interrupt that\r
+ was handled.\r
+\r
+ @param ECX MSR_CORE_LER_TO_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);\r
+ @endcode\r
+ @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
+**/\r
+#define MSR_CORE_LER_TO_LIP 0x000001DE\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRPHYSBASEn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_CORE_MTRRPHYSBASE0 0x00000200\r
+#define MSR_CORE_MTRRPHYSBASE1 0x00000202\r
+#define MSR_CORE_MTRRPHYSBASE2 0x00000204\r
+#define MSR_CORE_MTRRPHYSBASE3 0x00000206\r
+#define MSR_CORE_MTRRPHYSBASE4 0x00000208\r
+#define MSR_CORE_MTRRPHYSBASE5 0x0000020A\r
+#define MSR_CORE_MTRRPHYSMASK6 0x0000020D\r
+#define MSR_CORE_MTRRPHYSMASK7 0x0000020F\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRPHYSMASKn (0x00000201)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.\r
+ MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.\r
+ MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_CORE_MTRRPHYSMASK0 0x00000201\r
+#define MSR_CORE_MTRRPHYSMASK1 0x00000203\r
+#define MSR_CORE_MTRRPHYSMASK2 0x00000205\r
+#define MSR_CORE_MTRRPHYSMASK3 0x00000207\r
+#define MSR_CORE_MTRRPHYSMASK4 0x00000209\r
+#define MSR_CORE_MTRRPHYSMASK5 0x0000020B\r
+#define MSR_CORE_MTRRPHYSBASE6 0x0000020C\r
+#define MSR_CORE_MTRRPHYSBASE7 0x0000020E\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX64K_00000 (0x00000250)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX64K_00000 0x00000250\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX16K_80000 (0x00000258)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX16K_80000 0x00000258\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX16K_A0000 (0x00000259)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX16K_A0000 0x00000259\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX4K_C0000 (0x00000268)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX4K_C0000 0x00000268\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX4K_C8000 (0x00000269)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX4K_C8000 0x00000269\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);\r
+ AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r
+**/\r
+#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F\r
+\r
+\r
+/**\r
+ Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
+\r
+ @param ECX MSR_CORE_MC4_CTL (0x0000040C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);\r
+ AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
+**/\r
+#define MSR_CORE_MC4_CTL 0x0000040C\r
+\r
+\r
+/**\r
+ Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
+\r
+ @param ECX MSR_CORE_MC4_STATUS (0x0000040D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
+**/\r
+#define MSR_CORE_MC4_STATUS 0x0000040D\r
+\r
+\r
+/**\r
+ Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
+ register is either not implemented or contains no address if the ADDRV flag\r
+ in the MSR_MC4_STATUS register is clear. When not implemented in the\r
+ processor, all reads and writes to this MSR will cause a general-protection\r
+ exception.\r
+\r
+ @param ECX MSR_CORE_MC4_ADDR (0x0000040E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);\r
+ AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
+**/\r
+#define MSR_CORE_MC4_ADDR 0x0000040E\r
+\r
+\r
+/**\r
+ Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
+ register is either not implemented or contains no address if the ADDRV flag\r
+ in the MSR_MC3_STATUS register is clear. When not implemented in the\r
+ processor, all reads and writes to this MSR will cause a general-protection\r
+ exception.\r
+\r
+ @param ECX MSR_CORE_MC3_ADDR (0x00000412)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);\r
+ AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
+**/\r
+#define MSR_CORE_MC3_ADDR 0x00000412\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MC3_MISC (0x00000413)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);\r
+ AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.\r
+**/\r
+#define MSR_CORE_MC3_MISC 0x00000413\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MC5_CTL (0x00000414)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);\r
+ AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
+**/\r
+#define MSR_CORE_MC5_CTL 0x00000414\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MC5_STATUS (0x00000415)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
+**/\r
+#define MSR_CORE_MC5_STATUS 0x00000415\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MC5_ADDR (0x00000416)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);\r
+ AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
+**/\r
+#define MSR_CORE_MC5_ADDR 0x00000416\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE_MC5_MISC (0x00000417)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);\r
+ AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);\r
+ @endcode\r
+ @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
+**/\r
+#define MSR_CORE_MC5_MISC 0x00000417\r
+\r
+\r
+/**\r
+ Unique. See Table 2-2.\r
+\r
+ @param ECX MSR_CORE_IA32_EFER (0xC0000080)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE_IA32_EFER_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE_IA32_EFER_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE_IA32_EFER_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);\r
+ AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.\r
+**/\r
+#define MSR_CORE_IA32_EFER 0xC0000080\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE_IA32_EFER\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:11;\r
+ ///\r
+ /// [Bit 11] Execute Disable Bit Enable.\r
+ ///\r
+ UINT32 NXE:1;\r
+ UINT32 Reserved2:20;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE_IA32_EFER_REGISTER;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __GOLDMONT_MSR_H__\r
+#define __GOLDMONT_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel Atom processors based on the Goldmont microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x5C \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Core. Control Features in Intel 64Processor (R/W).\r
+\r
+ @param ECX MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Lock bit (R/WL)\r
+ ///\r
+ UINT32 Lock:1;\r
+ ///\r
+ /// [Bit 1] Enable VMX inside SMX operation (R/WL)\r
+ ///\r
+ UINT32 EnableVmxInsideSmx:1;\r
+ ///\r
+ /// [Bit 2] Enable VMX outside SMX operation (R/WL)\r
+ ///\r
+ UINT32 EnableVmxOutsideSmx:1;\r
+ UINT32 Reserved1:5;\r
+ ///\r
+ /// [Bits 14:8] SENTER local function enables (R/WL)\r
+ ///\r
+ UINT32 SenterLocalFunctionEnables:7;\r
+ ///\r
+ /// [Bit 15] SENTER global functions enable (R/WL)\r
+ ///\r
+ UINT32 SenterGlobalEnable:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 18] SGX global functions enable (R/WL)\r
+ ///\r
+ UINT32 SgxEnable:1;\r
+ UINT32 Reserved3:13;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. See http://biosbits.org.\r
+\r
+ @param ECX MSR_GOLDMONT_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
+ /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
+ /// MHz.\r
+ ///\r
+ UINT32 MaximumNonTurboRatio:8;\r
+ UINT32 Reserved2:12;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
+ /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
+ /// Turbo mode is disabled.\r
+ ///\r
+ UINT32 RatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
+ /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
+ /// programmable.\r
+ ///\r
+ UINT32 TDPLimit:1;\r
+ ///\r
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r
+ /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r
+ /// specify an temperature offset.\r
+ ///\r
+ UINT32 TJOFFSET:1;\r
+ UINT32 Reserved3:1;\r
+ UINT32 Reserved4:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
+ /// minimum ratio (maximum efficiency) that the processor can operates, in\r
+ /// units of 100MHz.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 Reserved5:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are\r
+ processor specific C-state code names, unrelated to MWAIT extension C-state\r
+ parameters or ACPI CStates. See http://biosbits.org.\r
+\r
+ @param ECX MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type\r
+ MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type\r
+ MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power). for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 0000b:\r
+ /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8\r
+ /// 0111b: C9 1000b: C10.\r
+ ///\r
+ UINT32 Limit:4;\r
+ UINT32 Reserved1:6;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
+ /// IO_read instructions sent to IO register specified by\r
+ /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
+ /// until next reset.\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:16;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.\r
+ Accessible only while in SMM.\r
+\r
+ @param ECX MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
+**/\r
+#define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and the\r
+ /// MSR_SMM_FEATURE_CONTROL is supported.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r
+ /// supported.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See\r
+ /// Table 2-2. Default value is 1.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved4:3;\r
+ ///\r
+ /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ UINT32 Reserved6:3;\r
+ ///\r
+ /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved7:8;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved9:3;\r
+ ///\r
+ /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
+ /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
+ /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
+ /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
+ /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
+ /// the power-on default value is used by BIOS to detect hardware support\r
+ /// of turbo mode. If power-on default value is 1, turbo mode is available\r
+ /// in the processor. If power-on default value is 0, turbo mode is not\r
+ /// available.\r
+ ///\r
+ UINT32 TurboModeDisable:1;\r
+ UINT32 Reserved10:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Miscellaneous Feature Control (R/W).\r
+\r
+ @param ECX MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L2 hardware prefetcher, which fetches additional lines of code or data\r
+ /// into the L2 cache.\r
+ ///\r
+ UINT32 L2HardwarePrefetcherDisable:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
+ /// the L1 data cache prefetcher, which fetches the next cache line into\r
+ /// L1 data cache.\r
+ ///\r
+ UINT32 DCUHardwarePrefetcherDisable:1;\r
+ UINT32 Reserved2:29;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. See http://biosbits.org.\r
+\r
+ @param ECX MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
+**/\r
+#define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables\r
+ /// hardware coordination of Enhanced Intel Speedstep Technology request\r
+ /// from processor cores; When 1, disables hardware coordination of\r
+ /// Enhanced Intel Speedstep Technology requests.\r
+ ///\r
+ UINT32 EISTHardwareCoordinationDisable:1;\r
+ UINT32 Reserved1:21;\r
+ ///\r
+ /// [Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then\r
+ /// thermal interrupt on one core is routed to all cores.\r
+ ///\r
+ UINT32 ThermalInterruptCoordinationEnable:1;\r
+ UINT32 Reserved2:9;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies\r
+ Maximum Ratio Limit for each Core Group. Max ratio for groups with more\r
+ cores must decrease monotonically. For groups with less than 4 cores, the\r
+ max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must\r
+ be 22 or less. For groups with more than 5 cores, the max ratio must be 16\r
+ or less..\r
+\r
+ @param ECX MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0\r
+ /// Maximum turbo ratio limit when number of active cores is less or equal\r
+ /// to Group 0 threshold.\r
+ ///\r
+ UINT32 MaxRatioLimitGroup0:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1\r
+ /// Maximum turbo ratio limit when number of active cores is less or equal\r
+ /// to Group 1 threshold and greater than Group 0 threshold.\r
+ ///\r
+ UINT32 MaxRatioLimitGroup1:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2\r
+ /// Maximum turbo ratio limit when number of active cores is less or equal\r
+ /// to Group 2 threshold and greater than Group 1 threshold.\r
+ ///\r
+ UINT32 MaxRatioLimitGroup2:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3\r
+ /// Maximum turbo ratio limit when number of active cores is less or equal\r
+ /// to Group 3 threshold and greater than Group 2 threshold.\r
+ ///\r
+ UINT32 MaxRatioLimitGroup3:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4\r
+ /// Maximum turbo ratio limit when number of active cores is less or equal\r
+ /// to Group 4 threshold and greater than Group 3 threshold.\r
+ ///\r
+ UINT32 MaxRatioLimitGroup4:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5\r
+ /// Maximum turbo ratio limit when number of active cores is less or equal\r
+ /// to Group 5 threshold and greater than Group 4 threshold.\r
+ ///\r
+ UINT32 MaxRatioLimitGroup5:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6\r
+ /// Maximum turbo ratio limit when number of active cores is less or equal\r
+ /// to Group 6 threshold and greater than Group 5 threshold.\r
+ ///\r
+ UINT32 MaxRatioLimitGroup6:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7\r
+ /// Maximum turbo ratio limit when number of active cores is less or equal\r
+ /// to Group 7 threshold and greater than Group 6 threshold.\r
+ ///\r
+ UINT32 MaxRatioLimitGroup7:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of\r
+ 0 threshold is ignored.\r
+\r
+ @param ECX MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.\r
+**/\r
+#define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of\r
+ /// active cores to operate under Group 0 Max Turbo Ratio limit.\r
+ ///\r
+ UINT32 CoreCountThresholdGroup0:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of\r
+ /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be\r
+ /// greater than Group 0 Core Count.\r
+ ///\r
+ UINT32 CoreCountThresholdGroup1:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of\r
+ /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be\r
+ /// greater than Group 1 Core Count.\r
+ ///\r
+ UINT32 CoreCountThresholdGroup2:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of\r
+ /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be\r
+ /// greater than Group 2 Core Count.\r
+ ///\r
+ UINT32 CoreCountThresholdGroup3:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of\r
+ /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be\r
+ /// greater than Group 3 Core Count.\r
+ ///\r
+ UINT32 CoreCountThresholdGroup4:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of\r
+ /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be\r
+ /// greater than Group 4 Core Count.\r
+ ///\r
+ UINT32 CoreCountThresholdGroup5:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of\r
+ /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be\r
+ /// greater than Group 5 Core Count.\r
+ ///\r
+ UINT32 CoreCountThresholdGroup6:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of\r
+ /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be\r
+ /// greater than Group 6 Core Count and not less than the total number of\r
+ /// processor cores in the package. E.g. specify 255.\r
+ ///\r
+ UINT32 CoreCountThresholdGroup7:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
+ "Filtering of Last Branch Records.".\r
+\r
+ @param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_LBR_SELECT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
+**/\r
+#define MSR_GOLDMONT_LBR_SELECT 0x000001C8\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] CPL_EQ_0.\r
+ ///\r
+ UINT32 CPL_EQ_0:1;\r
+ ///\r
+ /// [Bit 1] CPL_NEQ_0.\r
+ ///\r
+ UINT32 CPL_NEQ_0:1;\r
+ ///\r
+ /// [Bit 2] JCC.\r
+ ///\r
+ UINT32 JCC:1;\r
+ ///\r
+ /// [Bit 3] NEAR_REL_CALL.\r
+ ///\r
+ UINT32 NEAR_REL_CALL:1;\r
+ ///\r
+ /// [Bit 4] NEAR_IND_CALL.\r
+ ///\r
+ UINT32 NEAR_IND_CALL:1;\r
+ ///\r
+ /// [Bit 5] NEAR_RET.\r
+ ///\r
+ UINT32 NEAR_RET:1;\r
+ ///\r
+ /// [Bit 6] NEAR_IND_JMP.\r
+ ///\r
+ UINT32 NEAR_IND_JMP:1;\r
+ ///\r
+ /// [Bit 7] NEAR_REL_JMP.\r
+ ///\r
+ UINT32 NEAR_REL_JMP:1;\r
+ ///\r
+ /// [Bit 8] FAR_BRANCH.\r
+ ///\r
+ UINT32 FAR_BRANCH:1;\r
+ ///\r
+ /// [Bit 9] EN_CALL_STACK.\r
+ ///\r
+ UINT32 EN_CALL_STACK:1;\r
+ UINT32 Reserved1:22;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_LBR_SELECT_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that\r
+ points to the MSR containing the most recent branch record. See\r
+ MSR_LASTBRANCH_0_FROM_IP.\r
+\r
+ @param ECX MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Core. Power Control Register. See http://biosbits.org.\r
+\r
+ @param ECX MSR_GOLDMONT_POWER_CTL (0x000001FC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_POWER_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
+**/\r
+#define MSR_GOLDMONT_POWER_CTL 0x000001FC\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r
+ /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r
+ /// operating point when all execution cores enter MWAIT (C1).\r
+ ///\r
+ UINT32 C1EEnable:1;\r
+ UINT32 Reserved2:30;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_POWER_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
+ CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
+ the package. Lower 64 bits of an 128-bit external entropy value for key\r
+ derivation of an enclave.\r
+\r
+ @param ECX MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);\r
+ @endcode\r
+ @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.\r
+**/\r
+#define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300\r
+\r
+\r
+//\r
+// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.\r
+//\r
+#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0\r
+\r
+\r
+/**\r
+ Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of\r
+ an 128-bit external entropy value for key derivation of an enclave.\r
+\r
+ @param ECX MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);\r
+ @endcode\r
+ @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.\r
+**/\r
+#define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301\r
+\r
+\r
+//\r
+// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.\r
+//\r
+#define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1\r
+\r
+\r
+/**\r
+ Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r
+ Monitoring Version 4.".\r
+\r
+ @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
+**/\r
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Set 1 to clear Ovf_PMC0.\r
+ ///\r
+ UINT32 Ovf_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Set 1 to clear Ovf_PMC1.\r
+ ///\r
+ UINT32 Ovf_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Set 1 to clear Ovf_PMC2.\r
+ ///\r
+ UINT32 Ovf_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Set 1 to clear Ovf_PMC3.\r
+ ///\r
+ UINT32 Ovf_PMC3:1;\r
+ UINT32 Reserved1:28;\r
+ ///\r
+ /// [Bit 32] Set 1 to clear Ovf_FixedCtr0.\r
+ ///\r
+ UINT32 Ovf_FixedCtr0:1;\r
+ ///\r
+ /// [Bit 33] Set 1 to clear Ovf_FixedCtr1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr1:1;\r
+ ///\r
+ /// [Bit 34] Set 1 to clear Ovf_FixedCtr2.\r
+ ///\r
+ UINT32 Ovf_FixedCtr2:1;\r
+ UINT32 Reserved2:20;\r
+ ///\r
+ /// [Bit 55] Set 1 to clear Trace_ToPA_PMI.\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 58] Set 1 to clear LBR_Frz.\r
+ ///\r
+ UINT32 LBR_Frz:1;\r
+ ///\r
+ /// [Bit 59] Set 1 to clear CTR_Frz.\r
+ ///\r
+ UINT32 CTR_Frz:1;\r
+ ///\r
+ /// [Bit 60] Set 1 to clear ASCI.\r
+ ///\r
+ UINT32 ASCI:1;\r
+ ///\r
+ /// [Bit 61] Set 1 to clear Ovf_Uncore.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.\r
+ ///\r
+ UINT32 Ovf_BufDSSAVE:1;\r
+ ///\r
+ /// [Bit 63] Set 1 to clear CondChgd.\r
+ ///\r
+ UINT32 CondChgd:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
+\r
+\r
+/**\r
+ Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r
+ Monitoring Version 4.".\r
+\r
+ @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
+**/\r
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.\r
+ ///\r
+ UINT32 Ovf_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.\r
+ ///\r
+ UINT32 Ovf_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.\r
+ ///\r
+ UINT32 Ovf_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.\r
+ ///\r
+ UINT32 Ovf_PMC3:1;\r
+ UINT32 Reserved1:28;\r
+ ///\r
+ /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr0:1;\r
+ ///\r
+ /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr1:1;\r
+ ///\r
+ /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr2:1;\r
+ UINT32 Reserved2:20;\r
+ ///\r
+ /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 58] Set 1 to cause LBR_Frz = 1.\r
+ ///\r
+ UINT32 LBR_Frz:1;\r
+ ///\r
+ /// [Bit 59] Set 1 to cause CTR_Frz = 1.\r
+ ///\r
+ UINT32 CTR_Frz:1;\r
+ ///\r
+ /// [Bit 60] Set 1 to cause ASCI = 1.\r
+ ///\r
+ UINT32 ASCI:1;\r
+ ///\r
+ /// [Bit 61] Set 1 to cause Ovf_Uncore.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.\r
+ ///\r
+ UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Reserved4:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
+\r
+\r
+/**\r
+ Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
+ (PEBS).".\r
+\r
+ @param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS trigger and recording for the programmed event\r
+ /// (precise or otherwise) on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 Enable:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C3 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C6 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
+ Residency Counter. (R/O) Value since last reset that this core is in\r
+ processor-specific C3 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
+**/\r
+#define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC\r
+\r
+\r
+/**\r
+ Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r
+ /// further changes.\r
+ ///\r
+ UINT32 Lock:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r
+ /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r
+ /// logical processors are prevented from executing SMM code outside the\r
+ /// ranges defined by the SMRR. When set to '1' any logical processor in\r
+ /// the package that attempts to execute SMM code not within the ranges\r
+ /// defined by the SMRR will assert an unrecoverable MCE.\r
+ ///\r
+ UINT32 SMM_Code_Chk_En:1;\r
+ UINT32 Reserved2:29;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r
+ processors in the package. Available only while in SMM and\r
+ MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.\r
+\r
+ @param ECX MSR_GOLDMONT_SMM_DELAYED (0x000004E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_SMM_DELAYED_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r
+**/\r
+#define MSR_GOLDMONT_SMM_DELAYED 0x000004E2\r
+\r
+\r
+/**\r
+ Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r
+ processors in the package. Available only while in SMM.\r
+\r
+ @param ECX MSR_GOLDMONT_SMM_BLOCKED (0x000004E3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_SMM_BLOCKED_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r
+**/\r
+#define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3\r
+\r
+\r
+/**\r
+ Core. Trace Control Register (R/W).\r
+\r
+ @param ECX MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r
+**/\r
+#define MSR_IA32_RTIT_CTL 0x00000570\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] TraceEn.\r
+ ///\r
+ UINT32 TraceEn:1;\r
+ ///\r
+ /// [Bit 1] CYCEn.\r
+ ///\r
+ UINT32 CYCEn:1;\r
+ ///\r
+ /// [Bit 2] OS.\r
+ ///\r
+ UINT32 OS:1;\r
+ ///\r
+ /// [Bit 3] User.\r
+ ///\r
+ UINT32 User:1;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 7] CR3 filter.\r
+ ///\r
+ UINT32 CR3:1;\r
+ ///\r
+ /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.\r
+ ///\r
+ UINT32 ToPA:1;\r
+ ///\r
+ /// [Bit 9] MTCEn.\r
+ ///\r
+ UINT32 MTCEn:1;\r
+ ///\r
+ /// [Bit 10] TSCEn.\r
+ ///\r
+ UINT32 TSCEn:1;\r
+ ///\r
+ /// [Bit 11] DisRETC.\r
+ ///\r
+ UINT32 DisRETC:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 13] BranchEn.\r
+ ///\r
+ UINT32 BranchEn:1;\r
+ ///\r
+ /// [Bits 17:14] MTCFreq.\r
+ ///\r
+ UINT32 MTCFreq:4;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bits 22:19] CYCThresh.\r
+ ///\r
+ UINT32 CYCThresh:4;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bits 27:24] PSBFreq.\r
+ ///\r
+ UINT32 PSBFreq:4;\r
+ UINT32 Reserved5:4;\r
+ ///\r
+ /// [Bits 35:32] ADDR0_CFG.\r
+ ///\r
+ UINT32 ADDR0_CFG:4;\r
+ ///\r
+ /// [Bits 39:36] ADDR1_CFG.\r
+ ///\r
+ UINT32 ADDR1_CFG:4;\r
+ UINT32 Reserved6:24;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
+ "RAPL Interfaces.".\r
+\r
+ @param ECX MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT);\r
+ @endcode\r
+ @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
+**/\r
+#define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Power Units. Power related information (in Watts) is in\r
+ /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits\r
+ /// 3:0. Default value is 1000b, indicating power unit is in 3.9\r
+ /// milliWatts increment.\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Energy Status Units. Energy related information (in\r
+ /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned\r
+ /// integer represented by bits 12:8. Default value is 01110b, indicating\r
+ /// energy unit is in 61 microJoules.\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Time Unit. Time related information (in seconds) is in\r
+ /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits\r
+ /// 19:16. Default value is 1010b, indicating power unit is in 0.977\r
+ /// millisecond.\r
+ ///\r
+ UINT32 TimeUnit:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r
+ processor specific C-state code names, unrelated to MWAIT extension C-state\r
+ parameters or ACPI CStates.\r
+\r
+ @param ECX MSR_GOLDMONT_PKGC3_IRTL (0x0000060A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_PKGC3_IRTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
+ /// that should be used to decide if the package should be put into a\r
+ /// package C3 state.\r
+ ///\r
+ UINT32 InterruptResponseTimeLimit:10;\r
+ ///\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
+ /// of the interrupt response time limit. See Table 2-19 for supported\r
+ /// time unit encodings.\r
+ ///\r
+ UINT32 TimeUnit:3;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
+ /// valid and can be used by the processor for package C-sate management.\r
+ ///\r
+ UINT32 Valid:1;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_PKGC3_IRTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines\r
+ the interrupt response time limit used by the processor to manage transition\r
+ to package C6 or C7S state. Note: C-state values are processor specific\r
+ C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
+ CStates.\r
+\r
+ @param ECX MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_PKGC_IRTL1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
+ /// that should be used to decide if the package should be put into a\r
+ /// package C6 or C7S state.\r
+ ///\r
+ UINT32 InterruptResponseTimeLimit:10;\r
+ ///\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
+ /// of the interrupt response time limit. See Table 2-19 for supported\r
+ /// time unit encodings.\r
+ ///\r
+ UINT32 TimeUnit:3;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
+ /// valid and can be used by the processor for package C-sate management.\r
+ ///\r
+ UINT32 Valid:1;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_PKGC_IRTL1_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the\r
+ interrupt response time limit used by the processor to manage transition to\r
+ package C7 state. Note: C-state values are processor specific C-state code\r
+ names, unrelated to MWAIT extension C-state parameters or ACPI CStates.\r
+\r
+ @param ECX MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_PKGC_IRTL2_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
+ /// that should be used to decide if the package should be put into a\r
+ /// package C7 state.\r
+ ///\r
+ UINT32 InterruptResponseTimeLimit:10;\r
+ ///\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
+ /// of the interrupt response time limit. See Table 2-19 for supported\r
+ /// time unit encodings.\r
+ ///\r
+ UINT32 TimeUnit:3;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
+ /// valid and can be used by the processor for package C-sate management.\r
+ ///\r
+ UINT32 Valid:1;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_PKGC_IRTL2_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C2 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610\r
+\r
+\r
+/**\r
+ Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
+\r
+ @param ECX MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611\r
+\r
+\r
+/**\r
+ Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
+\r
+ @param ECX MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Parameters (R/W).\r
+\r
+ @param ECX MSR_GOLDMONT_PKG_POWER_INFO (0x00000614)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_PKG_POWER_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package\r
+ /// RAPL Domain.".\r
+ ///\r
+ UINT32 ThermalSpecPower:15;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL\r
+ /// Domain.".\r
+ ///\r
+ UINT32 MinimumPower:15;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL\r
+ /// Domain.".\r
+ ///\r
+ UINT32 MaximumPower:15;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 +\r
+ /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value\r
+ /// represented. by bits 52:48, "Z" is an unsigned integer represented by\r
+ /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of\r
+ /// MSR_RAPL_POWER_UNIT.\r
+ ///\r
+ UINT32 MaximumTimeWindow:7;\r
+ UINT32 Reserved4:9;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+ @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
+**/\r
+#define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,.\r
+ Package C10 Residency Counter. (R/O) Value since last reset that the entire\r
+ SOC is in an S0i3 state. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632\r
+\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Control (R/W).\r
+\r
+ @param ECX MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
+**/\r
+#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
+ /// field.\r
+ ///\r
+ UINT32 MAX_NON_TURBO_RATIO:8;\r
+ UINT32 Reserved1:23;\r
+ ///\r
+ /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
+ /// content of this register is locked until a reset.\r
+ ///\r
+ UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
+ refers to processor core frequency).\r
+\r
+ @param ECX MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
+**/\r
+#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
+ /// reduced below the operating system request due to assertion of\r
+ /// external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOTStatus:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to a thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ ///\r
+ /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to\r
+ /// package-level power limiting PL1.\r
+ ///\r
+ UINT32 PL1Status:1;\r
+ ///\r
+ /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to\r
+ /// package-level power limiting PL2.\r
+ ///\r
+ UINT32 PL2Status:1;\r
+ UINT32 Reserved1:5;\r
+ ///\r
+ /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to domain-level power limiting.\r
+ ///\r
+ UINT32 PowerLimitingStatus:1;\r
+ ///\r
+ /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to a thermal alert from the\r
+ /// Voltage Regulator.\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ ///\r
+ /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to multi-core turbo limits.\r
+ ///\r
+ UINT32 MaxTurboLimitStatus:1;\r
+ ///\r
+ /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to electrical design\r
+ /// point constraints (e.g. maximum electrical current consumption).\r
+ ///\r
+ UINT32 ElectricalDesignPointStatus:1;\r
+ ///\r
+ /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
+ /// is reduced below the operating system request due to Turbo transition\r
+ /// attenuation. This prevents performance degradation due to frequent\r
+ /// operating ratio changes.\r
+ ///\r
+ UINT32 TurboTransitionAttenuationStatus:1;\r
+ ///\r
+ /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency\r
+ /// is reduced below the maximum efficiency frequency.\r
+ ///\r
+ UINT32 MaximumEfficiencyFrequencyStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ ///\r
+ /// [Bit 18] Package-Level PL1 Power Limiting Log When set, indicates\r
+ /// that the Package Level PL1 Power Limiting Status bit has asserted\r
+ /// since the log bit was last cleared. This log bit will remain set until\r
+ /// cleared by software writing 0.\r
+ ///\r
+ UINT32 PL1Log:1;\r
+ ///\r
+ /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that\r
+ /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
+ /// log bit was last cleared. This log bit will remain set until cleared\r
+ /// by software writing 0.\r
+ ///\r
+ UINT32 PL2Log:1;\r
+ UINT32 Reserved3:5;\r
+ ///\r
+ /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
+ /// Power Limiting Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CorePowerLimitingLog:1;\r
+ ///\r
+ /// [Bit 26] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ ///\r
+ /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo\r
+ /// Limit Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 MaxTurboLimitLog:1;\r
+ ///\r
+ /// [Bit 28] Electrical Design Point Log When set, indicates that the EDP\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ElectricalDesignPointLog:1;\r
+ ///\r
+ /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
+ /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
+ /// was last cleared. This log bit will remain set until cleared by\r
+ /// software writing 0.\r
+ ///\r
+ UINT32 TurboTransitionAttenuationLog:1;\r
+ ///\r
+ /// [Bit 30] Maximum Efficiency Frequency Log When set, indicates that\r
+ /// the Maximum Efficiency Frequency Status bit has asserted since the log\r
+ /// bit was last cleared. This log bit will remain set until cleared by\r
+ /// software writing 0.\r
+ ///\r
+ UINT32 MaximumEfficiencyFrequencyLog:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch\r
+ record registers on the last branch record stack. The From_IP part of the\r
+ stack contains pointers to the source instruction . See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.6 and record format in Section\r
+ 17.4.8.1.\r
+\r
+ @param ECX MSR_GOLDMONT_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F\r
+#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690\r
+#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691\r
+#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692\r
+#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693\r
+#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694\r
+#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695\r
+#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696\r
+#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697\r
+#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698\r
+#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699\r
+#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A\r
+#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B\r
+#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C\r
+#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D\r
+#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E\r
+#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP\r
+ to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 31:0] From Linear Address (R/W).\r
+ ///\r
+ UINT32 FromLinearAddress:32;\r
+ ///\r
+ /// [Bit 47:32] From Linear Address (R/W).\r
+ ///\r
+ UINT32 FromLinearAddressHi:16;\r
+ ///\r
+ /// [Bits 62:48] Signed extension of bits 47:0.\r
+ ///\r
+ UINT32 SignedExtension:15;\r
+ ///\r
+ /// [Bit 63] Mispred.\r
+ ///\r
+ UINT32 Mispred:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record\r
+ registers on the last branch record stack. The To_IP part of the stack\r
+ contains pointers to the Destination instruction and elapsed cycles from\r
+ last LBR update. See also: - Section 17.6.\r
+\r
+ @param ECX MSR_GOLDMONT_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.\r
+ MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF\r
+#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0\r
+#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1\r
+#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2\r
+#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3\r
+#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4\r
+#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5\r
+#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6\r
+#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7\r
+#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8\r
+#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9\r
+#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA\r
+#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB\r
+#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC\r
+#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD\r
+#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE\r
+#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to\r
+ #MSR_GOLDMONT_LASTBRANCH_31_TO_IP.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 31:0] Target Linear Address (R/W).\r
+ ///\r
+ UINT32 TargetLinearAddress:32;\r
+ ///\r
+ /// [Bit 47:32] Target Linear Address (R/W).\r
+ ///\r
+ UINT32 TargetLinearAddressHi:16;\r
+ ///\r
+ /// [Bits 63:48] Elapsed cycles from last update to the LBR.\r
+ ///\r
+ UINT32 ElapsedCycles:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Resource Association Register (R/W).\r
+\r
+ @param ECX MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
+**/\r
+#define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ ///\r
+ /// [Bits 33:32] COS (R/W).\r
+ ///\r
+ UINT32 COS:2;\r
+ UINT32 Reserved2:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;\r
+\r
+\r
+/**\r
+ Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
+ ECX=1):EDX.COS_MAX[15:0] >=n.\r
+\r
+ @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_n\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM.\r
+ MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM.\r
+ MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.\r
+ @{\r
+**/\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to\r
+ #MSR_GOLDMONT_IA32_L2_QOS_MASK_2.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r
+ ///\r
+ UINT32 CBM:8;\r
+ UINT32 Reserved1:24;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;\r
+\r
+\r
+/**\r
+ Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,\r
+ ECX=1):EDX.COS_MAX[15:0] >=3.\r
+\r
+ @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_3\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.\r
+**/\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r
+ ///\r
+ UINT32 CBM:20;\r
+ UINT32 Reserved1:12;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;\r
+\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __GOLDMONT_PLUS_MSR_H__\r
+#define __GOLDMONT_PLUS_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel Atom processors based on the Goldmont plus microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x7A \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based\r
+ Sampling (PEBS).".\r
+\r
+ @param ECX MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_GOLDMONT_PLUS_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS trigger and recording for the programmed event\r
+ /// (precise or otherwise) on IA32_PMC0.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ ///\r
+ /// [Bit 1] Enable PEBS trigger and recording for the programmed event\r
+ /// (precise or otherwise) on IA32_PMC1.\r
+ ///\r
+ UINT32 Fix_Me_2:1;\r
+ ///\r
+ /// [Bit 2] Enable PEBS trigger and recording for the programmed event\r
+ /// (precise or otherwise) on IA32_PMC2.\r
+ ///\r
+ UINT32 Fix_Me_3:1;\r
+ ///\r
+ /// [Bit 3] Enable PEBS trigger and recording for the programmed event\r
+ /// (precise or otherwise) on IA32_PMC3.\r
+ ///\r
+ UINT32 Fix_Me_4:1;\r
+ UINT32 Reserved1:28;\r
+ ///\r
+ /// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.\r
+ ///\r
+ UINT32 Fix_Me_5:1;\r
+ ///\r
+ /// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.\r
+ ///\r
+ UINT32 Fix_Me_6:1;\r
+ ///\r
+ /// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.\r
+ ///\r
+ UINT32 Fix_Me_7:1;\r
+ UINT32 Reserved2:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up\r
+ the first entry of the 32-entry LBR stack. The From_IP part of the stack\r
+ contains pointers to the source instruction. See also: - Last Branch Record\r
+ Stack TOS at 1C9H. - Section 17.7, "Last Branch, Call Stack, Interrupt, and\r
+ .. Exception Recording for Processors based on Goldmont Plus\r
+ Microarchitecture.".\r
+\r
+ @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP 0x0000068F\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP 0x00000690\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP 0x00000691\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP 0x00000692\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP 0x00000693\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP 0x00000694\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP 0x00000695\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP 0x00000696\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP 0x00000697\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP 0x00000698\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP 0x00000699\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP 0x0000069A\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP 0x0000069B\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP 0x0000069C\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP 0x0000069D\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP 0x0000069E\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP 0x0000069F\r
+\r
+/**\r
+ Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up\r
+ the first entry of the 32-entry LBR stack. The To_IP part of the stack\r
+ contains pointers to the Destination instruction. See also: - Section 17.7,\r
+ "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors\r
+ based on Goldmont Plus Microarchitecture.".\r
+\r
+ @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP 0x000006CF\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP 0x000006D0\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP 0x000006D1\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP 0x000006D2\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP 0x000006D3\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP 0x000006D4\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP 0x000006D5\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP 0x000006D6\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP 0x000006D7\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP 0x000006D8\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP 0x000006D9\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP 0x000006DA\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP 0x000006DB\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP 0x000006DC\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP 0x000006DD\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP 0x000006DE\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP 0x000006DF\r
+\r
+\r
+/**\r
+ Core. Last Branch Record N Additional Information (R/W) One of the three\r
+ MSRs that make up the first entry of the 32-entry LBR stack. This part of\r
+ the stack contains flag and elapsed cycle information. See also: - Last\r
+ Branch Record Stack TOS at 1C9H. - Section 17.9.1, "LBR Stack.".\r
+\r
+ @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);\r
+ AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 0x00000DC0\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1 0x00000DC1\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2 0x00000DC2\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3 0x00000DC3\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4 0x00000DC4\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5 0x00000DC5\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6 0x00000DC6\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7 0x00000DC7\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8 0x00000DC8\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9 0x00000DC9\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10 0x00000DCA\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11 0x00000DCB\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12 0x00000DCC\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13 0x00000DCD\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14 0x00000DCE\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15 0x00000DCF\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16 0x00000DD0\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17 0x00000DD1\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18 0x00000DD2\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19 0x00000DD3\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20 0x00000DD4\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21 0x00000DD5\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22 0x00000DD6\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23 0x00000DD7\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24 0x00000DD8\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25 0x00000DD9\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26 0x00000DDA\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27 0x00000DDB\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28 0x00000DDC\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29 0x00000DDD\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30 0x00000DDE\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31 0x00000DDF\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel processors based on the Haswell-E microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __HASWELL_E_MSR_H__\r
+#define __HASWELL_E_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel processors based on the Haswell-E microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x3F \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Package. Configured State of Enabled Processor Core Count and Logical\r
+ Processor Count (RO) - After a Power-On RESET, enumerates factory\r
+ configuration of the number of processor cores and logical processors in the\r
+ physical package. - Following the sequence of (i) BIOS modified a\r
+ Configuration Mask which selects a subset of processor cores to be active\r
+ post RESET and (ii) a RESET event after the modification, enumerates the\r
+ current configuration of enabled processor core count and logical processor\r
+ count in the physical package.\r
+\r
+ @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);\r
+ @endcode\r
+ @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.\r
+**/\r
+#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are\r
+ /// currently enabled (by either factory configuration or BIOS\r
+ /// configuration) in the physical package.\r
+ ///\r
+ UINT32 Core_Count:16;\r
+ ///\r
+ /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that\r
+ /// are currently enabled (by either factory configuration or BIOS\r
+ /// configuration) in the physical package.\r
+ ///\r
+ UINT32 Thread_Count:16;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. A Hardware Assigned ID for the Logical Processor (RO).\r
+\r
+ @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);\r
+ @endcode\r
+ @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.\r
+**/\r
+#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific\r
+ /// numerical. value physically assigned to each logical processor. This\r
+ /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within\r
+ /// a physical package.\r
+ ///\r
+ UINT32 Logical_Processor_ID:8;\r
+ UINT32 Reserved1:24;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
+\r
+ @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power) for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
+ /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
+ /// supported by the processor are available.\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:9;\r
+ ///\r
+ /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C3AutoDemotion:1;\r
+ ///\r
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C1AutoDemotion:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Package C State Demotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateDemotion:1;\r
+ ///\r
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateUndemotion:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Global Machine Check Capability (R/O).\r
+\r
+ @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);\r
+ @endcode\r
+ @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
+**/\r
+#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Count.\r
+ ///\r
+ UINT32 Count:8;\r
+ ///\r
+ /// [Bit 8] MCG_CTL_P.\r
+ ///\r
+ UINT32 MCG_CTL_P:1;\r
+ ///\r
+ /// [Bit 9] MCG_EXT_P.\r
+ ///\r
+ UINT32 MCG_EXT_P:1;\r
+ ///\r
+ /// [Bit 10] MCP_CMCI_P.\r
+ ///\r
+ UINT32 MCP_CMCI_P:1;\r
+ ///\r
+ /// [Bit 11] MCG_TES_P.\r
+ ///\r
+ UINT32 MCG_TES_P:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 23:16] MCG_EXT_CNT.\r
+ ///\r
+ UINT32 MCG_EXT_CNT:8;\r
+ ///\r
+ /// [Bit 24] MCG_SER_P.\r
+ ///\r
+ UINT32 MCG_SER_P:1;\r
+ ///\r
+ /// [Bit 25] MCG_EM_P.\r
+ ///\r
+ UINT32 MCG_EM_P:1;\r
+ ///\r
+ /// [Bit 26] MCG_ELOG_P.\r
+ ///\r
+ UINT32 MCG_ELOG_P:1;\r
+ UINT32 Reserved2:5;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
+**/\r
+#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ Package. MC Bank Error Configuration (R/W).\r
+\r
+ @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
+ /// to log additional info in bits 36:32.\r
+ ///\r
+ UINT32 MemErrorLogEnable:1;\r
+ UINT32 Reserved2:30;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_ERROR_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+ @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
+ /// limit of 5 core active.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
+ /// limit of 6 core active.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
+ /// limit of 7 core active.\r
+ ///\r
+ UINT32 Maximum7C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
+ /// limit of 8 core active.\r
+ ///\r
+ UINT32 Maximum8C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);\r
+ @endcode\r
+ @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
+ /// limit of 9 core active.\r
+ ///\r
+ UINT32 Maximum9C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
+ /// limit of 10 core active.\r
+ ///\r
+ UINT32 Maximum10C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
+ /// limit of 11 core active.\r
+ ///\r
+ UINT32 Maximum11C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
+ /// limit of 12 core active.\r
+ ///\r
+ UINT32 Maximum12C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
+ /// limit of 13 core active.\r
+ ///\r
+ UINT32 Maximum13C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
+ /// limit of 14 core active.\r
+ ///\r
+ UINT32 Maximum14C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
+ /// limit of 15 core active.\r
+ ///\r
+ UINT32 Maximum15C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio\r
+ /// limit of 16 core active.\r
+ ///\r
+ UINT32 Maximum16C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);\r
+ @endcode\r
+ @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio\r
+ /// limit of 17 core active.\r
+ ///\r
+ UINT32 Maximum17C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio\r
+ /// limit of 18 core active.\r
+ ///\r
+ UINT32 Maximum18C:8;\r
+ UINT32 Reserved1:16;\r
+ UINT32 Reserved2:31;\r
+ ///\r
+ /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
+ /// the processor uses override configuration specified in\r
+ /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and\r
+ /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set\r
+ /// configuration (Default).\r
+ ///\r
+ UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
+\r
+ @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);\r
+ @endcode\r
+ @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
+**/\r
+#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Package. Energy Status Units Energy related information\r
+ /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
+ /// micro-joules).\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
+ /// Interfaces.".\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.\r
+\r
+ @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
+ /// to enable DRAM RAPL mode 0 (Direct VR).\r
+ ///\r
+ UINT32 Energy:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
+**/\r
+#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Package. Configuration of PCIE PLL Relative to BCLK(R/W).\r
+\r
+ @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz\r
+ /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use\r
+ /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz\r
+ /// operation.\r
+ ///\r
+ UINT32 PCIERatio:2;\r
+ ///\r
+ /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of\r
+ /// PCIE Ratio.\r
+ ///\r
+ UINT32 LPLLSelect:1;\r
+ ///\r
+ /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out\r
+ /// before re-locking Gen2/Gen3 PLLs.\r
+ ///\r
+ UINT32 LONGRESET:1;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
+ fields represent the widest possible range of uncore frequencies. Writing to\r
+ these fields allows software to control the minimum and the maximum\r
+ frequency that hardware will select.\r
+\r
+ @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 MAX_RATIO:7;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 MIN_RATIO:7;\r
+ UINT32 Reserved2:17;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
+\r
+/**\r
+ Package. Reserved (R/O) Reads return 0.\r
+\r
+ @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
+ refers to processor core frequency).\r
+\r
+ @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
+ /// reduced below the operating system request due to assertion of\r
+ /// external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to a thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ ///\r
+ /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to PBM limit.\r
+ ///\r
+ UINT32 PowerBudgetManagementStatus:1;\r
+ ///\r
+ /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to PCS\r
+ /// limit.\r
+ ///\r
+ UINT32 PlatformConfigurationServicesStatus:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
+ /// When set, frequency is reduced below the operating system request\r
+ /// because the processor has detected that utilization is low.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to a thermal alert from the\r
+ /// Voltage Regulator.\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to electrical design\r
+ /// point constraints (e.g. maximum electrical current consumption).\r
+ ///\r
+ UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to Multi-Core Turbo limits.\r
+ ///\r
+ UINT32 MultiCoreTurboStatus:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
+ /// below max non-turbo P1.\r
+ ///\r
+ UINT32 FrequencyP1Status:1;\r
+ ///\r
+ /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
+ /// set, frequency is reduced below max n-core turbo frequency.\r
+ ///\r
+ UINT32 TurboFrequencyLimitingStatus:1;\r
+ ///\r
+ /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
+ /// reduced below the operating system request.\r
+ ///\r
+ UINT32 FrequencyLimitingStatus:1;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ ///\r
+ /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PowerBudgetManagementLog:1;\r
+ ///\r
+ /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
+ /// the PCS Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PlatformConfigurationServicesLog:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
+ /// indicates that the AUBFC Status bit has asserted since the log bit was\r
+ /// last cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ ///\r
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 Reserved7:1;\r
+ ///\r
+ /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
+ /// Turbo Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 MultiCoreTurboLog:1;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
+ /// Frequency P1 Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CoreFrequencyP1Log:1;\r
+ ///\r
+ /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
+ /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 TurboFrequencyLimitingLog:1;\r
+ ///\r
+ /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
+ /// Frequency Limiting Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CoreFrequencyLimitingLog:1;\r
+ UINT32 Reserved9:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,\r
+ ECX=0):EBX.RDT-M[bit 12] = 1.\r
+\r
+ @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3\r
+ /// occupancy monitoring all other encoding reserved..\r
+ ///\r
+ UINT32 EventID:8;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bits 41:32] RMID (RW).\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved2:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Resource Association Register (R/W)..\r
+\r
+ @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
+**/\r
+#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] RMID.\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved1:22;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore perfmon per-socket global control.\r
+\r
+ @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700\r
+\r
+\r
+/**\r
+ Package. Uncore perfmon per-socket global status.\r
+\r
+ @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701\r
+\r
+\r
+/**\r
+ Package. Uncore perfmon per-socket global configuration.\r
+\r
+ @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702\r
+\r
+\r
+/**\r
+ Package. Uncore U-box UCLK fixed counter control.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703\r
+\r
+\r
+/**\r
+ Package. Uncore U-box UCLK fixed counter.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon event select for U-box counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon event select for U-box counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon U-box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon for PCU-box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon box-wide filter.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon box-wide filter.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon box-wide filter.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon box-wide filter.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon box-wide filter.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon box wide filter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon box wide filter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon counter n.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_CTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.\r
+ MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.\r
+ MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.\r
+ MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18\r
+#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19\r
+#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A\r
+#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B\r
+/// @}\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel processors based on the Haswell microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __HASWELL_MSR_H__\r
+#define __HASWELL_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel processors based on the Haswell microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x3C || \\r
+ DisplayModel == 0x45 || \\r
+ DisplayModel == 0x46 \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
+**/\r
+#define MSR_HASWELL_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
+ /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
+ /// MHz.\r
+ ///\r
+ UINT32 MaximumNonTurboRatio:8;\r
+ UINT32 Reserved2:12;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
+ /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
+ /// Turbo mode is disabled.\r
+ ///\r
+ UINT32 RatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
+ /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
+ /// programmable.\r
+ ///\r
+ UINT32 TDPLimit:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r
+ /// indicates that LPM is supported, and when set to 0, indicates LPM is\r
+ /// not supported.\r
+ ///\r
+ UINT32 LowPowerModeSupport:1;\r
+ ///\r
+ /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
+ /// TDP level available. 01: One additional TDP level available. 02: Two\r
+ /// additional TDP level available. 11: Reserved.\r
+ ///\r
+ UINT32 ConfigTDPLevels:2;\r
+ UINT32 Reserved4:5;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
+ /// minimum ratio (maximum efficiency) that the processor can operates, in\r
+ /// units of 100MHz.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
+ /// minimum supported operating ratio in units of 100 MHz.\r
+ ///\r
+ UINT32 MinimumOperatingRatio:8;\r
+ UINT32 Reserved5:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Performance Event Select for Counter n (R/W) Supports all fields\r
+ described inTable 2-2 and the fields below.\r
+\r
+ @param ECX MSR_HASWELL_IA32_PERFEVTSELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r
+ MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r
+ MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186\r
+#define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187\r
+#define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,\r
+ #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
+ ///\r
+ UINT32 EventSelect:8;\r
+ ///\r
+ /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
+ /// detect on the selected event logic.\r
+ ///\r
+ UINT32 UMASK:8;\r
+ ///\r
+ /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
+ ///\r
+ UINT32 USR:1;\r
+ ///\r
+ /// [Bit 17] OS: Counts while in privilege level is ring 0.\r
+ ///\r
+ UINT32 OS:1;\r
+ ///\r
+ /// [Bit 18] Edge: Enables edge detection if set.\r
+ ///\r
+ UINT32 E:1;\r
+ ///\r
+ /// [Bit 19] PC: enables pin control.\r
+ ///\r
+ UINT32 PC:1;\r
+ ///\r
+ /// [Bit 20] INT: enables interrupt on counter overflow.\r
+ ///\r
+ UINT32 INT:1;\r
+ ///\r
+ /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
+ /// event conditions occurring across all logical processors sharing a\r
+ /// processor core. When set to 0, the counter only increments the\r
+ /// associated event conditions occurring in the logical processor which\r
+ /// programmed the MSR.\r
+ ///\r
+ UINT32 ANY:1;\r
+ ///\r
+ /// [Bit 22] EN: enables the corresponding performance counter to commence\r
+ /// counting when this bit is set.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bit 23] INV: invert the CMASK.\r
+ ///\r
+ UINT32 INV:1;\r
+ ///\r
+ /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
+ /// performance counter increments each cycle if the event count is\r
+ /// greater than or equal to the CMASK.\r
+ ///\r
+ UINT32 CMASK:8;\r
+ UINT32 Reserved:32;\r
+ ///\r
+ /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r
+ /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
+ ///\r
+ UINT32 IN_TX:1;\r
+ UINT32 Reserved2:31;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Performance Event Select for Counter 2 (R/W) Supports all fields\r
+ described inTable 2-2 and the fields below.\r
+\r
+ @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
+ ///\r
+ UINT32 EventSelect:8;\r
+ ///\r
+ /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
+ /// detect on the selected event logic.\r
+ ///\r
+ UINT32 UMASK:8;\r
+ ///\r
+ /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
+ ///\r
+ UINT32 USR:1;\r
+ ///\r
+ /// [Bit 17] OS: Counts while in privilege level is ring 0.\r
+ ///\r
+ UINT32 OS:1;\r
+ ///\r
+ /// [Bit 18] Edge: Enables edge detection if set.\r
+ ///\r
+ UINT32 E:1;\r
+ ///\r
+ /// [Bit 19] PC: enables pin control.\r
+ ///\r
+ UINT32 PC:1;\r
+ ///\r
+ /// [Bit 20] INT: enables interrupt on counter overflow.\r
+ ///\r
+ UINT32 INT:1;\r
+ ///\r
+ /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
+ /// event conditions occurring across all logical processors sharing a\r
+ /// processor core. When set to 0, the counter only increments the\r
+ /// associated event conditions occurring in the logical processor which\r
+ /// programmed the MSR.\r
+ ///\r
+ UINT32 ANY:1;\r
+ ///\r
+ /// [Bit 22] EN: enables the corresponding performance counter to commence\r
+ /// counting when this bit is set.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bit 23] INV: invert the CMASK.\r
+ ///\r
+ UINT32 INV:1;\r
+ ///\r
+ /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
+ /// performance counter increments each cycle if the event count is\r
+ /// greater than or equal to the CMASK.\r
+ ///\r
+ UINT32 CMASK:8;\r
+ UINT32 Reserved:32;\r
+ ///\r
+ /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r
+ /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
+ ///\r
+ UINT32 IN_TX:1;\r
+ ///\r
+ /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and\r
+ /// in sampling, spurious PMI may occur and transactions may continuously\r
+ /// abort near overflow conditions. Software should favor using IN_TXCP\r
+ /// for counting over sampling. If sampling, software should use large\r
+ /// "sample-after" value after clearing the counter configured to use\r
+ /// IN_TXCP and also always reset the counter even when no overflow\r
+ /// condition was reported.\r
+ ///\r
+ UINT32 IN_TXCP:1;\r
+ UINT32 Reserved2:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record Filtering Select Register (R/W).\r
+\r
+ @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_LBR_SELECT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);\r
+ AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
+**/\r
+#define MSR_HASWELL_LBR_SELECT 0x000001C8\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] CPL_EQ_0.\r
+ ///\r
+ UINT32 CPL_EQ_0:1;\r
+ ///\r
+ /// [Bit 1] CPL_NEQ_0.\r
+ ///\r
+ UINT32 CPL_NEQ_0:1;\r
+ ///\r
+ /// [Bit 2] JCC.\r
+ ///\r
+ UINT32 JCC:1;\r
+ ///\r
+ /// [Bit 3] NEAR_REL_CALL.\r
+ ///\r
+ UINT32 NEAR_REL_CALL:1;\r
+ ///\r
+ /// [Bit 4] NEAR_IND_CALL.\r
+ ///\r
+ UINT32 NEAR_IND_CALL:1;\r
+ ///\r
+ /// [Bit 5] NEAR_RET.\r
+ ///\r
+ UINT32 NEAR_RET:1;\r
+ ///\r
+ /// [Bit 6] NEAR_IND_JMP.\r
+ ///\r
+ UINT32 NEAR_IND_JMP:1;\r
+ ///\r
+ /// [Bit 7] NEAR_REL_JMP.\r
+ ///\r
+ UINT32 NEAR_REL_JMP:1;\r
+ ///\r
+ /// [Bit 8] FAR_BRANCH.\r
+ ///\r
+ UINT32 FAR_BRANCH:1;\r
+ ///\r
+ /// [Bit 9] EN_CALL_STACK.\r
+ ///\r
+ UINT32 EN_CALL_STACK:1;\r
+ UINT32 Reserved1:22;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_LBR_SELECT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines\r
+ the interrupt response time limit used by the processor to manage transition\r
+ to package C6 or C7 state. The latency programmed in this register is for\r
+ the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.\r
+ Note: C-state values are processor specific C-state code names, unrelated to\r
+ MWAIT extension C-state parameters or ACPI C-States.\r
+\r
+ @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_PKGC_IRTL1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_PKGC_IRTL1 0x0000060B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
+ /// that should be used to decide if the package should be put into a\r
+ /// package C6 or C7 state.\r
+ ///\r
+ UINT32 InterruptResponseTimeLimit:10;\r
+ ///\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
+ /// of the interrupt response time limit. See Table 2-19 for supported\r
+ /// time unit encodings.\r
+ ///\r
+ UINT32 TimeUnit:3;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
+ /// valid and can be used by the processor for package C-sate management.\r
+ ///\r
+ UINT32 Valid:1;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_PKGC_IRTL1_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines\r
+ the interrupt response time limit used by the processor to manage transition\r
+ to package C6 or C7 state. The latency programmed in this register is for\r
+ the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.\r
+ Note: C-state values are processor specific C-state code names, unrelated to\r
+ MWAIT extension C-state parameters or ACPI C-States.\r
+\r
+ @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_PKGC_IRTL2_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_PKGC_IRTL2 0x0000060C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
+ /// that should be used to decide if the package should be put into a\r
+ /// package C6 or C7 state.\r
+ ///\r
+ UINT32 InterruptResponseTimeLimit:10;\r
+ ///\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
+ /// of the interrupt response time limit. See Table 2-19 for supported\r
+ /// time unit encodings.\r
+ ///\r
+ UINT32 TimeUnit:3;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
+ /// valid and can be used by the processor for package C-sate management.\r
+ ///\r
+ UINT32 Valid:1;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_PKGC_IRTL2_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
+\r
+ @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. Base TDP Ratio (R/O).\r
+\r
+ @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);\r
+ @endcode\r
+ @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
+**/\r
+#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
+ /// specific processor (in units of 100 MHz).\r
+ ///\r
+ UINT32 Config_TDP_Base:8;\r
+ UINT32 Reserved1:24;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Level 1 ratio and power level (R/O).\r
+\r
+ @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);\r
+ @endcode\r
+ @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
+ ///\r
+ UINT32 PKG_TDP_LVL1:15;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
+ /// for this specific processor.\r
+ ///\r
+ UINT32 Config_TDP_LVL1_Ratio:8;\r
+ UINT32 Reserved2:8;\r
+ ///\r
+ /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
+ /// Level 1.\r
+ ///\r
+ UINT32 PKG_MAX_PWR_LVL1:15;\r
+ ///\r
+ /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
+ /// Level 1.\r
+ ///\r
+ UINT32 PKG_MIN_PWR_LVL1:16;\r
+ UINT32 Reserved3:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Level 2 ratio and power level (R/O).\r
+\r
+ @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);\r
+ @endcode\r
+ @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
+**/\r
+#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
+ ///\r
+ UINT32 PKG_TDP_LVL2:15;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
+ /// for this specific processor.\r
+ ///\r
+ UINT32 Config_TDP_LVL2_Ratio:8;\r
+ UINT32 Reserved2:8;\r
+ ///\r
+ /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
+ /// Level 2.\r
+ ///\r
+ UINT32 PKG_MAX_PWR_LVL2:15;\r
+ ///\r
+ /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
+ /// Level 2.\r
+ ///\r
+ UINT32 PKG_MIN_PWR_LVL2:16;\r
+ UINT32 Reserved3:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Control (R/W).\r
+\r
+ @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);\r
+ AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
+**/\r
+#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
+ ///\r
+ UINT32 TDP_LEVEL:2;\r
+ UINT32 Reserved1:29;\r
+ ///\r
+ /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
+ /// this register is locked until a reset.\r
+ ///\r
+ UINT32 Config_TDP_Lock:1;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Control (R/W).\r
+\r
+ @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);\r
+ AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
+**/\r
+#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
+ /// field.\r
+ ///\r
+ UINT32 MAX_NON_TURBO_RATIO:8;\r
+ UINT32 Reserved1:23;\r
+ ///\r
+ /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
+ /// content of this register is locked until a reset.\r
+ ///\r
+ UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.\r
+\r
+ @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
+**/\r
+#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power) for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 0000b:\r
+ /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
+ /// 0100b: C7 0101b: C7s Package C states C7 are not available to\r
+ /// processor with signature 06_3CH.\r
+ ///\r
+ UINT32 Limit:4;\r
+ UINT32 Reserved1:6;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:9;\r
+ ///\r
+ /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C3AutoDemotion:1;\r
+ ///\r
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C1AutoDemotion:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ UINT32 Reserved4:3;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
+**/\r
+#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and the\r
+ /// MSR_SMM_FEATURE_CONTROL is supported.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r
+ /// supported.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+ @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore PMU global control.\r
+\r
+ @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core 0 select.\r
+ ///\r
+ UINT32 PMI_Sel_Core0:1;\r
+ ///\r
+ /// [Bit 1] Core 1 select.\r
+ ///\r
+ UINT32 PMI_Sel_Core1:1;\r
+ ///\r
+ /// [Bit 2] Core 2 select.\r
+ ///\r
+ UINT32 PMI_Sel_Core2:1;\r
+ ///\r
+ /// [Bit 3] Core 3 select.\r
+ ///\r
+ UINT32 PMI_Sel_Core3:1;\r
+ UINT32 Reserved1:15;\r
+ UINT32 Reserved2:10;\r
+ ///\r
+ /// [Bit 29] Enable all uncore counters.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bit 30] Enable wake on PMI.\r
+ ///\r
+ UINT32 WakePMI:1;\r
+ ///\r
+ /// [Bit 31] Enable Freezing counter when overflow.\r
+ ///\r
+ UINT32 FREEZE:1;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore PMU main status.\r
+\r
+ @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fixed counter overflowed.\r
+ ///\r
+ UINT32 Fixed:1;\r
+ ///\r
+ /// [Bit 1] An ARB counter overflowed.\r
+ ///\r
+ UINT32 ARB:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 3] A CBox counter overflowed (on any slice).\r
+ ///\r
+ UINT32 CBox:1;\r
+ UINT32 Reserved2:28;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore fixed counter control (R/W).\r
+\r
+ @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:20;\r
+ ///\r
+ /// [Bit 20] Enable overflow propagation.\r
+ ///\r
+ UINT32 EnableOverflow:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 22] Enable counting.\r
+ ///\r
+ UINT32 EnableCounting:1;\r
+ UINT32 Reserved3:9;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore fixed counter.\r
+\r
+ @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Current count.\r
+ ///\r
+ UINT32 CurrentCount:32;\r
+ ///\r
+ /// [Bits 47:32] Current count.\r
+ ///\r
+ UINT32 CurrentCountHi:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box configuration information (R/O).\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".\r
+ ///\r
+ UINT32 CBox:4;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, performance counter 0.\r
+\r
+ @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, performance counter 1.\r
+\r
+ @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3\r
+\r
+\r
+/**\r
+ Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r
+ /// further changes.\r
+ ///\r
+ UINT32 Lock:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r
+ /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r
+ /// logical processors are prevented from executing SMM code outside the\r
+ /// ranges defined by the SMRR. When set to '1' any logical processor in\r
+ /// the package that attempts to execute SMM code not within the ranges\r
+ /// defined by the SMRR will assert an unrecoverable MCE.\r
+ ///\r
+ UINT32 SMM_Code_Chk_En:1;\r
+ UINT32 Reserved2:29;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r
+ processors in the package. Available only while in SMM and\r
+ MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.\r
+\r
+ [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
+ processor of its state in a long flow of internal operation which\r
+ delays servicing an interrupt. The corresponding bit will be set at\r
+ the start of long events such as: Microcode Update Load, C6, WBINVD,\r
+ Ratio Change, Throttle. The bit is automatically cleared at the end of\r
+ each long event. The reset value of this field is 0. Only bit\r
+ positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be\r
+ updated.\r
+\r
+ [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
+ processor of its state in a long flow of internal operation which\r
+ delays servicing an interrupt. The corresponding bit will be set at\r
+ the start of long events such as: Microcode Update Load, C6, WBINVD,\r
+ Ratio Change, Throttle. The bit is automatically cleared at the end of\r
+ each long event. The reset value of this field is 0. Only bit\r
+ positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be\r
+ updated.\r
+\r
+ @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);\r
+ @endcode\r
+ @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r
+**/\r
+#define MSR_HASWELL_SMM_DELAYED 0x000004E2\r
+\r
+\r
+/**\r
+ Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r
+ processors in the package. Available only while in SMM.\r
+\r
+ [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
+ processor of its blocked state to service an SMI. The corresponding\r
+ bit will be set if the logical processor is in one of the following\r
+ states: Wait For SIPI or SENTER Sleep. The reset value of this field\r
+ is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,\r
+ ECX=PKG_LVL):EBX[15:0] can be updated.\r
+\r
+\r
+ [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
+ processor of its blocked state to service an SMI. The corresponding\r
+ bit will be set if the logical processor is in one of the following\r
+ states: Wait For SIPI or SENTER Sleep. The reset value of this field\r
+ is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,\r
+ ECX=PKG_LVL):EBX[15:0] can be updated.\r
+\r
+ @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);\r
+ @endcode\r
+ @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r
+**/\r
+#define MSR_HASWELL_SMM_BLOCKED 0x000004E3\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
+\r
+ @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);\r
+ @endcode\r
+ @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
+**/\r
+#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Package. Energy Status Units Energy related information\r
+ /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
+ /// micro-joules).\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
+ /// Interfaces.".\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
+ RAPL Domains.".\r
+\r
+ @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640\r
+\r
+\r
+/**\r
+ Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641\r
+\r
+\r
+/**\r
+ Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_HASWELL_PP1_POLICY (0x00000642)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);\r
+ AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r
+**/\r
+#define MSR_HASWELL_PP1_POLICY 0x00000642\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
+ refers to processor core frequency).\r
+\r
+ @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
+**/\r
+#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
+ /// reduced below the operating system request due to assertion of\r
+ /// external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to a thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to Processor Graphics driver\r
+ /// override.\r
+ ///\r
+ UINT32 GraphicsDriverStatus:1;\r
+ ///\r
+ /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
+ /// When set, frequency is reduced below the operating system request\r
+ /// because the processor has detected that utilization is low.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to a thermal alert from the\r
+ /// Voltage Regulator.\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to electrical design\r
+ /// point constraints (e.g. maximum electrical current consumption).\r
+ ///\r
+ UINT32 ElectricalDesignPointStatus:1;\r
+ ///\r
+ /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to domain-level power limiting.\r
+ ///\r
+ UINT32 PLStatus:1;\r
+ ///\r
+ /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to\r
+ /// package-level power limiting PL1.\r
+ ///\r
+ UINT32 PL1Status:1;\r
+ ///\r
+ /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to\r
+ /// package-level power limiting PL2.\r
+ ///\r
+ UINT32 PL2Status:1;\r
+ ///\r
+ /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to multi-core turbo limits.\r
+ ///\r
+ UINT32 MaxTurboLimitStatus:1;\r
+ ///\r
+ /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
+ /// is reduced below the operating system request due to Turbo transition\r
+ /// attenuation. This prevents performance degradation due to frequent\r
+ /// operating ratio changes.\r
+ ///\r
+ UINT32 TurboTransitionAttenuationStatus:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
+ /// Driver Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 GraphicsDriverLog:1;\r
+ ///\r
+ /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
+ /// indicates that the Autonomous Utilization-Based Frequency Control\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ ///\r
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ElectricalDesignPointLog:1;\r
+ ///\r
+ /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
+ /// Power Limiting Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 PLLog:1;\r
+ ///\r
+ /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
+ /// that the Package Level PL1 Power Limiting Status bit has asserted\r
+ /// since the log bit was last cleared. This log bit will remain set until\r
+ /// cleared by software writing 0.\r
+ ///\r
+ UINT32 PL1Log:1;\r
+ ///\r
+ /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
+ /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
+ /// log bit was last cleared. This log bit will remain set until cleared\r
+ /// by software writing 0.\r
+ ///\r
+ UINT32 PL2Log:1;\r
+ ///\r
+ /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
+ /// Limit Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 MaxTurboLimitLog:1;\r
+ ///\r
+ /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
+ /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
+ /// was last cleared. This log bit will remain set until cleared by\r
+ /// software writing 0.\r
+ ///\r
+ UINT32 TurboTransitionAttenuationLog:1;\r
+ UINT32 Reserved6:2;\r
+ UINT32 Reserved7:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
+ (frequency refers to processor graphics frequency).\r
+\r
+ @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r
+**/\r
+#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to assertion of external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to a thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to Processor Graphics driver\r
+ /// override.\r
+ ///\r
+ UINT32 GraphicsDriverStatus:1;\r
+ ///\r
+ /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
+ /// When set, frequency is reduced below the operating system request\r
+ /// because the processor has detected that utilization is low.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to a thermal alert from the\r
+ /// Voltage Regulator.\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to electrical design\r
+ /// point constraints (e.g. maximum electrical current consumption).\r
+ ///\r
+ UINT32 ElectricalDesignPointStatus:1;\r
+ ///\r
+ /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to domain-level power\r
+ /// limiting.\r
+ ///\r
+ UINT32 GraphicsPowerLimitingStatus:1;\r
+ ///\r
+ /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to\r
+ /// package-level power limiting PL1.\r
+ ///\r
+ UINT32 PL1STatus:1;\r
+ ///\r
+ /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to\r
+ /// package-level power limiting PL2.\r
+ ///\r
+ UINT32 PL2Status:1;\r
+ UINT32 Reserved3:4;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
+ /// Driver Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 GraphicsDriverLog:1;\r
+ ///\r
+ /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
+ /// indicates that the Autonomous Utilization-Based Frequency Control\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ ///\r
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ElectricalDesignPointLog:1;\r
+ ///\r
+ /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
+ /// Power Limiting Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CorePowerLimitingLog:1;\r
+ ///\r
+ /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
+ /// that the Package Level PL1 Power Limiting Status bit has asserted\r
+ /// since the log bit was last cleared. This log bit will remain set until\r
+ /// cleared by software writing 0.\r
+ ///\r
+ UINT32 PL1Log:1;\r
+ ///\r
+ /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
+ /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
+ /// log bit was last cleared. This log bit will remain set until cleared\r
+ /// by software writing 0.\r
+ ///\r
+ UINT32 PL2Log:1;\r
+ ///\r
+ /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
+ /// Limit Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 MaxTurboLimitLog:1;\r
+ ///\r
+ /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
+ /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
+ /// was last cleared. This log bit will remain set until cleared by\r
+ /// software writing 0.\r
+ ///\r
+ UINT32 TurboTransitionAttenuationLog:1;\r
+ UINT32 Reserved6:2;\r
+ UINT32 Reserved7:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
+ (frequency refers to ring interconnect in the uncore).\r
+\r
+ @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
+**/\r
+#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to assertion of external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to a thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to a thermal alert from the\r
+ /// Voltage Regulator.\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to electrical design\r
+ /// point constraints (e.g. maximum electrical current consumption).\r
+ ///\r
+ UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to\r
+ /// package-level power limiting PL1.\r
+ ///\r
+ UINT32 PL1STatus:1;\r
+ ///\r
+ /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to\r
+ /// package-level power limiting PL2.\r
+ ///\r
+ UINT32 PL2Status:1;\r
+ UINT32 Reserved4:4;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ UINT32 Reserved5:2;\r
+ ///\r
+ /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
+ /// Driver Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 GraphicsDriverLog:1;\r
+ ///\r
+ /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
+ /// indicates that the Autonomous Utilization-Based Frequency Control\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ ///\r
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ElectricalDesignPointLog:1;\r
+ ///\r
+ /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
+ /// Power Limiting Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CorePowerLimitingLog:1;\r
+ ///\r
+ /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
+ /// that the Package Level PL1 Power Limiting Status bit has asserted\r
+ /// since the log bit was last cleared. This log bit will remain set until\r
+ /// cleared by software writing 0.\r
+ ///\r
+ UINT32 PL1Log:1;\r
+ ///\r
+ /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
+ /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
+ /// log bit was last cleared. This log bit will remain set until cleared\r
+ /// by software writing 0.\r
+ ///\r
+ UINT32 PL2Log:1;\r
+ ///\r
+ /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
+ /// Limit Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 MaxTurboLimitLog:1;\r
+ ///\r
+ /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
+ /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
+ /// was last cleared. This log bit will remain set until cleared by\r
+ /// software writing 0.\r
+ ///\r
+ UINT32 TurboTransitionAttenuationLog:1;\r
+ UINT32 Reserved7:2;\r
+ UINT32 Reserved8:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 0, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 0, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 0, performance counter 0.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 0, performance counter 1.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 1, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 1, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 1, performance counter 0.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 1, performance counter 1.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 2, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 2, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 2, performance counter 0.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 2, performance counter 1.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 3, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 3, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 3, performance counter 0.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 3, performance counter 1.\r
+\r
+ @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
+\r
+ @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.\r
+**/\r
+#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset\r
+ /// that this package is in processor-specific C8 states. Count at the\r
+ /// same frequency as the TSC.\r
+ ///\r
+ UINT32 C8ResidencyCounter:32;\r
+ ///\r
+ /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r
+ /// reset that this package is in processor-specific C8 states. Count at\r
+ /// the same frequency as the TSC.\r
+ ///\r
+ UINT32 C8ResidencyCounterHi:28;\r
+ UINT32 Reserved:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
+\r
+ @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.\r
+**/\r
+#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset\r
+ /// that this package is in processor-specific C9 states. Count at the\r
+ /// same frequency as the TSC.\r
+ ///\r
+ UINT32 C9ResidencyCounter:32;\r
+ ///\r
+ /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r
+ /// reset that this package is in processor-specific C9 states. Count at\r
+ /// the same frequency as the TSC.\r
+ ///\r
+ UINT32 C9ResidencyCounterHi:28;\r
+ UINT32 Reserved:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
+\r
+ @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
+**/\r
+#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last\r
+ /// reset that this package is in processor-specific C10 states. Count at\r
+ /// the same frequency as the TSC.\r
+ ///\r
+ UINT32 C10ResidencyCounter:32;\r
+ ///\r
+ /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r
+ /// reset that this package is in processor-specific C10 states. Count at\r
+ /// the same frequency as the TSC.\r
+ ///\r
+ UINT32 C10ResidencyCounterHi:28;\r
+ UINT32 Reserved:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __IVY_BRIDGE_MSR_H__\r
+#define __IVY_BRIDGE_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel processors based on the Ivy Bridge microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x3A || \\r
+ DisplayModel == 0x3E \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Package. See http://biosbits.org.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
+ /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
+ /// MHz.\r
+ ///\r
+ UINT32 MaximumNonTurboRatio:8;\r
+ UINT32 Reserved2:12;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
+ /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
+ /// Turbo mode is disabled.\r
+ ///\r
+ UINT32 RatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
+ /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
+ /// programmable.\r
+ ///\r
+ UINT32 TDPLimit:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r
+ /// indicates that LPM is supported, and when set to 0, indicates LPM is\r
+ /// not supported.\r
+ ///\r
+ UINT32 LowPowerModeSupport:1;\r
+ ///\r
+ /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
+ /// TDP level available. 01: One additional TDP level available. 02: Two\r
+ /// additional TDP level available. 11: Reserved.\r
+ ///\r
+ UINT32 ConfigTDPLevels:2;\r
+ UINT32 Reserved4:5;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
+ /// minimum ratio (maximum efficiency) that the processor can operates, in\r
+ /// units of 100MHz.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
+ /// minimum supported operating ratio in units of 100 MHz.\r
+ ///\r
+ UINT32 MinimumOperatingRatio:8;\r
+ UINT32 Reserved5:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are\r
+ processor specific C-state code names, unrelated to MWAIT extension C-state\r
+ parameters or ACPI C-States. See http://biosbits.org.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power). for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r
+ /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
+ /// This field cannot be used to limit package C-state to C3.\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
+ /// IO_read instructions sent to IO register specified by\r
+ /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
+ /// until next reset.\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:9;\r
+ ///\r
+ /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
+ /// will conditionally demote C6/C7 requests to C3 based on uncore\r
+ /// auto-demote information.\r
+ ///\r
+ UINT32 C3AutoDemotion:1;\r
+ ///\r
+ /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
+ /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
+ /// auto-demote information.\r
+ ///\r
+ UINT32 C1AutoDemotion:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
+ /// demoted C3.\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
+ /// demoted C1.\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ UINT32 Reserved4:3;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Package. Base TDP Ratio (R/O).\r
+\r
+ @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
+ /// specific processor (in units of 100 MHz).\r
+ ///\r
+ UINT32 Config_TDP_Base:8;\r
+ UINT32 Reserved1:24;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Level 1 ratio and power level (R/O).\r
+\r
+ @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
+ ///\r
+ UINT32 PKG_TDP_LVL1:15;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
+ /// for this specific processor.\r
+ ///\r
+ UINT32 Config_TDP_LVL1_Ratio:8;\r
+ UINT32 Reserved2:8;\r
+ ///\r
+ /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
+ /// Level 1.\r
+ ///\r
+ UINT32 PKG_MAX_PWR_LVL1:15;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
+ /// Level 1.\r
+ ///\r
+ UINT32 PKG_MIN_PWR_LVL1:15;\r
+ UINT32 Reserved4:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Level 2 ratio and power level (R/O).\r
+\r
+ @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
+ ///\r
+ UINT32 PKG_TDP_LVL2:15;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
+ /// for this specific processor.\r
+ ///\r
+ UINT32 Config_TDP_LVL2_Ratio:8;\r
+ UINT32 Reserved2:8;\r
+ ///\r
+ /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
+ /// Level 2.\r
+ ///\r
+ UINT32 PKG_MAX_PWR_LVL2:15;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
+ /// Level 2.\r
+ ///\r
+ UINT32 PKG_MIN_PWR_LVL2:15;\r
+ UINT32 Reserved4:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Control (R/W).\r
+\r
+ @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
+ ///\r
+ UINT32 TDP_LEVEL:2;\r
+ UINT32 Reserved1:29;\r
+ ///\r
+ /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
+ /// this register is locked until a reset.\r
+ ///\r
+ UINT32 Config_TDP_Lock:1;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Control (R/W).\r
+\r
+ @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
+ /// field.\r
+ ///\r
+ UINT32 MAX_NON_TURBO_RATIO:8;\r
+ UINT32 Reserved1:23;\r
+ ///\r
+ /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
+ /// content of this register is locked until a reset.\r
+ ///\r
+ UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number Enable Control (R/W).\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.\r
+ /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit\r
+ /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to\r
+ /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged\r
+ /// inventory initialization agent to access MSR_PPIN. After reading\r
+ /// MSR_PPIN, the privileged inventory initialization agent should write\r
+ /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
+ /// prevent unauthorized modification to MSR_PPIN_CTL.\r
+ ///\r
+ UINT32 LockOut:1;\r
+ ///\r
+ /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
+ /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will\r
+ /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default\r
+ /// is 0.\r
+ ///\r
+ UINT32 Enable_PPIN:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number (R/O). Protected Processor\r
+ Inventory Number (R/O) A unique value within a given CPUID\r
+ family/model/stepping signature that a privileged inventory initialization\r
+ agent can access to identify each physical processor, when access to\r
+ MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r
+ MSR_PPIN_CTL[bits 1:0] = '10b'.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PPIN 0x0000004F\r
+\r
+\r
+/**\r
+ Package. See http://biosbits.org.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
+ /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
+ /// MHz.\r
+ ///\r
+ UINT32 MaximumNonTurboRatio:8;\r
+ UINT32 Reserved2:7;\r
+ ///\r
+ /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that\r
+ /// Protected Processor Inventory Number (PPIN) capability can be enabled\r
+ /// for privileged system inventory agent to read PPIN from MSR_PPIN. When\r
+ /// set to 0, PPIN capability is not supported. An attempt to access\r
+ /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.\r
+ ///\r
+ UINT32 PPIN_CAP:1;\r
+ UINT32 Reserved3:4;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
+ /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
+ /// Turbo mode is disabled.\r
+ ///\r
+ UINT32 RatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
+ /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
+ /// programmable.\r
+ ///\r
+ UINT32 TDPLimit:1;\r
+ ///\r
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r
+ /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r
+ /// specify an temperature offset.\r
+ ///\r
+ UINT32 TJOFFSET:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
+ /// minimum ratio (maximum efficiency) that the processor can operates, in\r
+ /// units of 100MHz.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 Reserved6:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;\r
+\r
+\r
+/**\r
+ Package. MC Bank Error Configuration (R/W).\r
+\r
+ @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
+ /// to log additional info in bits 36:32.\r
+ ///\r
+ UINT32 MemErrorLogEnable:1;\r
+ UINT32 Reserved2:30;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which\r
+ /// PROCHOT# will be asserted. The value is degree C.\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ ///\r
+ /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature\r
+ /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#\r
+ /// will assert at the offset target temperature. Write is permitted only\r
+ /// MSR_PLATFORM_INFO.[30] is set.\r
+ ///\r
+ UINT32 TCCActivationOffset:4;\r
+ UINT32 Reserved2:4;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
+ /// limit of 9 core active.\r
+ ///\r
+ UINT32 Maximum9C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
+ /// limit of 10core active.\r
+ ///\r
+ UINT32 Maximum10C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
+ /// limit of 11 core active.\r
+ ///\r
+ UINT32 Maximum11C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
+ /// limit of 12 core active.\r
+ ///\r
+ UINT32 Maximum12C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
+ /// limit of 13 core active.\r
+ ///\r
+ UINT32 Maximum13C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
+ /// limit of 14 core active.\r
+ ///\r
+ UINT32 Maximum14C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
+ /// limit of 15 core active.\r
+ ///\r
+ UINT32 Maximum15C:8;\r
+ UINT32 Reserved:7;\r
+ ///\r
+ /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
+ /// the processor uses override configuration specified in\r
+ /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
+ /// uses factory-set configuration (Default).\r
+ ///\r
+ UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 5:0] Recoverable Address LSB.\r
+ ///\r
+ UINT32 RecoverableAddressLSB:6;\r
+ ///\r
+ /// [Bits 8:6] Address Mode.\r
+ ///\r
+ UINT32 AddressMode:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bits 31:16] PCI Express Requestor ID.\r
+ ///\r
+ UINT32 PCIExpressRequestorID:16;\r
+ ///\r
+ /// [Bits 39:32] PCI Express Segment Number.\r
+ ///\r
+ UINT32 PCIExpressSegmentNumber:8;\r
+ UINT32 Reserved2:24;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
+ and its corresponding slice of L3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.\r
+ @{\r
+**/\r
+#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474\r
+#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478\r
+#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
+ and its corresponding slice of L3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.\r
+ @{\r
+**/\r
+#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475\r
+#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479\r
+#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
+ and its corresponding slice of L3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.\r
+ @{\r
+**/\r
+#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476\r
+#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A\r
+#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
+ and its corresponding slice of L3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.\r
+ MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.\r
+ @{\r
+**/\r
+#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477\r
+#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B\r
+#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Package RAPL Perf Status (R/O).\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC3:1;\r
+ UINT32 Reserved1:28;\r
+ ///\r
+ /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC0:1;\r
+ ///\r
+ /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC1:1;\r
+ ///\r
+ /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC2:1;\r
+ ///\r
+ /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC3:1;\r
+ UINT32 Reserved2:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore perfmon per-socket global control.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00\r
+\r
+\r
+/**\r
+ Package. Uncore perfmon per-socket global status.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01\r
+\r
+\r
+/**\r
+ Package. Uncore perfmon per-socket global configuration.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon U-box wide status.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon box wide status.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon local box wide control.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon box wide filter.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon local box wide control.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon box wide filter.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon local box wide control.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon box wide filter.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon local box wide control.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon box wide filter.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon local box wide control.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon box wide filter.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon local box wide control.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon box wide filter.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon local box wide control.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon box wide filter.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 0.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 2.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 3.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
+**/\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel processors based on the Nehalem microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __NEHALEM_MSR_H__\r
+#define __NEHALEM_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel processors based on the Nehalem microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x1A || \\r
+ DisplayModel == 0x1E || \\r
+ DisplayModel == 0x1F || \\r
+ DisplayModel == 0x2E \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Package. Model Specific Platform ID (R).\r
+\r
+ @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);\r
+ @endcode\r
+ @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
+**/\r
+#define MSR_NEHALEM_PLATFORM_ID 0x00000017\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:18;\r
+ ///\r
+ /// [Bits 52:50] See Table 2-2.\r
+ ///\r
+ UINT32 PlatformId:3;\r
+ UINT32 Reserved3:11;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_PLATFORM_ID_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. SMI Counter (R/O).\r
+\r
+ @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_SMI_COUNT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);\r
+ @endcode\r
+ @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
+**/\r
+#define MSR_NEHALEM_SMI_COUNT 0x00000034\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r
+ /// RESET.\r
+ ///\r
+ UINT32 SMICount:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_SMI_COUNT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. see http://biosbits.org.\r
+\r
+ @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
+**/\r
+#define MSR_NEHALEM_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
+ /// of the frequency that invariant TSC runs at. The invariant TSC\r
+ /// frequency can be computed by multiplying this ratio by 133.33 MHz.\r
+ ///\r
+ UINT32 MaximumNonTurboRatio:8;\r
+ UINT32 Reserved2:12;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
+ /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
+ /// Turbo mode is disabled.\r
+ ///\r
+ UINT32 RatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)\r
+ /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are\r
+ /// programmable, and when set to 0, indicates TDC and TDP Limits for\r
+ /// Turbo mode are not programmable.\r
+ ///\r
+ UINT32 TDC_TDPLimit:1;\r
+ UINT32 Reserved3:2;\r
+ UINT32 Reserved4:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
+ /// minimum ratio (maximum efficiency) that the processor can operates, in\r
+ /// units of 133.33MHz.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 Reserved5:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are\r
+ processor specific C-state code names, unrelated to MWAIT extension C-state\r
+ parameters or ACPI CStates. See http://biosbits.org.\r
+\r
+ @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
+**/\r
+#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power). for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r
+ /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package\r
+ /// C-state limit. Note: This field cannot be used to limit package\r
+ /// C-state to C3.\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
+ /// IO_read instructions sent to IO register specified by\r
+ /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
+ /// until next reset.\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:8;\r
+ ///\r
+ /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores\r
+ /// in a deep C-State will wake only when the event message is destined\r
+ /// for that core. When 0, all processor cores in a deep C-State will wake\r
+ /// for an event message.\r
+ ///\r
+ UINT32 InterruptFiltering:1;\r
+ ///\r
+ /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
+ /// will conditionally demote C6/C7 requests to C3 based on uncore\r
+ /// auto-demote information.\r
+ ///\r
+ UINT32 C3AutoDemotion:1;\r
+ ///\r
+ /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
+ /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
+ /// auto-demote information.\r
+ ///\r
+ UINT32 C1AutoDemotion:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Package C State Demotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateDemotion:1;\r
+ ///\r
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateUndemotion:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Power Management IO Redirection in C-state (R/W) See\r
+ http://biosbits.org.\r
+\r
+ @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);\r
+ AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
+**/\r
+#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
+ /// visible to software for IO redirection. If IO MWAIT Redirection is\r
+ /// enabled, reads to this address will be consumed by the power\r
+ /// management logic and decoded to MWAIT instructions. When IO port\r
+ /// address redirection is enabled, this is the IO port address reported\r
+ /// to the OS/software.\r
+ ///\r
+ UINT32 Lvl2Base:16;\r
+ ///\r
+ /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
+ /// maximum C-State code name to be included when IO read to MWAIT\r
+ /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r
+ /// is the max C-State to include 001b - C6 is the max C-State to include\r
+ /// 010b - C7 is the max C-State to include.\r
+ ///\r
+ UINT32 CStateRange:3;\r
+ UINT32 Reserved1:13;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See\r
+ /// Table 2-2. Default value is 1.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved4:3;\r
+ ///\r
+ /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ UINT32 Reserved6:3;\r
+ ///\r
+ /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved7:8;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved9:3;\r
+ ///\r
+ /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
+ /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
+ /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
+ /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
+ /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
+ /// the power-on default value is used by BIOS to detect hardware support\r
+ /// of turbo mode. If power-on default value is 1, turbo mode is available\r
+ /// in the processor. If power-on default value is 0, turbo mode is not\r
+ /// available.\r
+ ///\r
+ UINT32 TurboModeDisable:1;\r
+ UINT32 Reserved10:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Thread.\r
+\r
+ @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
+**/\r
+#define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
+ /// PROCHOT# will be asserted. The value is degree C.\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ UINT32 Reserved2:8;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER;\r
+\r
+\r
+/**\r
+ Miscellaneous Feature Control (R/W).\r
+\r
+ @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L2 hardware prefetcher, which fetches additional lines of code or data\r
+ /// into the L2 cache.\r
+ ///\r
+ UINT32 L2HardwarePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
+ /// disables the adjacent cache line prefetcher, which fetches the cache\r
+ /// line that comprises a cache line pair (128 bytes).\r
+ ///\r
+ UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
+ /// the L1 data cache prefetcher, which fetches the next cache line into\r
+ /// L1 data cache.\r
+ ///\r
+ UINT32 DCUHardwarePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
+ /// data cache IP prefetcher, which uses sequential load history (based on\r
+ /// instruction Pointer of previous loads) to determine whether to\r
+ /// prefetch additional lines.\r
+ ///\r
+ UINT32 DCUIPPrefetcherDisable:1;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6\r
+\r
+\r
+/**\r
+ See http://biosbits.org.\r
+\r
+ @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);\r
+ AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
+**/\r
+#define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,\r
+ /// enables hardware coordination of Enhanced Intel Speedstep Technology\r
+ /// request from processor cores; When 1, disables hardware coordination\r
+ /// of Enhanced Intel Speedstep Technology requests.\r
+ ///\r
+ UINT32 EISTHardwareCoordinationDisable:1;\r
+ ///\r
+ /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes\r
+ /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with\r
+ /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by\r
+ /// CPUID.(EAX=06h):ECX[3].\r
+ ///\r
+ UINT32 EnergyPerformanceBiasEnable:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_MISC_PWR_MGMT_REGISTER;\r
+\r
+\r
+/**\r
+ See http://biosbits.org.\r
+\r
+ @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);\r
+ AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.\r
+**/\r
+#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt\r
+ /// granularity.\r
+ ///\r
+ UINT32 TDPLimit:15;\r
+ ///\r
+ /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0\r
+ /// indicates override is not active, and a value = 1 indicates active.\r
+ ///\r
+ UINT32 TDPLimitOverrideEnable:1;\r
+ ///\r
+ /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp\r
+ /// granularity.\r
+ ///\r
+ UINT32 TDCLimit:15;\r
+ ///\r
+ /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0\r
+ /// indicates override is not active, and a value = 1 indicates active.\r
+ ///\r
+ UINT32 TDCLimitOverrideEnable:1;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+ @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
+ "Filtering of Last Branch Records.".\r
+\r
+ @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_LBR_SELECT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);\r
+ AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
+**/\r
+#define MSR_NEHALEM_LBR_SELECT 0x000001C8\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] CPL_EQ_0.\r
+ ///\r
+ UINT32 CPL_EQ_0:1;\r
+ ///\r
+ /// [Bit 1] CPL_NEQ_0.\r
+ ///\r
+ UINT32 CPL_NEQ_0:1;\r
+ ///\r
+ /// [Bit 2] JCC.\r
+ ///\r
+ UINT32 JCC:1;\r
+ ///\r
+ /// [Bit 3] NEAR_REL_CALL.\r
+ ///\r
+ UINT32 NEAR_REL_CALL:1;\r
+ ///\r
+ /// [Bit 4] NEAR_IND_CALL.\r
+ ///\r
+ UINT32 NEAR_IND_CALL:1;\r
+ ///\r
+ /// [Bit 5] NEAR_RET.\r
+ ///\r
+ UINT32 NEAR_RET:1;\r
+ ///\r
+ /// [Bit 6] NEAR_IND_JMP.\r
+ ///\r
+ UINT32 NEAR_IND_JMP:1;\r
+ ///\r
+ /// [Bit 7] NEAR_REL_JMP.\r
+ ///\r
+ UINT32 NEAR_REL_JMP:1;\r
+ ///\r
+ /// [Bit 8] FAR_BRANCH.\r
+ ///\r
+ UINT32 FAR_BRANCH:1;\r
+ UINT32 Reserved1:23;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_LBR_SELECT_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
+ that points to the MSR containing the most recent branch record. See\r
+ MSR_LASTBRANCH_0_FROM_IP (at 680H).\r
+\r
+ @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
+ last branch instruction that the processor executed prior to the last\r
+ exception that was generated or the last interrupt that was handled.\r
+\r
+ @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);\r
+ @endcode\r
+ @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
+**/\r
+#define MSR_NEHALEM_LER_FROM_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
+ to the target of the last branch instruction that the processor executed\r
+ prior to the last exception that was generated or the last interrupt that\r
+ was handled.\r
+\r
+ @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);\r
+ @endcode\r
+ @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
+**/\r
+#define MSR_NEHALEM_LER_TO_LIP 0x000001DE\r
+\r
+\r
+/**\r
+ Core. Power Control Register. See http://biosbits.org.\r
+\r
+ @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_POWER_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
+**/\r
+#define MSR_NEHALEM_POWER_CTL 0x000001FC\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r
+ /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r
+ /// operating point when all execution cores enter MWAIT (C1).\r
+ ///\r
+ UINT32 C1EEnable:1;\r
+ UINT32 Reserved2:30;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_POWER_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. (RO).\r
+\r
+ @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);\r
+ @endcode\r
+ @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:29;\r
+ ///\r
+ /// [Bit 61] UNC_Ovf Uncore overflowed if 1.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ UINT32 Reserved3:2;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. (R/W).\r
+\r
+ @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:29;\r
+ ///\r
+ /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ UINT32 Reserved3:2;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
+\r
+ @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
+**/\r
+#define MSR_NEHALEM_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC3:1;\r
+ UINT32 Reserved1:28;\r
+ ///\r
+ /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC0:1;\r
+ ///\r
+ /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC1:1;\r
+ ///\r
+ /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC2:1;\r
+ ///\r
+ /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC3:1;\r
+ UINT32 Reserved2:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r
+ Facility.".\r
+\r
+ @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);\r
+ AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r
+**/\r
+#define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
+ /// that will be counted. (R/W).\r
+ ///\r
+ UINT32 MinimumThreshold:16;\r
+ UINT32 Reserved1:16;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_PEBS_LD_LAT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C3 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
+**/\r
+#define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C6 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C7 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
+**/\r
+#define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
+ Residency Counter. (R/O) Value since last reset that this core is in\r
+ processor-specific C3 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
+**/\r
+#define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
+ Residency Counter. (R/O) Value since last reset that this core is in\r
+ processor-specific C6 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
+ branch record registers on the last branch record stack. The From_IP part of\r
+ the stack contains pointers to the source instruction. See also: - Last\r
+ Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in\r
+ Section 17.4.8.1.\r
+\r
+ @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);\r
+ AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F\r
+/// @}\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
+ record registers on the last branch record stack. This part of the stack\r
+ contains pointers to the destination instruction.\r
+\r
+ @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);\r
+ AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
+ MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF\r
+/// @}\r
+\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);\r
+ AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.\r
+**/\r
+#define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] From M to S (R/W).\r
+ ///\r
+ UINT32 FromMtoS:1;\r
+ ///\r
+ /// [Bit 1] From E to S (R/W).\r
+ ///\r
+ UINT32 FromEtoS:1;\r
+ ///\r
+ /// [Bit 2] From S to S (R/W).\r
+ ///\r
+ UINT32 FromStoS:1;\r
+ ///\r
+ /// [Bit 3] From F to S (R/W).\r
+ ///\r
+ UINT32 FromFtoS:1;\r
+ ///\r
+ /// [Bit 4] From M to I (R/W).\r
+ ///\r
+ UINT32 FromMtoI:1;\r
+ ///\r
+ /// [Bit 5] From E to I (R/W).\r
+ ///\r
+ UINT32 FromEtoI:1;\r
+ ///\r
+ /// [Bit 6] From S to I (R/W).\r
+ ///\r
+ UINT32 FromStoI:1;\r
+ ///\r
+ /// [Bit 7] From F to I (R/W).\r
+ ///\r
+ UINT32 FromFtoI:1;\r
+ UINT32 Reserved1:24;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER;\r
+\r
+\r
+/**\r
+ Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
+ Facility.".\r
+\r
+ @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391\r
+\r
+\r
+/**\r
+ Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
+ Facility.".\r
+\r
+ @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392\r
+\r
+\r
+/**\r
+ Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
+ Facility.".\r
+\r
+ @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393\r
+\r
+\r
+/**\r
+ Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
+ Facility.".\r
+\r
+ @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394\r
+\r
+\r
+/**\r
+ Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
+ Facility.".\r
+\r
+ @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395\r
+\r
+\r
+/**\r
+ Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".\r
+\r
+ @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);\r
+ AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.\r
+**/\r
+#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396\r
+\r
+\r
+/**\r
+ Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration\r
+ Facility.".\r
+\r
+ @param ECX MSR_NEHALEM_UNCORE_PMCi\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.\r
+ MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.\r
+ MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.\r
+ MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.\r
+ MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.\r
+ MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.\r
+ MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.\r
+ MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_NEHALEM_UNCORE_PMC0 0x000003B0\r
+#define MSR_NEHALEM_UNCORE_PMC1 0x000003B1\r
+#define MSR_NEHALEM_UNCORE_PMC2 0x000003B2\r
+#define MSR_NEHALEM_UNCORE_PMC3 0x000003B3\r
+#define MSR_NEHALEM_UNCORE_PMC4 0x000003B4\r
+#define MSR_NEHALEM_UNCORE_PMC5 0x000003B5\r
+#define MSR_NEHALEM_UNCORE_PMC6 0x000003B6\r
+#define MSR_NEHALEM_UNCORE_PMC7 0x000003B7\r
+/// @}\r
+\r
+/**\r
+ Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration\r
+ Facility.".\r
+\r
+ @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.\r
+ MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.\r
+ MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.\r
+ MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.\r
+ MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.\r
+ MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.\r
+ MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.\r
+ MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon fixed counter.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon fixed counter control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon global control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon global status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon global overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.\r
+**/\r
+#define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);\r
+ AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.\r
+**/\r
+#define MSR_NEHALEM_U_PMON_CTR 0x00000C11\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1vperfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_CTR0 0x00000C91\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_CTR1 0x00000C93\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_CTR2 0x00000C95\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96\r
+\r
+\r
+/**\r
+ Package. Uncore W-box perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_W_PMON_CTR3 0x00000C97\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon time stamp unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon DSP unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon ISS unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon MAP unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon MIC THR select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon PGT unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon PLD unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon ZDP unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon time stamp unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon DSP unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon ISS unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon MAP unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon MIC THR select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon PGT unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon PLD unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon ZDP unit select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 0 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon event select MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E\r
+\r
+\r
+/**\r
+ Package. Uncore R-box 1 perfmon counter MSR.\r
+\r
+ @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);\r
+ AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.\r
+**/\r
+#define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon local box match MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 0 perfmon local box mask MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.\r
+**/\r
+#define MSR_NEHALEM_B0_PMON_MASK 0x00000E46\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon local box match MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 0 perfmon local box mask MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.\r
+**/\r
+#define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon local box match MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D\r
+\r
+\r
+/**\r
+ Package. Uncore B-box 1 perfmon local box mask MSR.\r
+\r
+ @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);\r
+ AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.\r
+**/\r
+#define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon local box address match/mask config MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon local box address match MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 0 perfmon local box address mask MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.\r
+**/\r
+#define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon local box match MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59\r
+\r
+\r
+/**\r
+ Package. Uncore S-box 1 perfmon local box mask MSR.\r
+\r
+ @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);\r
+ AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.\r
+**/\r
+#define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon local box address match/mask config MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon local box address match MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D\r
+\r
+\r
+/**\r
+ Package. Uncore M-box 1 perfmon local box address mask MSR.\r
+\r
+ @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);\r
+ AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);\r
+ @endcode\r
+ @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.\r
+**/\r
+#define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for P6 Family Processors.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __P6_MSR_H__\r
+#define __P6_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is P6 Family Processors?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x03 || \\r
+ DisplayModel == 0x05 || \\r
+ DisplayModel == 0x07 || \\r
+ DisplayModel == 0x08 || \\r
+ DisplayModel == 0x0A || \\r
+ DisplayModel == 0x0B \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ See Section 2.22, "MSRs in Pentium Processors.".\r
+\r
+ @param ECX MSR_P6_P5_MC_ADDR (0x00000000)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);\r
+ AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
+**/\r
+#define MSR_P6_P5_MC_ADDR 0x00000000\r
+\r
+\r
+/**\r
+ See Section 2.22, "MSRs in Pentium Processors.".\r
+\r
+ @param ECX MSR_P6_P5_MC_TYPE (0x00000001)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);\r
+ AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);\r
+ @endcode\r
+ @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
+**/\r
+#define MSR_P6_P5_MC_TYPE 0x00000001\r
+\r
+\r
+/**\r
+ See Section 17.17, "Time-Stamp Counter.".\r
+\r
+ @param ECX MSR_P6_TSC (0x00000010)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_TSC);\r
+ AsmWriteMsr64 (MSR_P6_TSC, Msr);\r
+ @endcode\r
+ @note MSR_P6_TSC is defined as TSC in SDM.\r
+**/\r
+#define MSR_P6_TSC 0x00000010\r
+\r
+\r
+/**\r
+ Platform ID (R) The operating system can use this MSR to determine "slot"\r
+ information for the processor and the proper microcode update to load.\r
+\r
+ @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_IA32_PLATFORM_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);\r
+ @endcode\r
+ @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r
+**/\r
+#define MSR_P6_IA32_PLATFORM_ID 0x00000017\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:18;\r
+ ///\r
+ /// [Bits 52:50] Platform Id (R) Contains information concerning the\r
+ /// intended platform for the processor.\r
+ ///\r
+ /// 52 51 50\r
+ /// 0 0 0 Processor Flag 0.\r
+ /// 0 0 1 Processor Flag 1\r
+ /// 0 1 0 Processor Flag 2\r
+ /// 0 1 1 Processor Flag 3\r
+ /// 1 0 0 Processor Flag 4\r
+ /// 1 0 1 Processor Flag 5\r
+ /// 1 1 0 Processor Flag 6\r
+ /// 1 1 1 Processor Flag 7\r
+ ///\r
+ UINT32 PlatformId:3;\r
+ ///\r
+ /// [Bits 56:53] L2 Cache Latency Read.\r
+ ///\r
+ UINT32 L2CacheLatencyRead:4;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 60] Clock Frequency Ratio Read.\r
+ ///\r
+ UINT32 ClockFrequencyRatioRead:1;\r
+ UINT32 Reserved4:3;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_IA32_PLATFORM_ID_REGISTER;\r
+\r
+\r
+/**\r
+ Section 10.4.4, "Local APIC Status and Location.".\r
+\r
+ @param ECX MSR_P6_APIC_BASE (0x0000001B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_APIC_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_APIC_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_APIC_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);\r
+ AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.\r
+**/\r
+#define MSR_P6_APIC_BASE 0x0000001B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_APIC_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.\r
+ ///\r
+ UINT32 BSP:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =\r
+ /// Disabled.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bits 31:12] APIC Base Address.\r
+ ///\r
+ UINT32 ApicBase:20;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_APIC_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
+ features; (R) indicates current processor configuration.\r
+\r
+ @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_EBL_CR_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);\r
+ AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.\r
+**/\r
+#define MSR_P6_EBL_CR_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 DataErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)\r
+ /// 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 ResponseErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 AERR_DriveEnable:1;\r
+ ///\r
+ /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =\r
+ /// Disabled.\r
+ ///\r
+ UINT32 BERR_Enable:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =\r
+ /// Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 BERR_DriverEnable:1;\r
+ ///\r
+ /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 BINIT_DriverEnable:1;\r
+ ///\r
+ /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 OutputTriStateEnable:1;\r
+ ///\r
+ /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 ExecuteBIST:1;\r
+ ///\r
+ /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 AERR_ObservationEnabled:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 BINIT_ObservationEnabled:1;\r
+ ///\r
+ /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.\r
+ ///\r
+ UINT32 InOrderQueueDepth:1;\r
+ ///\r
+ /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.\r
+ ///\r
+ UINT32 ResetVector:1;\r
+ ///\r
+ /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.\r
+ ///\r
+ UINT32 FRCModeEnable:1;\r
+ ///\r
+ /// [Bits 17:16] APIC Cluster ID (R).\r
+ ///\r
+ UINT32 APICClusterID:2;\r
+ ///\r
+ /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =\r
+ /// 133MHz 11 = Reserved.\r
+ ///\r
+ UINT32 SystemBusFrequency:2;\r
+ ///\r
+ /// [Bits 21:20] Symmetric Arbitration ID (R).\r
+ ///\r
+ UINT32 SymmetricArbitrationID:2;\r
+ ///\r
+ /// [Bits 25:22] Clock Frequency Ratio (R).\r
+ ///\r
+ UINT32 ClockFrequencyRatio:4;\r
+ ///\r
+ /// [Bit 26] Low Power Mode Enable (R/W).\r
+ ///\r
+ UINT32 LowPowerModeEnable:1;\r
+ ///\r
+ /// [Bit 27] Clock Frequency Ratio.\r
+ ///\r
+ UINT32 ClockFrequencyRatio1:1;\r
+ UINT32 Reserved4:4;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_EBL_CR_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ Test Control Register.\r
+\r
+ @param ECX MSR_P6_TEST_CTL (0x00000033)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_TEST_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_TEST_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_TEST_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);\r
+ AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.\r
+**/\r
+#define MSR_P6_TEST_CTL 0x00000033\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_TEST_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:30;\r
+ ///\r
+ /// [Bit 30] Streaming Buffer Disable.\r
+ ///\r
+ UINT32 StreamingBufferDisable:1;\r
+ ///\r
+ /// [Bit 31] Disable LOCK# Assertion for split locked access.\r
+ ///\r
+ UINT32 Disable_LOCK:1;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_TEST_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ BIOS Update Trigger Register.\r
+\r
+ @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);\r
+ AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);\r
+ @endcode\r
+ @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.\r
+**/\r
+#define MSR_P6_BIOS_UPDT_TRIG 0x00000079\r
+\r
+\r
+/**\r
+ Chunk n data register D[63:0]: used to write to and read from the L2.\r
+\r
+ @param ECX MSR_P6_BBL_CR_Dn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);\r
+ @endcode\r
+ @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.\r
+ MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.\r
+ MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.\r
+ @{\r
+**/\r
+#define MSR_P6_BBL_CR_D0 0x00000088\r
+#define MSR_P6_BBL_CR_D1 0x00000089\r
+#define MSR_P6_BBL_CR_D2 0x0000008A\r
+/// @}\r
+\r
+\r
+/**\r
+ BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to\r
+ write to and read from the L2 depending on the usage model.\r
+\r
+ @param ECX MSR_P6_BIOS_SIGN (0x0000008B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);\r
+ AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);\r
+ @endcode\r
+ @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.\r
+**/\r
+#define MSR_P6_BIOS_SIGN 0x0000008B\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_PERFCTR0 (0x000000C1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.\r
+ MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.\r
+ @{\r
+**/\r
+#define MSR_P6_PERFCTR0 0x000000C1\r
+#define MSR_P6_PERFCTR1 0x000000C2\r
+/// @}\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRCAP (0x000000FE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);\r
+ AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.\r
+**/\r
+#define MSR_P6_MTRRCAP 0x000000FE\r
+\r
+\r
+/**\r
+ Address register: used to send specified address (A31-A3) to L2 during cache\r
+ initialization accesses.\r
+\r
+ @param ECX MSR_P6_BBL_CR_ADDR (0x00000116)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_BBL_CR_ADDR_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.\r
+**/\r
+#define MSR_P6_BBL_CR_ADDR 0x00000116\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bits 31:3] Address bits\r
+ ///\r
+ UINT32 Address:29;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_BBL_CR_ADDR_REGISTER;\r
+\r
+\r
+/**\r
+ Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.\r
+\r
+ @param ECX MSR_P6_BBL_CR_DECC (0x00000118)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);\r
+ @endcode\r
+ @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.\r
+**/\r
+#define MSR_P6_BBL_CR_DECC 0x00000118\r
+\r
+\r
+/**\r
+ Control register: used to program L2 commands to be issued via cache\r
+ configuration accesses mechanism. Also receives L2 lookup response.\r
+\r
+ @param ECX MSR_P6_BBL_CR_CTL (0x00000119)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_BBL_CR_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.\r
+**/\r
+#define MSR_P6_BBL_CR_CTL 0x00000119\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_BBL_CR_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] L2 Command\r
+ /// Data Read w/ LRU update (RLU)\r
+ /// Tag Read w/ Data Read (TRR)\r
+ /// Tag Inquire (TI)\r
+ /// L2 Control Register Read (CR)\r
+ /// L2 Control Register Write (CW)\r
+ /// Tag Write w/ Data Read (TWR)\r
+ /// Tag Write w/ Data Write (TWW)\r
+ /// Tag Write (TW).\r
+ ///\r
+ UINT32 L2Command:5;\r
+ ///\r
+ /// [Bits 6:5] State to L2\r
+ ///\r
+ UINT32 StateToL2:2;\r
+ UINT32 Reserved:1;\r
+ ///\r
+ /// [Bits 9:8] Way to L2.\r
+ ///\r
+ UINT32 WayToL2:2;\r
+ ///\r
+ /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.\r
+ ///\r
+ UINT32 Way:2;\r
+ ///\r
+ /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.\r
+ ///\r
+ UINT32 MESI:2;\r
+ ///\r
+ /// [Bits 15:14] State from L2.\r
+ ///\r
+ UINT32 StateFromL2:2;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 17] L2 Hit.\r
+ ///\r
+ UINT32 L2Hit:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bits 20:19] User supplied ECC.\r
+ ///\r
+ UINT32 UserEcc:2;\r
+ ///\r
+ /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.\r
+ ///\r
+ UINT32 ProcessorNumber:1;\r
+ UINT32 Reserved4:10;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_BBL_CR_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Trigger register: used to initiate a cache configuration accesses access,\r
+ Write only with Data = 0.\r
+\r
+ @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);\r
+ @endcode\r
+ @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.\r
+**/\r
+#define MSR_P6_BBL_CR_TRIG 0x0000011A\r
+\r
+\r
+/**\r
+ Busy register: indicates when a cache configuration accesses L2 command is\r
+ in progress. D[0] = 1 = BUSY.\r
+\r
+ @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);\r
+ @endcode\r
+ @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.\r
+**/\r
+#define MSR_P6_BBL_CR_BUSY 0x0000011B\r
+\r
+\r
+/**\r
+ Control register 3: used to configure the L2 Cache.\r
+\r
+ @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_BBL_CR_CTL3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);\r
+ AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.\r
+**/\r
+#define MSR_P6_BBL_CR_CTL3 0x0000011E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] L2 Configured (read/write ).\r
+ ///\r
+ UINT32 L2Configured:1;\r
+ ///\r
+ /// [Bits 4:1] L2 Cache Latency (read/write).\r
+ ///\r
+ UINT32 L2CacheLatency:4;\r
+ ///\r
+ /// [Bit 5] ECC Check Enable (read/write).\r
+ ///\r
+ UINT32 ECCCheckEnable:1;\r
+ ///\r
+ /// [Bit 6] Address Parity Check Enable (read/write).\r
+ ///\r
+ UINT32 AddressParityCheckEnable:1;\r
+ ///\r
+ /// [Bit 7] CRTN Parity Check Enable (read/write).\r
+ ///\r
+ UINT32 CRTNParityCheckEnable:1;\r
+ ///\r
+ /// [Bit 8] L2 Enabled (read/write).\r
+ ///\r
+ UINT32 L2Enabled:1;\r
+ ///\r
+ /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way\r
+ /// Reserved.\r
+ ///\r
+ UINT32 L2Associativity:2;\r
+ ///\r
+ /// [Bits 12:11] Number of L2 banks (read only).\r
+ ///\r
+ UINT32 L2Banks:2;\r
+ ///\r
+ /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes\r
+ /// 1MByte 2MByte 4MBytes.\r
+ ///\r
+ UINT32 CacheSizePerBank:5;\r
+ ///\r
+ /// [Bit 18] Cache State error checking enable (read/write).\r
+ ///\r
+ UINT32 CacheStateErrorEnable:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes\r
+ /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.\r
+ ///\r
+ UINT32 L2AddressRange:3;\r
+ ///\r
+ /// [Bit 23] L2 Hardware Disable (read only).\r
+ ///\r
+ UINT32 L2HardwareDisable:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 25] Cache bus fraction (read only).\r
+ ///\r
+ UINT32 CacheBusFraction:1;\r
+ UINT32 Reserved3:6;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_BBL_CR_CTL3_REGISTER;\r
+\r
+\r
+/**\r
+ CS register target for CPL 0 code.\r
+\r
+ @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);\r
+ AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);\r
+ @endcode\r
+ @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.\r
+**/\r
+#define MSR_P6_SYSENTER_CS_MSR 0x00000174\r
+\r
+\r
+/**\r
+ Stack pointer for CPL 0 stack.\r
+\r
+ @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);\r
+ AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);\r
+ @endcode\r
+ @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.\r
+**/\r
+#define MSR_P6_SYSENTER_ESP_MSR 0x00000175\r
+\r
+\r
+/**\r
+ CPL 0 code entry point.\r
+\r
+ @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);\r
+ AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);\r
+ @endcode\r
+ @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.\r
+**/\r
+#define MSR_P6_SYSENTER_EIP_MSR 0x00000176\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MCG_CAP (0x00000179)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);\r
+ AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);\r
+ @endcode\r
+ @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.\r
+**/\r
+#define MSR_P6_MCG_CAP 0x00000179\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MCG_STATUS (0x0000017A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);\r
+ AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.\r
+**/\r
+#define MSR_P6_MCG_STATUS 0x0000017A\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MCG_CTL (0x0000017B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);\r
+ AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);\r
+ @endcode\r
+ @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.\r
+**/\r
+#define MSR_P6_MCG_CTL 0x0000017B\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_PERFEVTSELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_PERFEVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_PERFEVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_PERFEVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM.\r
+ MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.\r
+ @{\r
+**/\r
+#define MSR_P6_PERFEVTSEL0 0x00000186\r
+#define MSR_P6_PERFEVTSEL1 0x00000187\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and\r
+ #MSR_P6_PERFEVTSEL1.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Event Select Refer to Performance Counter section for a\r
+ /// list of event encodings.\r
+ ///\r
+ UINT32 EventSelect:8;\r
+ ///\r
+ /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable\r
+ /// all count options.\r
+ ///\r
+ UINT32 UMASK:8;\r
+ ///\r
+ /// [Bit 16] USER Controls the counting of events at Privilege levels of\r
+ /// 1, 2, and 3.\r
+ ///\r
+ UINT32 USR:1;\r
+ ///\r
+ /// [Bit 17] OS Controls the counting of events at Privilege level of 0.\r
+ ///\r
+ UINT32 OS:1;\r
+ ///\r
+ /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.\r
+ ///\r
+ UINT32 E:1;\r
+ ///\r
+ /// [Bit 19] PC Enabled the signaling of performance counter overflow via\r
+ /// BP0 pin.\r
+ ///\r
+ UINT32 PC:1;\r
+ ///\r
+ /// [Bit 20] INT Enables the signaling of counter overflow via input to\r
+ /// APIC 1 = Enable 0 = Disable.\r
+ ///\r
+ UINT32 INT:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 22] ENABLE Enables the counting of performance events in both\r
+ /// counters 1 = Enable 0 = Disable.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0\r
+ /// = Non-Inverted.\r
+ ///\r
+ UINT32 INV:1;\r
+ ///\r
+ /// [Bits 31:24] CMASK (Counter Mask).\r
+ ///\r
+ UINT32 CMASK:8;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_PERFEVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_DEBUGCTLMSR_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);\r
+ AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.\r
+**/\r
+#define MSR_P6_DEBUGCTLMSR 0x000001D9\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable/Disable Last Branch Records.\r
+ ///\r
+ UINT32 LBR:1;\r
+ ///\r
+ /// [Bit 1] Branch Trap Flag.\r
+ ///\r
+ UINT32 BTF:1;\r
+ ///\r
+ /// [Bit 2] Performance Monitoring/Break Point Pins.\r
+ ///\r
+ UINT32 PB0:1;\r
+ ///\r
+ /// [Bit 3] Performance Monitoring/Break Point Pins.\r
+ ///\r
+ UINT32 PB1:1;\r
+ ///\r
+ /// [Bit 4] Performance Monitoring/Break Point Pins.\r
+ ///\r
+ UINT32 PB2:1;\r
+ ///\r
+ /// [Bit 5] Performance Monitoring/Break Point Pins.\r
+ ///\r
+ UINT32 PB3:1;\r
+ ///\r
+ /// [Bit 6] Enable/Disable Execution Trace Messages.\r
+ ///\r
+ UINT32 TR:1;\r
+ UINT32 Reserved1:25;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_DEBUGCTLMSR_REGISTER;\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);\r
+ AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);\r
+ @endcode\r
+ @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.\r
+**/\r
+#define MSR_P6_LASTBRANCHFROMIP 0x000001DB\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);\r
+ AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);\r
+ @endcode\r
+ @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.\r
+**/\r
+#define MSR_P6_LASTBRANCHTOIP 0x000001DC\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_LASTINTFROMIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);\r
+ AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);\r
+ @endcode\r
+ @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.\r
+**/\r
+#define MSR_P6_LASTINTFROMIP 0x000001DD\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_LASTINTTOIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);\r
+ AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);\r
+ @endcode\r
+ @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.\r
+**/\r
+#define MSR_P6_LASTINTTOIP 0x000001DE\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRPHYSBASEn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);\r
+ AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.\r
+ MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.\r
+ MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.\r
+ MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.\r
+ MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.\r
+ MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.\r
+ MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.\r
+ MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_P6_MTRRPHYSBASE0 0x00000200\r
+#define MSR_P6_MTRRPHYSBASE1 0x00000202\r
+#define MSR_P6_MTRRPHYSBASE2 0x00000204\r
+#define MSR_P6_MTRRPHYSBASE3 0x00000206\r
+#define MSR_P6_MTRRPHYSBASE4 0x00000208\r
+#define MSR_P6_MTRRPHYSBASE5 0x0000020A\r
+#define MSR_P6_MTRRPHYSBASE6 0x0000020C\r
+#define MSR_P6_MTRRPHYSBASE7 0x0000020E\r
+/// @}\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRPHYSMASKn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);\r
+ AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.\r
+ MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.\r
+ MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.\r
+ MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.\r
+ MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.\r
+ MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.\r
+ MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.\r
+ MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_P6_MTRRPHYSMASK0 0x00000201\r
+#define MSR_P6_MTRRPHYSMASK1 0x00000203\r
+#define MSR_P6_MTRRPHYSMASK2 0x00000205\r
+#define MSR_P6_MTRRPHYSMASK3 0x00000207\r
+#define MSR_P6_MTRRPHYSMASK4 0x00000209\r
+#define MSR_P6_MTRRPHYSMASK5 0x0000020B\r
+#define MSR_P6_MTRRPHYSMASK6 0x0000020D\r
+#define MSR_P6_MTRRPHYSMASK7 0x0000020F\r
+/// @}\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX64K_00000 0x00000250\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX16K_80000 0x00000258\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX16K_A0000 0x00000259\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX4K_C0000 0x00000268\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX4K_C8000 0x00000269\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX4K_D0000 0x0000026A\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX4K_D8000 0x0000026B\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX4K_E0000 0x0000026C\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX4K_E8000 0x0000026D\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX4K_F0000 0x0000026E\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);\r
+ AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);\r
+ @endcode\r
+ @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r
+**/\r
+#define MSR_P6_MTRRFIX4K_F8000 0x0000026F\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_MTRRDEFTYPE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);\r
+ AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.\r
+**/\r
+#define MSR_P6_MTRRDEFTYPE 0x000002FF\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Default memory type.\r
+ ///\r
+ UINT32 Type:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] Fixed MTRR enable.\r
+ ///\r
+ UINT32 FE:1;\r
+ ///\r
+ /// [Bit 11] MTRR Enable.\r
+ ///\r
+ UINT32 E:1;\r
+ UINT32 Reserved2:20;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_MTRRDEFTYPE_REGISTER;\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_P6_MC0_CTL (0x00000400)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);\r
+ AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);\r
+ @endcode\r
+ @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM.\r
+ MSR_P6_MC1_CTL is defined as MC1_CTL in SDM.\r
+ MSR_P6_MC2_CTL is defined as MC2_CTL in SDM.\r
+ MSR_P6_MC3_CTL is defined as MC3_CTL in SDM.\r
+ MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.\r
+ @{\r
+**/\r
+#define MSR_P6_MC0_CTL 0x00000400\r
+#define MSR_P6_MC1_CTL 0x00000404\r
+#define MSR_P6_MC2_CTL 0x00000408\r
+#define MSR_P6_MC3_CTL 0x00000410\r
+#define MSR_P6_MC4_CTL 0x0000040C\r
+/// @}\r
+\r
+\r
+/**\r
+\r
+ Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,\r
+ except bits 0, 4, 57, and 61 are hardcoded to 1.\r
+\r
+ @param ECX MSR_P6_MCn_STATUS\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_P6_MC_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_P6_MC_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_P6_MC_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);\r
+ AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM.\r
+ MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM.\r
+ MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM.\r
+ MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM.\r
+ MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.\r
+ @{\r
+**/\r
+#define MSR_P6_MC0_STATUS 0x00000401\r
+#define MSR_P6_MC1_STATUS 0x00000405\r
+#define MSR_P6_MC2_STATUS 0x00000409\r
+#define MSR_P6_MC3_STATUS 0x00000411\r
+#define MSR_P6_MC4_STATUS 0x0000040D\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_P6_MC0_STATUS to\r
+ #MSR_P6_MC4_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] MC_STATUS_MCACOD.\r
+ ///\r
+ UINT32 MC_STATUS_MCACOD:16;\r
+ ///\r
+ /// [Bits 31:16] MC_STATUS_MSCOD.\r
+ ///\r
+ UINT32 MC_STATUS_MSCOD:16;\r
+ UINT32 Reserved:25;\r
+ ///\r
+ /// [Bit 57] MC_STATUS_DAM.\r
+ ///\r
+ UINT32 MC_STATUS_DAM:1;\r
+ ///\r
+ /// [Bit 58] MC_STATUS_ADDRV.\r
+ ///\r
+ UINT32 MC_STATUS_ADDRV:1;\r
+ ///\r
+ /// [Bit 59] MC_STATUS_MISCV.\r
+ ///\r
+ UINT32 MC_STATUS_MISCV:1;\r
+ ///\r
+ /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is\r
+ /// hardcoded to 1.).\r
+ ///\r
+ UINT32 MC_STATUS_EN:1;\r
+ ///\r
+ /// [Bit 61] MC_STATUS_UC.\r
+ ///\r
+ UINT32 MC_STATUS_UC:1;\r
+ ///\r
+ /// [Bit 62] MC_STATUS_O.\r
+ ///\r
+ UINT32 MC_STATUS_O:1;\r
+ ///\r
+ /// [Bit 63] MC_STATUS_V.\r
+ ///\r
+ UINT32 MC_STATUS_V:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_P6_MC_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+\r
+ MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.\r
+\r
+ @param ECX MSR_P6_MC0_ADDR (0x00000402)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);\r
+ AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM.\r
+ MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM.\r
+ MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM.\r
+ MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM.\r
+ MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.\r
+ @{\r
+**/\r
+#define MSR_P6_MC0_ADDR 0x00000402\r
+#define MSR_P6_MC1_ADDR 0x00000406\r
+#define MSR_P6_MC2_ADDR 0x0000040A\r
+#define MSR_P6_MC3_ADDR 0x00000412\r
+#define MSR_P6_MC4_ADDR 0x0000040E\r
+/// @}\r
+\r
+\r
+/**\r
+ Defined in MCA architecture but not implemented in the P6 family processors.\r
+\r
+ @param ECX MSR_P6_MC0_MISC (0x00000403)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);\r
+ AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);\r
+ @endcode\r
+ @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM.\r
+ MSR_P6_MC1_MISC is defined as MC1_MISC in SDM.\r
+ MSR_P6_MC2_MISC is defined as MC2_MISC in SDM.\r
+ MSR_P6_MC3_MISC is defined as MC3_MISC in SDM.\r
+ MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.\r
+ @{\r
+**/\r
+#define MSR_P6_MC0_MISC 0x00000403\r
+#define MSR_P6_MC1_MISC 0x00000407\r
+#define MSR_P6_MC2_MISC 0x0000040B\r
+#define MSR_P6_MC3_MISC 0x00000413\r
+#define MSR_P6_MC4_MISC 0x0000040F\r
+/// @}\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Pentium(R) 4 Processors.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __PENTIUM_4_MSR_H__\r
+#define __PENTIUM_4_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Pentium(R) 4 Processors?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x0F \\r
+ )\r
+\r
+/**\r
+ 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range\r
+ Determination.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)\r
+ Enables and disables processor features; (R) indicates current processor\r
+ configuration.\r
+\r
+ @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state\r
+ /// output is enabled (1) or disabled (0) as set by the strapping of SMI#.\r
+ /// The value in this bit is written on the deassertion of RESET#; the bit\r
+ /// is set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 OutputTriStateEnabled:1;\r
+ ///\r
+ /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST\r
+ /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The\r
+ /// value in this bit is written on the deassertion of RESET#; the bit is\r
+ /// set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 ExecuteBIST:1;\r
+ ///\r
+ /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue\r
+ /// depth for the system bus is 1 (1) or up to 12 (0) as set by the\r
+ /// strapping of A7#. The value in this bit is written on the deassertion\r
+ /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 InOrderQueueDepth:1;\r
+ ///\r
+ /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#\r
+ /// observation is enabled (0) or disabled (1) as determined by the\r
+ /// strapping of A9#. The value in this bit is written on the deassertion\r
+ /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 MCERR_ObservationDisabled:1;\r
+ ///\r
+ /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#\r
+ /// observation is enabled (0) or disabled (1) as determined by the\r
+ /// strapping of A10#. The value in this bit is written on the deassertion\r
+ /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 BINIT_ObservationEnabled:1;\r
+ ///\r
+ /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID\r
+ /// value as set by the strapping of A12# and A11#. The logical cluster ID\r
+ /// value is written into the field on the deassertion of RESET#; the\r
+ /// field is set to 1 when the address bus signal is asserted.\r
+ ///\r
+ UINT32 APICClusterID:2;\r
+ ///\r
+ /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled\r
+ /// (0) or disabled (1) as set by the strapping of A15#. The value in this\r
+ /// bit is written on the deassertion of RESET#; the bit is set to 1 when\r
+ /// the address bus signal is asserted.\r
+ ///\r
+ UINT32 BusParkDisable:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set\r
+ /// by the strapping of BR[3:0]. The logical ID value is written into the\r
+ /// field on the deassertion of RESET#; the field is set to 1 when the\r
+ /// address bus signal is asserted.\r
+ ///\r
+ UINT32 AgentID:2;\r
+ UINT32 Reserved2:18;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)\r
+ Enables and disables processor features.\r
+\r
+ @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the\r
+ /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear\r
+ /// to disabled (0, default).\r
+ ///\r
+ UINT32 RCNT_SCNT:1;\r
+ ///\r
+ /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data\r
+ /// bus parity checking; clear to enable parity checking.\r
+ ///\r
+ UINT32 DataErrorCheckingDisable:1;\r
+ ///\r
+ /// [Bit 2] Response Error Checking Disable (R/W) Set to disable\r
+ /// (default); clear to enable.\r
+ ///\r
+ UINT32 ResponseErrorCheckingDisable:1;\r
+ ///\r
+ /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable\r
+ /// (default); clear to enable.\r
+ ///\r
+ UINT32 AddressRequestErrorCheckingDisable:1;\r
+ ///\r
+ /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving\r
+ /// for initiator bus requests (default); clear to enable.\r
+ ///\r
+ UINT32 InitiatorMCERR_Disable:1;\r
+ ///\r
+ /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving\r
+ /// for initiator internal errors (default); clear to enable.\r
+ ///\r
+ UINT32 InternalMCERR_Disable:1;\r
+ ///\r
+ /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver\r
+ /// (default); clear to enable driver.\r
+ ///\r
+ UINT32 BINIT_DriverDisable:1;\r
+ UINT32 Reserved1:25;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of\r
+ this MSR varies according to the MODEL value in the CPUID version\r
+ information. The following bit field layout applies to Pentium 4 and Xeon\r
+ Processors with MODEL encoding equal or greater than 2. (R) The field\r
+ Indicates the current processor frequency configuration.\r
+\r
+ @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable\r
+ /// bus speed: *EncodingScalable Bus Speed*\r
+ ///\r
+ /// 000B 100 MHz (Model 2).\r
+ /// 000B 266 MHz (Model 3 or 4)\r
+ /// 001B 133 MHz\r
+ /// 010B 200 MHz\r
+ /// 011B 166 MHz\r
+ /// 100B 333 MHz (Model 6)\r
+ ///\r
+ /// 133.33 MHz should be utilized if performing calculation with System\r
+ /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if\r
+ /// performing calculation with System Bus Speed when encoding is 011B.\r
+ /// 266.67 MHz should be utilized if performing calculation with System\r
+ /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33\r
+ /// MHz should be utilized if performing calculation with System Bus\r
+ /// Speed when encoding is 100B and model encoding = 6. All other values\r
+ /// are reserved.\r
+ ///\r
+ UINT32 ScalableBusSpeed:3;\r
+ UINT32 Reserved2:5;\r
+ ///\r
+ /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R)\r
+ /// The processor core clock frequency to system bus frequency ratio\r
+ /// observed at the de-assertion of the reset pin.\r
+ ///\r
+ UINT32 ClockRatio:8;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of\r
+ this MSR varies according to the MODEL value of the CPUID version\r
+ information. This bit field layout applies to Pentium 4 and Xeon Processors\r
+ with MODEL encoding less than 2. Indicates current processor frequency\r
+ configuration.\r
+\r
+ @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:21;\r
+ ///\r
+ /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable\r
+ /// bus speed: *Encoding* *Scalable Bus Speed*\r
+ ///\r
+ /// 000B 100 MHz All others values reserved.\r
+ ///\r
+ UINT32 ScalableBusSpeed:3;\r
+ UINT32 Reserved2:8;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RAX 0x00000180\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RBX 0x00000181\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RCX 0x00000182\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RDX 0x00000183\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RSI 0x00000184\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RDI 0x00000185\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RBP 0x00000186\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RSP 0x00000187\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section\r
+ 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
+ state at time of machine check error. When in non-64-bit modes at the time\r
+ of the error, bits 63-32 do not contain valid data.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_RIP 0x00000189\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,\r
+ "IA32_MCG Extended Machine Check State MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_MCG_MISC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_MISC 0x0000018A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] DS When set, the bit indicates that a page assist or page\r
+ /// fault occurred during DS normal operation. The processors response is\r
+ /// to shut down. The bit is used as an aid for debugging DS handling\r
+ /// code. It is the responsibility of the user (BIOS or operating system)\r
+ /// to clear this bit for normal operation.\r
+ ///\r
+ UINT32 DS:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_MCG_MISC_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R8 0x00000190\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,\r
+ "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the\r
+ associated state-save MSRs) exist only in Intel 64 processors. These\r
+ registers contain valid information only when the processor is operating in\r
+ 64-bit mode at the time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R9 0x00000191\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R10 0x00000192\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R11 0x00000193\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R12 0x00000194\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R13 0x00000195\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R14 0x00000196\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG\r
+ Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
+ state-save MSRs) exist only in Intel 64 processors. These registers contain\r
+ valid information only when the processor is operating in 64-bit mode at the\r
+ time of the error.\r
+\r
+ @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MCG_R15 0x00000197\r
+\r
+\r
+/**\r
+ Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:\r
+ When read, specifies the value of the target TM2 transition last written.\r
+ When set, it sets the next target value for TM2 transition. 4, 6. Shared.\r
+ For Family F, Model 4 and Model 6 processors: When read, specifies the value\r
+ of the target TM2 transition last written. Writes may cause #GP exceptions.\r
+\r
+ @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fast-Strings Enable. See Table 2-2.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.\r
+ ///\r
+ UINT32 FPU:1;\r
+ ///\r
+ /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal\r
+ /// Monitor," and see Table 2-2.\r
+ ///\r
+ UINT32 TM1:1;\r
+ ///\r
+ /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception\r
+ /// to be issued instead of a split-lock cycle. Operating systems that set\r
+ /// this bit must align system structures to avoid split-lock scenarios.\r
+ /// When the bit is clear (default), normal split-locks are issued to the\r
+ /// bus.\r
+ /// This debug feature is specific to the Pentium 4 processor.\r
+ ///\r
+ UINT32 SplitLockDisable:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level\r
+ /// cache is disabled; when clear (default) the third-level cache is\r
+ /// enabled. This flag is reserved for processors that do not have a\r
+ /// third-level cache. Note that the bit controls only the third-level\r
+ /// cache; and only if overall caching is enabled through the CD flag of\r
+ /// control register CR0, the page-level cache controls, and/or the MTRRs.\r
+ /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".\r
+ ///\r
+ UINT32 ThirdLevelCacheDisable:1;\r
+ ///\r
+ /// [Bit 7] Performance Monitoring Available (R) See Table 2-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ ///\r
+ /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is\r
+ /// suppressed during a Split Lock access. When clear (default), LOCK is\r
+ /// not suppressed.\r
+ ///\r
+ UINT32 SuppressLockEnable:1;\r
+ ///\r
+ /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.\r
+ /// When clear (default), enables the prefetch queue.\r
+ ///\r
+ UINT32 PrefetchQueueDisable:1;\r
+ ///\r
+ /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt\r
+ /// reporting through the FERR# pin is enabled; when clear, this interrupt\r
+ /// reporting function is disabled.\r
+ /// When this flag is set and the processor is in the stop-clock state\r
+ /// (STPCLK# is asserted), asserting the FERR# pin signals to the\r
+ /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,\r
+ /// SMI#, or RESET#) is pending and that the processor should return to\r
+ /// normal operation to handle the interrupt. This flag does not affect\r
+ /// the normal operation of the FERR# pin (to indicate an unmasked\r
+ /// floatingpoint error) when the STPCLK# pin is not asserted.\r
+ ///\r
+ UINT32 FERR:1;\r
+ ///\r
+ /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See\r
+ /// Table 2-2. When set, the processor does not support branch trace\r
+ /// storage (BTS); when clear, BTS is supported.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable\r
+ /// (R) See Table 2-2. When set, the processor does not support processor\r
+ /// event-based sampling (PEBS); when clear, PEBS is supported.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ ///\r
+ /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal\r
+ /// sensor indicates that the die temperature is at the predetermined\r
+ /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce\r
+ /// the bus to core ratio and voltage according to the value last written\r
+ /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the\r
+ /// processor does not change the VID signals or the bus to core ratio\r
+ /// when the processor enters a thermal managed state. If the TM2 feature\r
+ /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then\r
+ /// this feature is not supported and BIOS must not alter the contents of\r
+ /// this bit location. The processor is operating out of spec if both this\r
+ /// bit and the TM1 bit are set to disabled states.\r
+ ///\r
+ UINT32 TM2:1;\r
+ UINT32 Reserved3:4;\r
+ ///\r
+ /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ ///\r
+ /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1,\r
+ /// the processor fetches the cache line of the 128-byte sector containing\r
+ /// currently required data. When set to 0, the processor fetches both\r
+ /// cache lines in the sector.\r
+ /// Single processor platforms should not set this bit. Server platforms\r
+ /// should set or clear this bit based on platform performance observed\r
+ /// in validation and testing. BIOS may contain a setup option that\r
+ /// controls the setting of this bit.\r
+ ///\r
+ UINT32 AdjacentCacheLinePrefetchDisable:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this\r
+ /// can cause unexpected behavior to software that depends on the\r
+ /// availability of CPUID leaves greater than 3.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ ///\r
+ /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache\r
+ /// is placed in shared mode; when clear (default), the cache is placed in\r
+ /// adaptive mode. This bit is only enabled for IA-32 processors that\r
+ /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data\r
+ /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are\r
+ /// identical, data in L1 is shared across logical processors. Otherwise,\r
+ /// L1 is not shared and cache use is competitive. If the Context ID\r
+ /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1,\r
+ /// the ability to switch modes is not supported. BIOS must not alter the\r
+ /// contents of IA32_MISC_ENABLE[24].\r
+ ///\r
+ UINT32 L1DataCacheContextMode:1;\r
+ UINT32 Reserved5:7;\r
+ UINT32 Reserved6:2;\r
+ ///\r
+ /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved7:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ 3, 4, 6. Shared. Platform Feature Requirements (R).\r
+\r
+ @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:18;\r
+ ///\r
+ /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor\r
+ /// has specific platform requirements. The details of the platform\r
+ /// requirements are listed in the respective data sheets of the processor.\r
+ ///\r
+ UINT32 PLATFORM:1;\r
+ UINT32 Reserved2:13;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains\r
+ a pointer to the last branch instruction that the processor executed prior\r
+ to the last exception that was generated or the last interrupt that was\r
+ handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear\r
+ IP Linear address of the last branch instruction (If IA-32e mode is active).\r
+ From Linear IP Linear address of the last branch instruction. Reserved.\r
+\r
+ @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area\r
+ contains a pointer to the target of the last branch instruction that the\r
+ processor executed prior to the last exception that was generated or the\r
+ last interrupt that was handled. See Section 17.13.3, "Last Exception\r
+ Records.". Unique. From Linear IP Linear address of the target of the last\r
+ branch instruction (If IA-32e mode is active). From Linear IP Linear address\r
+ of the target of the last branch instruction. Reserved.\r
+\r
+ @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug\r
+ features are used. Bit definitions are discussed in the referenced section.\r
+ See Section 17.13.1, "MSR_DEBUGCTLA MSR.".\r
+\r
+ @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an\r
+ index (0-3 or 0-15) that points to the top of the last branch record stack\r
+ (that is, that points the index of the MSR containing the most recent branch\r
+ record). See Section 17.13.2, "LBR Stack for Processors Based on Intel\r
+ NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.\r
+\r
+ @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA\r
+\r
+\r
+/**\r
+ 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record\r
+ registers on the last branch record stack. It contains pointers to the\r
+ source and destination instruction for one of the last four branches,\r
+ exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through\r
+ MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models\r
+ 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See\r
+ Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
+ for Processors based on Skylake Microarchitecture.".\r
+\r
+ @param ECX MSR_PENTIUM_4_LASTBRANCH_n\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB\r
+#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC\r
+#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD\r
+#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BPU_COUNTERn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM.\r
+ MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM.\r
+ MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM.\r
+ MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300\r
+#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301\r
+#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302\r
+#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MS_COUNTERn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM.\r
+ MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM.\r
+ MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM.\r
+ MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304\r
+#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305\r
+#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306\r
+#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM.\r
+ MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM.\r
+ MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM.\r
+ MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308\r
+#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309\r
+#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A\r
+#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IQ_COUNTERn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM.\r
+ MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM.\r
+ MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM.\r
+ MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM.\r
+ MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM.\r
+ MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C\r
+#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D\r
+#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E\r
+#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F\r
+#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310\r
+#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BPU_CCCRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM.\r
+ MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM.\r
+ MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM.\r
+ MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360\r
+#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361\r
+#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362\r
+#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MS_CCCRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM.\r
+ MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM.\r
+ MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM.\r
+ MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_MS_CCCR0 0x00000364\r
+#define MSR_PENTIUM_4_MS_CCCR1 0x00000365\r
+#define MSR_PENTIUM_4_MS_CCCR2 0x00000366\r
+#define MSR_PENTIUM_4_MS_CCCR3 0x00000367\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FLAME_CCCRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM.\r
+ MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM.\r
+ MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM.\r
+ MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368\r
+#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369\r
+#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A\r
+#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IQ_CCCRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM.\r
+ MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM.\r
+ MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM.\r
+ MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM.\r
+ MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM.\r
+ MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C\r
+#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D\r
+#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E\r
+#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F\r
+#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370\r
+#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9\r
+\r
+\r
+/**\r
+ 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r
+ available on later processors. It is only available on processor family 0FH,\r
+ models 01H-02H.\r
+\r
+ @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA\r
+\r
+\r
+/**\r
+ 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r
+ available on later processors. It is only available on processor family 0FH,\r
+ models 01H-02H.\r
+\r
+ @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_ALF_ESCRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM.\r
+ MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM.\r
+ MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM.\r
+ MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM.\r
+ MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM.\r
+ MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA\r
+#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB\r
+#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC\r
+#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD\r
+#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0\r
+#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1\r
+/// @}\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)\r
+ Controls the enabling of processor event sampling and replay tagging.\r
+\r
+ @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 12:0] See Table 19-36.\r
+ ///\r
+ UINT32 EventNum:13;\r
+ UINT32 Reserved1:11;\r
+ ///\r
+ /// [Bit 24] UOP Tag Enables replay tagging when set.\r
+ ///\r
+ UINT32 UOP:1;\r
+ ///\r
+ /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical\r
+ /// processor when set; disables PEBS when clear (default). See Section\r
+ /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
+ /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors\r
+ /// that do not support Intel HyperThreading Technology.\r
+ ///\r
+ UINT32 ENABLE_PEBS_MY_THR:1;\r
+ ///\r
+ /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical\r
+ /// processor when set; disables PEBS when clear (default). See Section\r
+ /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
+ /// logical processor. This bit is reserved for IA-32 processors that do\r
+ /// not support Intel Hyper-Threading Technology.\r
+ ///\r
+ UINT32 ENABLE_PEBS_OTH_THR:1;\r
+ UINT32 Reserved2:5;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ 0, 1, 2, 3, 4, 6. Shared. See Table 19-36.\r
+\r
+ @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2\r
+\r
+\r
+/**\r
+ 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
+ record registers on the last branch record stack (680H-68FH). This part of\r
+ the stack contains pointers to the source instruction for one of the last 16\r
+ branches, exceptions, or interrupts taken by the processor. The MSRs at\r
+ 680H-68FH, 6C0H-6CfH are not available in processor releases before family\r
+ 0FH, model 03H. These MSRs replace MSRs previously located at\r
+ 1DBH-1DEH.which performed the same function for early releases. See Section\r
+ 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for\r
+ Processors based on Skylake Microarchitecture.".\r
+\r
+ @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F\r
+/// @}\r
+\r
+\r
+/**\r
+ 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
+ record registers on the last branch record stack (6C0H-6CFH). This part of\r
+ the stack contains pointers to the destination instruction for one of the\r
+ last 16 branches, exceptions, or interrupts that the processor took. See\r
+ Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
+ for Processors based on Skylake Microarchitecture.".\r
+\r
+ @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
+ MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF\r
+/// @}\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section\r
+ 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
+ 8-MByte L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section\r
+ 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
+ 8-MByte L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF\r
+\r
+\r
+/**\r
+ 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section\r
+ 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
+ 8-MByte L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0\r
+\r
+\r
+/**\r
+ 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,\r
+ "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte\r
+ L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2\r
+\r
+\r
+/**\r
+ 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,\r
+ "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte\r
+ L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3\r
+\r
+\r
+/**\r
+ 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section\r
+ 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
+ 8MByte L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC\r
+\r
+\r
+/**\r
+ 6. Shared. GBUSQ Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD\r
+\r
+\r
+/**\r
+ 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section\r
+ 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
+ 8MByte L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE\r
+\r
+\r
+/**\r
+ 6. Shared. GSNPQ Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF\r
+\r
+\r
+/**\r
+ 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,\r
+ "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte\r
+ L3 Cache.".\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0\r
+\r
+\r
+/**\r
+ 6. Shared. FSB Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1\r
+\r
+\r
+/**\r
+ 6. Shared. FSB Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2\r
+\r
+\r
+/**\r
+ 6. Shared. FSB Event Control and Counter Register (R/W).\r
+\r
+ @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);\r
+ AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r
+**/\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Pentium M Processors.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __PENTIUM_M_MSR_H__\r
+#define __PENTIUM_M_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Pentium M Processors?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x0D \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ See Section 2.22, "MSRs in Pentium Processors.".\r
+\r
+ @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000\r
+\r
+\r
+/**\r
+ See Section 2.22, "MSRs in Pentium Processors.".\r
+\r
+ @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001\r
+\r
+\r
+/**\r
+ Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
+ features. (R) Indicates current processor configuration.\r
+\r
+ @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the\r
+ /// Pentium M processor.\r
+ ///\r
+ UINT32 DataErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on\r
+ /// the Pentium M processor.\r
+ ///\r
+ UINT32 ResponseErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium\r
+ /// M processor.\r
+ ///\r
+ UINT32 MCERR_DriveEnable:1;\r
+ ///\r
+ /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium\r
+ /// M processor.\r
+ ///\r
+ UINT32 AddressParityEnable:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on\r
+ /// the Pentium M processor.\r
+ ///\r
+ UINT32 BINIT_DriverEnable:1;\r
+ ///\r
+ /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 OutputTriStateEnable:1;\r
+ ///\r
+ /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 ExecuteBIST:1;\r
+ ///\r
+ /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
+ /// Always 0 on the Pentium M processor.\r
+ ///\r
+ UINT32 MCERR_ObservationEnabled:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
+ /// Always 0 on the Pentium M processor.\r
+ ///\r
+ UINT32 BINIT_ObservationEnabled:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes\r
+ /// Always 0 on the Pentium M processor.\r
+ ///\r
+ UINT32 ResetVector:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M\r
+ /// processor.\r
+ ///\r
+ UINT32 APICClusterID:2;\r
+ ///\r
+ /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always\r
+ /// 0 on the Pentium M processor.\r
+ ///\r
+ UINT32 SystemBusFrequency:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium\r
+ /// M processor.\r
+ ///\r
+ UINT32 SymmetricArbitrationID:2;\r
+ ///\r
+ /// [Bits 26:22] Clock Frequency Ratio (R/O).\r
+ ///\r
+ UINT32 ClockFrequencyRatio:5;\r
+ UINT32 Reserved7:5;\r
+ UINT32 Reserved8:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ Last Branch Record n (R/W) One of 8 last branch record registers on the last\r
+ branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold\r
+ the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section\r
+ 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
+ Processors)".\r
+\r
+ @param ECX MSR_PENTIUM_M_LASTBRANCH_n\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
+ MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040\r
+#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041\r
+#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042\r
+#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043\r
+#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044\r
+#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045\r
+#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046\r
+#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047\r
+/// @}\r
+\r
+\r
+/**\r
+ Reserved.\r
+\r
+ @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
+ /// Indicates if the L2 is hardware-disabled.\r
+ ///\r
+ UINT32 L2HardwareEnabled:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the\r
+ /// cache data bus. ECC is always generated on write cycles. 1. = Disabled\r
+ /// (default) 2. = Enabled For the Pentium M processor, ECC checking on\r
+ /// the cache data bus is always enabled.\r
+ ///\r
+ UINT32 ECCCheckEnable:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
+ /// Disabled (default) Until this bit is set the processor will not\r
+ /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
+ ///\r
+ UINT32 L2Enabled:1;\r
+ UINT32 Reserved3:14;\r
+ ///\r
+ /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
+ ///\r
+ UINT32 L2NotPresent:1;\r
+ UINT32 Reserved4:8;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;\r
+\r
+\r
+/**\r
+\r
+\r
+ @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
+ /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
+ /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
+ /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
+ /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
+ ///\r
+ UINT32 TM_SELECT:1;\r
+ UINT32 Reserved2:15;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_M_THERM2_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
+ /// this bit enables the thermal control circuit (TCC) portion of the\r
+ /// Intel Thermal Monitor feature. This allows processor clocks to be\r
+ /// automatically modulated based on the processor's thermal sensor\r
+ /// operation. 0 = Disabled (default). The automatic thermal control\r
+ /// circuit enable bit determines if the thermal control circuit (TCC)\r
+ /// will be activated when the processor's internal thermal sensor\r
+ /// determines the processor is about to exceed its maximum operating\r
+ /// temperature. When the TCC is activated and TM1 is enabled, the\r
+ /// processors clocks will be forced to a 50% duty cycle. BIOS must enable\r
+ /// this feature. The bit should not be confused with the on-demand\r
+ /// thermal control circuit enable bit.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
+ /// monitoring enabled 0 = Performance monitoring disabled.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the\r
+ /// processor to indicate a pending break event within the processor 0 =\r
+ /// Indicates compatible FERR# signaling behavior This bit must be set to\r
+ /// 1 to support XAPIC interrupt model usage.\r
+ /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't\r
+ /// support branch trace storage (BTS) 0 = BTS is supported\r
+ ///\r
+ UINT32 FERR:1;\r
+ ///\r
+ /// [Bit 11] Branch Trace Storage Unavailable (RO)\r
+ /// 1 = Processor doesn't support branch trace storage (BTS)\r
+ /// 0 = BTS is supported\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =\r
+ /// Processor does not support processor event based sampling (PEBS); 0 =\r
+ /// PEBS is supported. The Pentium M processor does not support PEBS.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved5:3;\r
+ ///\r
+ /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
+ /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M\r
+ /// processor, this bit may be configured to be read-only.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved6:6;\r
+ ///\r
+ /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
+ /// disabled. xTPR messages are optional messages that allow the processor\r
+ /// to inform the chipset of its priority. The default is processor\r
+ /// specific.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved7:8;\r
+ UINT32 Reserved8:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points\r
+ to the MSR containing the most recent branch record. See also: -\r
+ MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,\r
+ and Exception Recording (Pentium M Processors)".\r
+\r
+ @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Debug Control (R/W) Controls how several debug features are used. Bit\r
+ definitions are discussed in the referenced section. See Section 17.15,\r
+ "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".\r
+\r
+ @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9\r
+\r
+\r
+/**\r
+ Last Exception Record To Linear IP (R) This area contains a pointer to the\r
+ target of the last branch instruction that the processor executed prior to\r
+ the last exception that was generated or the last interrupt that was\r
+ handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording\r
+ (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception\r
+ MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Last Exception Record From Linear IP (R) Contains a pointer to the last\r
+ branch instruction that the processor executed prior to the last exception\r
+ that was generated or the last interrupt that was handled. See Section\r
+ 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
+ Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE\r
+\r
+\r
+/**\r
+ See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_MC4_CTL 0x0000040C\r
+\r
+\r
+/**\r
+ See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
+\r
+ @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D\r
+\r
+\r
+/**\r
+ See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is\r
+ either not implemented or contains no address if the ADDRV flag in the\r
+ MSR_MC4_STATUS register is clear. When not implemented in the processor, all\r
+ reads and writes to this MSR will cause a general-protection exception.\r
+\r
+ @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E\r
+\r
+\r
+/**\r
+ See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
+\r
+ @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_MC3_CTL 0x00000410\r
+\r
+\r
+/**\r
+ See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
+\r
+ @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_MC3_STATUS 0x00000411\r
+\r
+\r
+/**\r
+ See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is\r
+ either not implemented or contains no address if the ADDRV flag in the\r
+ MSR_MC3_STATUS register is clear. When not implemented in the processor, all\r
+ reads and writes to this MSR will cause a general-protection exception.\r
+\r
+ @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);\r
+ AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
+**/\r
+#define MSR_PENTIUM_M_MC3_ADDR 0x00000412\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Pentium Processors.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __PENTIUM_MSR_H__\r
+#define __PENTIUM_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Pentium Processors?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x05 && \\r
+ ( \\r
+ DisplayModel == 0x01 || \\r
+ DisplayModel == 0x02 || \\r
+ DisplayModel == 0x04 \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r
+\r
+ @param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);\r
+ AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
+**/\r
+#define MSR_PENTIUM_P5_MC_ADDR 0x00000000\r
+\r
+\r
+/**\r
+ See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r
+\r
+ @param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);\r
+ AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
+**/\r
+#define MSR_PENTIUM_P5_MC_TYPE 0x00000001\r
+\r
+\r
+/**\r
+ See Section 17.17, "Time-Stamp Counter.".\r
+\r
+ @param ECX MSR_PENTIUM_TSC (0x00000010)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);\r
+ AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_TSC is defined as TSC in SDM.\r
+**/\r
+#define MSR_PENTIUM_TSC 0x00000010\r
+\r
+\r
+/**\r
+ See Section 18.6.9.1, "Control and Event Select Register (CESR).".\r
+\r
+ @param ECX MSR_PENTIUM_CESR (0x00000011)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);\r
+ AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_CESR is defined as CESR in SDM.\r
+**/\r
+#define MSR_PENTIUM_CESR 0x00000011\r
+\r
+\r
+/**\r
+ Section 18.6.9.3, "Events Counted.".\r
+\r
+ @param ECX MSR_PENTIUM_CTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);\r
+ AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.\r
+ MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.\r
+ @{\r
+**/\r
+#define MSR_PENTIUM_CTR0 0x00000012\r
+#define MSR_PENTIUM_CTR1 0x00000013\r
+/// @}\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __SANDY_BRIDGE_MSR_H__\r
+#define __SANDY_BRIDGE_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel processors based on the Sandy Bridge microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x2A || \\r
+ DisplayModel == 0x2D \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Thread. SMI Counter (R/O).\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] SMI Count (R/O) Count SMIs.\r
+ ///\r
+ UINT32 SMICount:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Platform Information Contains power management and other model\r
+ specific features enumeration. See http://biosbits.org.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
+ /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
+ /// MHz.\r
+ ///\r
+ UINT32 MaximumNonTurboRatio:8;\r
+ UINT32 Reserved2:12;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
+ /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
+ /// Turbo mode is disabled.\r
+ ///\r
+ UINT32 RatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
+ /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
+ /// programmable.\r
+ ///\r
+ UINT32 TDPLimit:1;\r
+ UINT32 Reserved3:2;\r
+ UINT32 Reserved4:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
+ /// minimum ratio (maximum efficiency) that the processor can operates, in\r
+ /// units of 100MHz.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 Reserved5:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are\r
+ processor specific C-state code names, unrelated to MWAIT extension C-state\r
+ parameters or ACPI CStates. See http://biosbits.org.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power). for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r
+ /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
+ /// This field cannot be used to limit package C-state to C3.\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
+ /// IO_read instructions sent to IO register specified by\r
+ /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
+ /// until next reset.\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:9;\r
+ ///\r
+ /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
+ /// will conditionally demote C6/C7 requests to C3 based on uncore\r
+ /// auto-demote information.\r
+ ///\r
+ UINT32 C3AutoDemotion:1;\r
+ ///\r
+ /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
+ /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
+ /// auto-demote information.\r
+ ///\r
+ UINT32 C1AutoDemotion:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
+ /// demoted C3.\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
+ /// demoted C1.\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ UINT32 Reserved4:3;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Power Management IO Redirection in C-state (R/W) See\r
+ http://biosbits.org.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
+ /// visible to software for IO redirection. If IO MWAIT Redirection is\r
+ /// enabled, reads to this address will be consumed by the power\r
+ /// management logic and decoded to MWAIT instructions. When IO port\r
+ /// address redirection is enabled, this is the IO port address reported\r
+ /// to the OS/software.\r
+ ///\r
+ UINT32 Lvl2Base:16;\r
+ ///\r
+ /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
+ /// maximum C-State code name to be included when IO read to MWAIT\r
+ /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r
+ /// is the max C-State to include 001b - C6 is the max C-State to include\r
+ /// 010b - C7 is the max C-State to include.\r
+ ///\r
+ UINT32 CStateRange:3;\r
+ UINT32 Reserved1:13;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+ handler to handle unsuccessful read of this MSR.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
+ /// MSR, the configuration of AES instruction set availability is as\r
+ /// follows: 11b: AES instructions are not available until next RESET.\r
+ /// otherwise, AES instructions are available. Note, AES instruction set\r
+ /// is not available if read is unsuccessful. If the configuration is not\r
+ /// 01b, AES instruction can be mis-configured if a privileged agent\r
+ /// unintentionally writes 11b.\r
+ ///\r
+ UINT32 AESConfiguration:2;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.\r
+ MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.\r
+ MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.\r
+ MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D\r
+/// @}\r
+\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ ///\r
+ /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed\r
+ /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).\r
+ ///\r
+ UINT32 CoreVoltage:16;\r
+ UINT32 Reserved2:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was\r
+ originally named IA32_THERM_CONTROL MSR.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%\r
+ /// increment.\r
+ ///\r
+ UINT32 OnDemandClockModulationDutyCycle:4;\r
+ ///\r
+ /// [Bit 4] On demand Clock Modulation Enable (R/W).\r
+ ///\r
+ UINT32 OnDemandClockModulationEnable:1;\r
+ UINT32 Reserved1:27;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER;\r
+\r
+\r
+/**\r
+ Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:6;\r
+ ///\r
+ /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ UINT32 Reserved5:3;\r
+ ///\r
+ /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved6:8;\r
+ UINT32 Reserved7:2;\r
+ ///\r
+ /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved8:3;\r
+ ///\r
+ /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
+ /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
+ /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
+ /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
+ /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
+ /// the power-on default value is used by BIOS to detect hardware support\r
+ /// of turbo mode. If power-on default value is 1, turbo mode is available\r
+ /// in the processor. If power-on default value is 0, turbo mode is not\r
+ /// available.\r
+ ///\r
+ UINT32 TurboModeDisable:1;\r
+ UINT32 Reserved9:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
+ /// PROCHOT# will be asserted. The value is degree C.\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ UINT32 Reserved2:8;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
+\r
+\r
+/**\r
+ Miscellaneous Feature Control (R/W).\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L2 hardware prefetcher, which fetches additional lines of code or data\r
+ /// into the L2 cache.\r
+ ///\r
+ UINT32 L2HardwarePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
+ /// disables the adjacent cache line prefetcher, which fetches the cache\r
+ /// line that comprises a cache line pair (128 bytes).\r
+ ///\r
+ UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
+ /// the L1 data cache prefetcher, which fetches the next cache line into\r
+ /// L1 data cache.\r
+ ///\r
+ UINT32 DCUHardwarePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
+ /// data cache IP prefetcher, which uses sequential load history (based on\r
+ /// instruction Pointer of previous loads) to determine whether to\r
+ /// prefetch additional lines.\r
+ ///\r
+ UINT32 DCUIPPrefetcherDisable:1;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6\r
+\r
+\r
+/**\r
+ Thread. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7\r
+\r
+\r
+/**\r
+ See http://biosbits.org.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record Filtering Select Register (R/W) See Section\r
+ 17.9.2, "Filtering of Last Branch Records.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] CPL_EQ_0.\r
+ ///\r
+ UINT32 CPL_EQ_0:1;\r
+ ///\r
+ /// [Bit 1] CPL_NEQ_0.\r
+ ///\r
+ UINT32 CPL_NEQ_0:1;\r
+ ///\r
+ /// [Bit 2] JCC.\r
+ ///\r
+ UINT32 JCC:1;\r
+ ///\r
+ /// [Bit 3] NEAR_REL_CALL.\r
+ ///\r
+ UINT32 NEAR_REL_CALL:1;\r
+ ///\r
+ /// [Bit 4] NEAR_IND_CALL.\r
+ ///\r
+ UINT32 NEAR_IND_CALL:1;\r
+ ///\r
+ /// [Bit 5] NEAR_RET.\r
+ ///\r
+ UINT32 NEAR_RET:1;\r
+ ///\r
+ /// [Bit 6] NEAR_IND_JMP.\r
+ ///\r
+ UINT32 NEAR_IND_JMP:1;\r
+ ///\r
+ /// [Bit 7] NEAR_REL_JMP.\r
+ ///\r
+ UINT32 NEAR_REL_JMP:1;\r
+ ///\r
+ /// [Bit 8] FAR_BRANCH.\r
+ ///\r
+ UINT32 FAR_BRANCH:1;\r
+ UINT32 Reserved1:23;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
+ that points to the MSR containing the most recent branch record. See\r
+ MSR_LASTBRANCH_0_FROM_IP (at 680H).\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
+ last branch instruction that the processor executed prior to the last\r
+ exception that was generated or the last interrupt that was handled.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
+ to the target of the last branch instruction that the processor executed\r
+ prior to the last exception that was generated or the last interrupt that\r
+ was handled.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE\r
+\r
+\r
+/**\r
+ Core. See http://biosbits.org.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC\r
+\r
+\r
+/**\r
+ Package. Always 0 (CMCI not supported).\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284\r
+\r
+\r
+/**\r
+ See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Thread. Ovf_PMC0.\r
+ ///\r
+ UINT32 Ovf_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Thread. Ovf_PMC1.\r
+ ///\r
+ UINT32 Ovf_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Thread. Ovf_PMC2.\r
+ ///\r
+ UINT32 Ovf_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Thread. Ovf_PMC3.\r
+ ///\r
+ UINT32 Ovf_PMC3:1;\r
+ ///\r
+ /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
+ ///\r
+ UINT32 Ovf_PMC4:1;\r
+ ///\r
+ /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
+ ///\r
+ UINT32 Ovf_PMC5:1;\r
+ ///\r
+ /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
+ ///\r
+ UINT32 Ovf_PMC6:1;\r
+ ///\r
+ /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
+ ///\r
+ UINT32 Ovf_PMC7:1;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bit 32] Thread. Ovf_FixedCtr0.\r
+ ///\r
+ UINT32 Ovf_FixedCtr0:1;\r
+ ///\r
+ /// [Bit 33] Thread. Ovf_FixedCtr1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr1:1;\r
+ ///\r
+ /// [Bit 34] Thread. Ovf_FixedCtr2.\r
+ ///\r
+ UINT32 Ovf_FixedCtr2:1;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 61] Thread. Ovf_Uncore.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Thread. Ovf_BufDSSAVE.\r
+ ///\r
+ UINT32 Ovf_BufDSSAVE:1;\r
+ ///\r
+ /// [Bit 63] Thread. CondChgd.\r
+ ///\r
+ UINT32 CondChgd:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
+ Facilities.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Thread. Set 1 to enable PMC0 to count.\r
+ ///\r
+ UINT32 PCM0_EN:1;\r
+ ///\r
+ /// [Bit 1] Thread. Set 1 to enable PMC1 to count.\r
+ ///\r
+ UINT32 PCM1_EN:1;\r
+ ///\r
+ /// [Bit 2] Thread. Set 1 to enable PMC2 to count.\r
+ ///\r
+ UINT32 PCM2_EN:1;\r
+ ///\r
+ /// [Bit 3] Thread. Set 1 to enable PMC3 to count.\r
+ ///\r
+ UINT32 PCM3_EN:1;\r
+ ///\r
+ /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >\r
+ /// 4).\r
+ ///\r
+ UINT32 PCM4_EN:1;\r
+ ///\r
+ /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >\r
+ /// 5).\r
+ ///\r
+ UINT32 PCM5_EN:1;\r
+ ///\r
+ /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >\r
+ /// 6).\r
+ ///\r
+ UINT32 PCM6_EN:1;\r
+ ///\r
+ /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >\r
+ /// 7).\r
+ ///\r
+ UINT32 PCM7_EN:1;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.\r
+ ///\r
+ UINT32 FIXED_CTR0:1;\r
+ ///\r
+ /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.\r
+ ///\r
+ UINT32 FIXED_CTR1:1;\r
+ ///\r
+ /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.\r
+ ///\r
+ UINT32 FIXED_CTR2:1;\r
+ UINT32 Reserved2:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
+ ///\r
+ UINT32 Ovf_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
+ ///\r
+ UINT32 Ovf_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
+ ///\r
+ UINT32 Ovf_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
+ ///\r
+ UINT32 Ovf_PMC3:1;\r
+ ///\r
+ /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
+ ///\r
+ UINT32 Ovf_PMC4:1;\r
+ ///\r
+ /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
+ ///\r
+ UINT32 Ovf_PMC5:1;\r
+ ///\r
+ /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
+ ///\r
+ UINT32 Ovf_PMC6:1;\r
+ ///\r
+ /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
+ ///\r
+ UINT32 Ovf_PMC7:1;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
+ ///\r
+ UINT32 Ovf_FixedCtr0:1;\r
+ ///\r
+ /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr1:1;\r
+ ///\r
+ /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
+ ///\r
+ UINT32 Ovf_FixedCtr2:1;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
+ ///\r
+ UINT32 Ovf_BufDSSAVE:1;\r
+ ///\r
+ /// [Bit 63] Thread. Set 1 to clear CondChgd.\r
+ ///\r
+ UINT32 CondChgd:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
+ ///\r
+ UINT32 PEBS_EN_PMC3:1;\r
+ UINT32 Reserved1:28;\r
+ ///\r
+ /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC0:1;\r
+ ///\r
+ /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC1:1;\r
+ ///\r
+ /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC2:1;\r
+ ///\r
+ /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
+ ///\r
+ UINT32 LL_EN_PMC3:1;\r
+ UINT32 Reserved2:27;\r
+ ///\r
+ /// [Bit 63] Enable Precise Store. (R/W).\r
+ ///\r
+ UINT32 PS_EN:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r
+ Facility.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
+ /// that will be counted. (R/W).\r
+ ///\r
+ UINT32 MinimumThreshold:16;\r
+ UINT32 Reserved1:16;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C3 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C6 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C7 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
+ Residency Counter. (R/O) Value since last reset that this core is in\r
+ processor-specific C3 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
+ Residency Counter. (R/O) Value since last reset that this core is in\r
+ processor-specific C6 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7\r
+ Residency Counter. (R/O) Value since last reset that this core is in\r
+ processor-specific C7 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE\r
+\r
+\r
+/**\r
+ Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU\r
+ /// hardware detected errors.\r
+ ///\r
+ UINT32 PCUHardwareError:1;\r
+ ///\r
+ /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU\r
+ /// controller detected errors.\r
+ ///\r
+ UINT32 PCUControllerError:1;\r
+ ///\r
+ /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU\r
+ /// firmware detected errors.\r
+ ///\r
+ UINT32 PCUFirmwareError:1;\r
+ UINT32 Reserved1:29;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
+ "RAPL Interfaces.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606\r
+\r
+\r
+/**\r
+ Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r
+ processor specific C-state code names, unrelated to MWAIT extension C-state\r
+ parameters or ACPI CStates.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
+ /// that should be used to decide if the package should be put into a\r
+ /// package C3 state.\r
+ ///\r
+ UINT32 TimeLimit:10;\r
+ ///\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
+ /// unit of the interrupt response time limit. The following time unit\r
+ /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
+ /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
+ ///\r
+ UINT32 TimeUnit:3;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
+ /// valid and can be used by the processor for package C-sate management.\r
+ ///\r
+ UINT32 Valid:1;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the\r
+ budget allocated for the package to exit from C6 to a C0 state, where\r
+ interrupt request can be delivered to the core and serviced. Additional\r
+ core-exit latency amy be applicable depending on the actual C-state the core\r
+ is in. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
+ /// that should be used to decide if the package should be put into a\r
+ /// package C6 state.\r
+ ///\r
+ UINT32 TimeLimit:10;\r
+ ///\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
+ /// unit of the interrupt response time limit. The following time unit\r
+ /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
+ /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
+ ///\r
+ UINT32 TimeUnit:3;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
+ /// valid and can be used by the processor for package C-sate management.\r
+ ///\r
+ UINT32 Valid:1;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C2 states. Count at the same frequency as the TSC.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610\r
+\r
+\r
+/**\r
+ Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614\r
+\r
+\r
+/**\r
+ Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
+ RAPL Domains.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638\r
+\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
+ branch record registers on the last branch record stack. This part of the\r
+ stack contains pointers to the source instruction. See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section\r
+ 17.4.8.1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F\r
+/// @}\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
+ record registers on the last branch record stack. This part of the stack\r
+ contains pointers to the destination instruction.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
+ MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
+ /// limit of 5 core active.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
+ /// limit of 6 core active.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
+ /// limit of 7 core active.\r
+ ///\r
+ UINT32 Maximum7C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
+ /// limit of 8 core active.\r
+ ///\r
+ UINT32 Maximum8C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore PMU global control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Slice 0 select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice0:1;\r
+ ///\r
+ /// [Bit 1] Slice 1 select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice1:1;\r
+ ///\r
+ /// [Bit 2] Slice 2 select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice2:1;\r
+ ///\r
+ /// [Bit 3] Slice 3 select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice3:1;\r
+ ///\r
+ /// [Bit 4] Slice 4 select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice4:1;\r
+ UINT32 Reserved1:14;\r
+ UINT32 Reserved2:10;\r
+ ///\r
+ /// [Bit 29] Enable all uncore counters.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bit 30] Enable wake on PMI.\r
+ ///\r
+ UINT32 WakePMI:1;\r
+ ///\r
+ /// [Bit 31] Enable Freezing counter when overflow.\r
+ ///\r
+ UINT32 FREEZE:1;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore PMU main status.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fixed counter overflowed.\r
+ ///\r
+ UINT32 Fixed:1;\r
+ ///\r
+ /// [Bit 1] An ARB counter overflowed.\r
+ ///\r
+ UINT32 ARB:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 3] A CBox counter overflowed (on any slice).\r
+ ///\r
+ UINT32 CBox:1;\r
+ UINT32 Reserved2:28;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore fixed counter control (R/W).\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:20;\r
+ ///\r
+ /// [Bit 20] Enable overflow propagation.\r
+ ///\r
+ UINT32 EnableOverflow:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 22] Enable counting.\r
+ ///\r
+ UINT32 EnableCounting:1;\r
+ UINT32 Reserved3:9;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore fixed counter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Current count.\r
+ ///\r
+ UINT32 CurrentCount:32;\r
+ ///\r
+ /// [Bits 47:32] Current count.\r
+ ///\r
+ UINT32 CurrentCountHi:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box configuration information (R/O).\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Report the number of C-Box units with performance counters,\r
+ /// including processor cores and processor graphics".\r
+ ///\r
+ UINT32 CBox:4;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, performance counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, performance counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
+\r
+\r
+/**\r
+ Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the\r
+ budget allocated for the package to exit from C7 to a C0 state, where\r
+ interrupt request can be delivered to the core and serviced. Additional\r
+ core-exit latency amy be applicable depending on the actual C-state the core\r
+ is in. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
+ /// that should be used to decide if the package should be put into a\r
+ /// package C7 state.\r
+ ///\r
+ UINT32 TimeLimit:10;\r
+ ///\r
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
+ /// unit of the interrupt response time limit. The following time unit\r
+ /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
+ /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
+ ///\r
+ UINT32 TimeUnit:3;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
+ /// valid and can be used by the processor for package C-sate management.\r
+ ///\r
+ UINT32 Valid:1;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A\r
+\r
+\r
+/**\r
+ Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
+ RAPL Domains.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640\r
+\r
+\r
+/**\r
+ Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641\r
+\r
+\r
+/**\r
+ Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 0, counter n event select MSR.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box n, unit status for counter 0-3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 0, performance counter n.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 1, counter n event select MSR.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 1, performance counter n.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 2, counter n event select MSR.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 2, performance counter n.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 3, counter n event select MSR.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 3, performance counter n.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 4, counter n event select MSR.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 4, performance counter n.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.\r
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. MC Bank Error Configuration (R/W).\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
+ /// to log additional info in bits 36:32.\r
+ ///\r
+ UINT32 MemErrorLogEnable:1;\r
+ UINT32 Reserved2:30;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS\r
+ /// counting logic for specific events requiring additional configuration,\r
+ /// see Table 19-17.\r
+ ///\r
+ UINT32 ENABLE_PEBS_NUM_ALT:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Package RAPL Perf Status (R/O).\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Package. Uncore U-box UCLK fixed counter control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08\r
+\r
+\r
+/**\r
+ Package. Uncore U-box UCLK fixed counter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon event select for U-box counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon event select for U-box counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon for PCU-box-wide control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon box-wide filter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon local box wide control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon box wide filter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon local box wide control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon box wide filter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon local box wide control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon box wide filter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon local box wide control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon box wide filter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon local box wide control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon box wide filter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon local box wide control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon box wide filter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon local box wide control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon box wide filter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon local box wide control.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon box wide filter.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 0.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 1.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 2.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 3.\r
+\r
+ @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);\r
+ @endcode\r
+ @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
+**/\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel processors based on the Silvermont microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __SILVERMONT_MSR_H__\r
+#define __SILVERMONT_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel processors based on the Silvermont microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x37 || \\r
+ DisplayModel == 0x4A || \\r
+ DisplayModel == 0x4D || \\r
+ DisplayModel == 0x5A || \\r
+ DisplayModel == 0x5D \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Module. Model Specific Platform ID (R).\r
+\r
+ @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);\r
+ @endcode\r
+ @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
+**/\r
+#define MSR_SILVERMONT_PLATFORM_ID 0x00000017\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
+ ///\r
+ UINT32 MaximumQualifiedRatio:5;\r
+ UINT32 Reserved2:19;\r
+ UINT32 Reserved3:18;\r
+ ///\r
+ /// [Bits 52:50] See Table 2-2.\r
+ ///\r
+ UINT32 PlatformId:3;\r
+ UINT32 Reserved4:11;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PLATFORM_ID_REGISTER;\r
+\r
+\r
+/**\r
+ Module. Processor Hard Power-On Configuration (R/W) Writes ignored.\r
+\r
+ @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
+**/\r
+#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ Core. SMI Counter (R/O).\r
+\r
+ @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_SMI_COUNT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);\r
+ @endcode\r
+ @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
+**/\r
+#define MSR_SILVERMONT_SMI_COUNT 0x00000034\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r
+ /// RESET.\r
+ ///\r
+ UINT32 SMICount:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_SMI_COUNT_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.\r
+\r
+ @param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type\r
+ MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type\r
+ MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Lock (R/WL).\r
+ ///\r
+ UINT32 Lock:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] Enable VMX outside SMX operation (R/WL).\r
+ ///\r
+ UINT32 EnableVmxOutsideSmx:1;\r
+ UINT32 Reserved2:29;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
+ record registers on the last branch record stack. The From_IP part of the\r
+ stack contains pointers to the source instruction. See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.5 and record format in Section\r
+ 17.4.8.1.\r
+\r
+ @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);\r
+ @endcode\r
+ @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040\r
+#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041\r
+#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042\r
+#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043\r
+#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044\r
+#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045\r
+#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046\r
+#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047\r
+/// @}\r
+\r
+\r
+/**\r
+ Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
+ record registers on the last branch record stack. The To_IP part of the\r
+ stack contains pointers to the destination instruction.\r
+\r
+ @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);\r
+ @endcode\r
+ @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
+ MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060\r
+#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061\r
+#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062\r
+#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063\r
+#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064\r
+#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065\r
+#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066\r
+#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067\r
+/// @}\r
+\r
+\r
+/**\r
+ Module. Scalable Bus Speed(RO) This field indicates the intended scalable\r
+ bus clock speed for processors based on Silvermont microarchitecture:.\r
+\r
+ @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_FSB_FREQ_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);\r
+ @endcode\r
+ @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
+**/\r
+#define MSR_SILVERMONT_FSB_FREQ 0x000000CD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Scalable Bus Speed\r
+ ///\r
+ /// Silvermont Processor Family\r
+ /// ---------------------------\r
+ /// 100B: 080.0 MHz\r
+ /// 000B: 083.3 MHz\r
+ /// 001B: 100.0 MHz\r
+ /// 010B: 133.3 MHz\r
+ /// 011B: 116.7 MHz\r
+ ///\r
+ /// Airmont Processor Family\r
+ /// ---------------------------\r
+ /// 0000B: 083.3 MHz\r
+ /// 0001B: 100.0 MHz\r
+ /// 0010B: 133.3 MHz\r
+ /// 0011B: 116.7 MHz\r
+ /// 0100B: 080.0 MHz\r
+ /// 0101B: 093.3 MHz\r
+ /// 0110B: 090.0 MHz\r
+ /// 0111B: 088.9 MHz\r
+ /// 1000B: 087.5 MHz\r
+ ///\r
+ UINT32 ScalableBusSpeed:4;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_FSB_FREQ_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Platform Information: Contains power management and other model\r
+ specific features enumeration. See http://biosbits.org.\r
+\r
+ @param ECX MSR_SILVERMONT_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio\r
+ /// of the maximum frequency that does not require turbo. Frequency =\r
+ /// ratio * Scalable Bus Frequency.\r
+ ///\r
+ UINT32 MaximumNon_TurboRatio:8;\r
+ UINT32 Reserved2:16;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;\r
+\r
+/**\r
+ Module. C-State Configuration Control (R/W) Note: C-state values are\r
+ processor specific C-state code names, unrelated to MWAIT extension C-state\r
+ parameters or ACPI CStates. See http://biosbits.org.\r
+\r
+ @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
+**/\r
+#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power). for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r
+ /// 100b: C4 110b: C6 111b: C7 (Silvermont only).\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
+ /// IO_read instructions sent to IO register specified by\r
+ /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
+ /// until next reset.\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:16;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Module. Power Management IO Redirection in C-state (R/W) See\r
+ http://biosbits.org.\r
+\r
+ @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
+**/\r
+#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
+ /// visible to software for IO redirection. If IO MWAIT Redirection is\r
+ /// enabled, reads to this address will be consumed by the power\r
+ /// management logic and decoded to MWAIT instructions. When IO port\r
+ /// address redirection is enabled, this is the IO port address reported\r
+ /// to the OS/software.\r
+ ///\r
+ UINT32 Lvl2Base:16;\r
+ ///\r
+ /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
+ /// maximum C-State code name to be included when IO read to MWAIT\r
+ /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4\r
+ /// is the max C-State to include 110b - C6 is the max C-State to include\r
+ /// 111b - C7 is the max C-State to include.\r
+ ///\r
+ UINT32 CStateRange:3;\r
+ UINT32 Reserved1:13;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Module.\r
+\r
+ @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
+**/\r
+#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
+ /// Indicates if the L2 is hardware-disabled.\r
+ ///\r
+ UINT32 L2HardwareEnabled:1;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r
+ /// Disabled (default) Until this bit is set the processor will not\r
+ /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
+ ///\r
+ UINT32 L2Enabled:1;\r
+ UINT32 Reserved2:14;\r
+ ///\r
+ /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
+ ///\r
+ UINT32 L2NotPresent:1;\r
+ UINT32 Reserved3:8;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;\r
+\r
+\r
+/**\r
+ Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+ handler to handle unsuccessful read of this MSR.\r
+\r
+ @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
+**/\r
+#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
+ /// MSR, the configuration of AES instruction set availability is as\r
+ /// follows: 11b: AES instructions are not available until next RESET.\r
+ /// otherwise, AES instructions are available. Note, AES instruction set\r
+ /// is not available if read is unsuccessful. If the configuration is not\r
+ /// 01b, AES instruction can be mis-configured if a privileged agent\r
+ /// unintentionally writes 11b.\r
+ ///\r
+ UINT32 AESConfiguration:2;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See\r
+ /// Table 2-2. Default value is 0.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved4:3;\r
+ ///\r
+ /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
+ /// Table 2-2.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ UINT32 Reserved6:3;\r
+ ///\r
+ /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved7:8;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved9:3;\r
+ ///\r
+ /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors\r
+ /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
+ /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
+ /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
+ /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
+ /// the power-on default value is used by BIOS to detect hardware support\r
+ /// of turbo mode. If power-on default value is 1, turbo mode is available\r
+ /// in the processor. If power-on default value is 0, turbo mode is not\r
+ /// available.\r
+ ///\r
+ UINT32 TurboModeDisable:1;\r
+ UINT32 Reserved10:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
+**/\r
+#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (R) The default thermal throttling or\r
+ /// PROCHOT# activation temperature in degree C, The effective temperature\r
+ /// for thermal throttling or PROCHOT# activation is "Temperature Target"\r
+ /// + "Target Offset".\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ ///\r
+ /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to\r
+ /// adjust the throttling and PROCHOT# activation temperature from the\r
+ /// default target specified in TEMPERATURE_TARGET (bits 23:16).\r
+ ///\r
+ UINT32 TargetOffset:6;\r
+ UINT32 Reserved2:2;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;\r
+\r
+\r
+/**\r
+ Miscellaneous Feature Control (R/W).\r
+\r
+ @param ECX MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L2 hardware prefetcher, which fetches additional lines of code or data\r
+ /// into the L2 cache.\r
+ ///\r
+ UINT32 L2HardwarePrefetcherDisable:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
+ /// the L1 data cache prefetcher, which fetches the next cache line into\r
+ /// L1 data cache.\r
+ ///\r
+ UINT32 DCUHardwarePrefetcherDisable:1;\r
+ UINT32 Reserved2:29;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Module. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);\r
+ @endcode\r
+ @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
+**/\r
+#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6\r
+\r
+\r
+/**\r
+ Module. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);\r
+ @endcode\r
+ @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
+**/\r
+#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode (RW).\r
+\r
+ @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
+ /// limit of 5 core active.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
+ /// limit of 6 core active.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
+ /// limit of 7 core active.\r
+ ///\r
+ UINT32 Maximum7C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
+ /// limit of 8 core active.\r
+ ///\r
+ UINT32 Maximum8C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
+ "Filtering of Last Branch Records.".\r
+\r
+ @param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_LBR_SELECT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
+**/\r
+#define MSR_SILVERMONT_LBR_SELECT 0x000001C8\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] CPL_EQ_0.\r
+ ///\r
+ UINT32 CPL_EQ_0:1;\r
+ ///\r
+ /// [Bit 1] CPL_NEQ_0.\r
+ ///\r
+ UINT32 CPL_NEQ_0:1;\r
+ ///\r
+ /// [Bit 2] JCC.\r
+ ///\r
+ UINT32 JCC:1;\r
+ ///\r
+ /// [Bit 3] NEAR_REL_CALL.\r
+ ///\r
+ UINT32 NEAR_REL_CALL:1;\r
+ ///\r
+ /// [Bit 4] NEAR_IND_CALL.\r
+ ///\r
+ UINT32 NEAR_IND_CALL:1;\r
+ ///\r
+ /// [Bit 5] NEAR_RET.\r
+ ///\r
+ UINT32 NEAR_RET:1;\r
+ ///\r
+ /// [Bit 6] NEAR_IND_JMP.\r
+ ///\r
+ UINT32 NEAR_IND_JMP:1;\r
+ ///\r
+ /// [Bit 7] NEAR_REL_JMP.\r
+ ///\r
+ UINT32 NEAR_REL_JMP:1;\r
+ ///\r
+ /// [Bit 8] FAR_BRANCH.\r
+ ///\r
+ UINT32 FAR_BRANCH:1;\r
+ UINT32 Reserved1:23;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_LBR_SELECT_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that\r
+ points to the MSR containing the most recent branch record. See\r
+ MSR_LASTBRANCH_0_FROM_IP.\r
+\r
+ @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Core. Last Exception Record From Linear IP (R) Contains a pointer to the\r
+ last branch instruction that the processor executed prior to the last\r
+ exception that was generated or the last interrupt that was handled.\r
+\r
+ @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);\r
+ @endcode\r
+ @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
+**/\r
+#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Core. Last Exception Record To Linear IP (R) This area contains a pointer\r
+ to the target of the last branch instruction that the processor executed\r
+ prior to the last exception that was generated or the last interrupt that\r
+ was handled.\r
+\r
+ @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);\r
+ @endcode\r
+ @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
+**/\r
+#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE\r
+\r
+\r
+/**\r
+ Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
+ (PEBS).".\r
+\r
+ @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
+**/\r
+#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C6 states. Counts at the TSC Frequency.\r
+\r
+ @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
+ Residency Counter. (R/O) Value since last reset that this core is in\r
+ processor-specific C6 states. Counts at the TSC Frequency.\r
+\r
+ @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r
+\r
+\r
+/**\r
+ Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
+\r
+ @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);\r
+ @endcode\r
+ @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
+**/\r
+#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
+\r
+\r
+/**\r
+ Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r
+ 2-2.\r
+\r
+ @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);\r
+ @endcode\r
+ @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
+**/\r
+#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1\r
+ Residency Counter. (R/O) Value since last reset that this core is in\r
+ processor-specific C1 states. Counts at the TSC frequency.\r
+\r
+ @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
+ "RAPL Interfaces.".\r
+\r
+ @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);\r
+ @endcode\r
+ @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
+**/\r
+#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Power Units. Power related information (in milliWatts) is\r
+ /// based on the multiplier, 2^PU; where PU is an unsigned integer\r
+ /// represented by bits 3:0. Default value is 0101b, indicating power unit\r
+ /// is in 32 milliWatts increment.\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Energy Status Units. Energy related information (in\r
+ /// microJoules) is based on the multiplier, 2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 00101b,\r
+ /// indicating energy unit is in 32 microJoules increment.\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in\r
+ /// one second.\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Power Limit Control (R/W).\r
+\r
+ @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package\r
+ /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.\r
+ ///\r
+ UINT32 Limit:15;\r
+ ///\r
+ /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package\r
+ /// RAPL Domain.".\r
+ ///\r
+ UINT32 Enable:1;\r
+ ///\r
+ /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,\r
+ /// "Package RAPL Domain.".\r
+ ///\r
+ UINT32 ClampingLimit:1;\r
+ ///\r
+ /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.\r
+ /// If 0 is specified in bits [23:17], defaults to 1 second window.\r
+ ///\r
+ UINT32 Time:7;\r
+ UINT32 Reserved1:8;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."\r
+ and MSR_RAPL_POWER_UNIT in Table 2-8.\r
+\r
+ @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611\r
+\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."\r
+ and MSR_RAPL_POWER_UNIT in Table 2-8.\r
+\r
+ @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion\r
+ policy. Writing a value of 0 disables core level HW demotion policy.\r
+\r
+ @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);\r
+ @endcode\r
+ @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.\r
+**/\r
+#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668\r
+\r
+\r
+/**\r
+ Package. Module C6 demotion policy config MSR. Controls module (i.e. two\r
+ cores sharing the second-level cache) C6 demotion policy. Writing a value of\r
+ 0 disables module level HW demotion policy.\r
+\r
+ @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);\r
+ @endcode\r
+ @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.\r
+**/\r
+#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669\r
+\r
+\r
+/**\r
+ Module. Module C6 Residency Counter (R/0) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI CStates. Time that this module is in module-specific C6 states since\r
+ last reset. Counts at 1 Mhz frequency.\r
+\r
+ @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);\r
+ @endcode\r
+ @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.\r
+**/\r
+#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Parameter (R/0).\r
+\r
+ @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);\r
+ @endcode\r
+ @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
+**/\r
+#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is\r
+ /// the equivalent of thermal specification power of the package domain.\r
+ /// The unit of this field is specified by the "Power Units" field of\r
+ /// MSR_RAPL_POWER_UNIT.\r
+ ///\r
+ UINT32 ThermalSpecPower:15;\r
+ UINT32 Reserved1:17;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PP0 RAPL Power Limit Control (R/W).\r
+\r
+ @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
+ /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.\r
+ ///\r
+ UINT32 Limit:15;\r
+ ///\r
+ /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
+ /// RAPL Domains.".\r
+ ///\r
+ UINT32 Enable:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time\r
+ /// duration over which the average power must remain below\r
+ /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time\r
+ /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time\r
+ /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.\r
+ /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35\r
+ /// second time duration. 0x8: 40 second time duration. 0x9: 45 second\r
+ /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.\r
+ ///\r
+ UINT32 Time:7;\r
+ UINT32 Reserved2:8;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Defintions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __SKYLAKE_MSR_H__\r
+#define __SKYLAKE_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel processors based on the Skylake microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x4E || \\r
+ DisplayModel == 0x5E || \\r
+ DisplayModel == 0x55 || \\r
+ DisplayModel == 0x8E || \\r
+ DisplayModel == 0x9E || \\r
+ DisplayModel == 0x66 \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+ @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)\r
+ that points to the MSR containing the most recent branch record.\r
+\r
+ @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Core. Power Control Register See http://biosbits.org.\r
+\r
+ @param ECX MSR_SKYLAKE_POWER_CTL (0x000001FC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_POWER_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_POWER_CTL 0x000001FC\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU\r
+ /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating\r
+ /// point when all execution cores enter MWAIT (C1).\r
+ ///\r
+ UINT32 C1EEnable:1;\r
+ UINT32 Reserved2:17;\r
+ ///\r
+ /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit\r
+ /// disables the Race to Halt optimization and avoids this optimization\r
+ /// limitation to execute below the most efficient frequency ratio.\r
+ /// Default value is 0 for processors that support Race to Halt\r
+ /// optimization. Default value is 1 for processors that do not support\r
+ /// Race to Halt optimization.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ ///\r
+ /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit\r
+ /// disables the P-States energy efficiency optimization. Default value is\r
+ /// 0. Disable/enable the energy efficiency optimization in P-State legacy\r
+ /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the\r
+ /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP\r
+ /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS\r
+ /// desired or OS maximize to the OS minimize performance setting.\r
+ ///\r
+ UINT32 DisableEnergyEfficiencyOptimization:1;\r
+ UINT32 Reserved3:11;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_POWER_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
+ CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
+ the package. Lower 64 bits of an 128-bit external entropy value for key\r
+ derivation of an enclave.\r
+\r
+ @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = 0;\r
+ AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300\r
+\r
+//\r
+// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.\r
+//\r
+#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0\r
+/**\r
+ Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
+ CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
+ the package. Upper 64 bits of an 128-bit external entropy value for key\r
+ derivation of an enclave.\r
+\r
+ @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = 0;\r
+ AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301\r
+\r
+//\r
+// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.\r
+//\r
+#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1\r
+\r
+\r
+/**\r
+ See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
+ Version 4.".\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Thread. Ovf_PMC0.\r
+ ///\r
+ UINT32 Ovf_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Thread. Ovf_PMC1.\r
+ ///\r
+ UINT32 Ovf_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Thread. Ovf_PMC2.\r
+ ///\r
+ UINT32 Ovf_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Thread. Ovf_PMC3.\r
+ ///\r
+ UINT32 Ovf_PMC3:1;\r
+ ///\r
+ /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
+ ///\r
+ UINT32 Ovf_PMC4:1;\r
+ ///\r
+ /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
+ ///\r
+ UINT32 Ovf_PMC5:1;\r
+ ///\r
+ /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
+ ///\r
+ UINT32 Ovf_PMC6:1;\r
+ ///\r
+ /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
+ ///\r
+ UINT32 Ovf_PMC7:1;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bit 32] Thread. Ovf_FixedCtr0.\r
+ ///\r
+ UINT32 Ovf_FixedCtr0:1;\r
+ ///\r
+ /// [Bit 33] Thread. Ovf_FixedCtr1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr1:1;\r
+ ///\r
+ /// [Bit 34] Thread. Ovf_FixedCtr2.\r
+ ///\r
+ UINT32 Ovf_FixedCtr2:1;\r
+ UINT32 Reserved2:20;\r
+ ///\r
+ /// [Bit 55] Thread. Trace_ToPA_PMI.\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 58] Thread. LBR_Frz.\r
+ ///\r
+ UINT32 LBR_Frz:1;\r
+ ///\r
+ /// [Bit 59] Thread. CTR_Frz.\r
+ ///\r
+ UINT32 CTR_Frz:1;\r
+ ///\r
+ /// [Bit 60] Thread. ASCI.\r
+ ///\r
+ UINT32 ASCI:1;\r
+ ///\r
+ /// [Bit 61] Thread. Ovf_Uncore.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Thread. Ovf_BufDSSAVE.\r
+ ///\r
+ UINT32 Ovf_BufDSSAVE:1;\r
+ ///\r
+ /// [Bit 63] Thread. CondChgd.\r
+ ///\r
+ UINT32 CondChgd:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
+ Version 4.".\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
+**/\r
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
+ ///\r
+ UINT32 Ovf_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
+ ///\r
+ UINT32 Ovf_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
+ ///\r
+ UINT32 Ovf_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
+ ///\r
+ UINT32 Ovf_PMC3:1;\r
+ ///\r
+ /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
+ ///\r
+ UINT32 Ovf_PMC4:1;\r
+ ///\r
+ /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
+ ///\r
+ UINT32 Ovf_PMC5:1;\r
+ ///\r
+ /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
+ ///\r
+ UINT32 Ovf_PMC6:1;\r
+ ///\r
+ /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
+ ///\r
+ UINT32 Ovf_PMC7:1;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
+ ///\r
+ UINT32 Ovf_FixedCtr0:1;\r
+ ///\r
+ /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr1:1;\r
+ ///\r
+ /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
+ ///\r
+ UINT32 Ovf_FixedCtr2:1;\r
+ UINT32 Reserved2:20;\r
+ ///\r
+ /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 58] Thread. Set 1 to clear LBR_Frz.\r
+ ///\r
+ UINT32 LBR_Frz:1;\r
+ ///\r
+ /// [Bit 59] Thread. Set 1 to clear CTR_Frz.\r
+ ///\r
+ UINT32 CTR_Frz:1;\r
+ ///\r
+ /// [Bit 60] Thread. Set 1 to clear ASCI.\r
+ ///\r
+ UINT32 ASCI:1;\r
+ ///\r
+ /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
+ ///\r
+ UINT32 Ovf_BufDSSAVE:1;\r
+ ///\r
+ /// [Bit 63] Thread. Set 1 to clear CondChgd.\r
+ ///\r
+ UINT32 CondChgd:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
+\r
+\r
+/**\r
+ See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
+ Version 4.".\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
+**/\r
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.\r
+ ///\r
+ UINT32 Ovf_PMC0:1;\r
+ ///\r
+ /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.\r
+ ///\r
+ UINT32 Ovf_PMC1:1;\r
+ ///\r
+ /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.\r
+ ///\r
+ UINT32 Ovf_PMC2:1;\r
+ ///\r
+ /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.\r
+ ///\r
+ UINT32 Ovf_PMC3:1;\r
+ ///\r
+ /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).\r
+ ///\r
+ UINT32 Ovf_PMC4:1;\r
+ ///\r
+ /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).\r
+ ///\r
+ UINT32 Ovf_PMC5:1;\r
+ ///\r
+ /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).\r
+ ///\r
+ UINT32 Ovf_PMC6:1;\r
+ ///\r
+ /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).\r
+ ///\r
+ UINT32 Ovf_PMC7:1;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr0:1;\r
+ ///\r
+ /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr1:1;\r
+ ///\r
+ /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.\r
+ ///\r
+ UINT32 Ovf_FixedCtr2:1;\r
+ UINT32 Reserved2:20;\r
+ ///\r
+ /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.\r
+ ///\r
+ UINT32 Trace_ToPA_PMI:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.\r
+ ///\r
+ UINT32 LBR_Frz:1;\r
+ ///\r
+ /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.\r
+ ///\r
+ UINT32 CTR_Frz:1;\r
+ ///\r
+ /// [Bit 60] Thread. Set 1 to cause ASCI = 1.\r
+ ///\r
+ UINT32 ASCI:1;\r
+ ///\r
+ /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.\r
+ ///\r
+ UINT32 Ovf_Uncore:1;\r
+ ///\r
+ /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.\r
+ ///\r
+ UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Reserved4:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. FrontEnd Precise Event Condition Select (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.\r
+**/\r
+#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Event Code Select.\r
+ ///\r
+ UINT32 EventCodeSelect:3;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 4] Event Code Select High.\r
+ ///\r
+ UINT32 EventCodeSelectHigh:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:8] IDQ_Bubble_Length Specifier.\r
+ ///\r
+ UINT32 IDQ_Bubble_Length:12;\r
+ ///\r
+ /// [Bits 22:20] IDQ_Bubble_Width Specifier.\r
+ ///\r
+ UINT32 IDQ_Bubble_Width:3;\r
+ UINT32 Reserved3:9;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both\r
+ platform vendor hardware implementation and BIOS enablement support it. This\r
+ MSR will read 0 if not valid.\r
+\r
+ @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);\r
+ @endcode\r
+ @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.\r
+**/\r
+#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Total energy consumed by all devices in the platform that\r
+ /// receive power from integrated power delivery mechanism, Included\r
+ /// platform devices are processor cores, SOC, memory, add-on or\r
+ /// peripheral devices that get powered directly from the platform power\r
+ /// delivery means. The energy units are specified in the\r
+ /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.\r
+ ///\r
+ UINT32 TotalEnergy:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Productive Performance Count. (R/O). Hardware's view of workload\r
+ scalability. See Section 14.4.5.1.\r
+\r
+ @param ECX MSR_SKYLAKE_PPERF (0x0000064E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);\r
+ @endcode\r
+ @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.\r
+**/\r
+#define MSR_SKYLAKE_PPERF 0x0000064E\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
+ refers to processor core frequency).\r
+\r
+ @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
+**/\r
+#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to assertion of external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to a thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to residency state\r
+ /// regulation limit.\r
+ ///\r
+ UINT32 ResidencyStateRegulationStatus:1;\r
+ ///\r
+ /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
+ /// is reduced below the operating system request due to Running Average\r
+ /// Thermal Limit (RATL).\r
+ ///\r
+ UINT32 RunningAverageThermalLimitStatus:1;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to a thermal alert from a\r
+ /// processor Voltage Regulator (VR).\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ ///\r
+ /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to VR thermal design\r
+ /// current limit.\r
+ ///\r
+ UINT32 VRThermDesignCurrentStatus:1;\r
+ ///\r
+ /// [Bit 8] Other Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to electrical or other constraints.\r
+ ///\r
+ UINT32 OtherStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
+ /// set, frequency is reduced below the operating system request due to\r
+ /// package/platform-level power limiting PL1.\r
+ ///\r
+ UINT32 PL1Status:1;\r
+ ///\r
+ /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
+ /// set, frequency is reduced below the operating system request due to\r
+ /// package/platform-level power limiting PL2/PL3.\r
+ ///\r
+ UINT32 PL2Status:1;\r
+ ///\r
+ /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to multi-core turbo limits.\r
+ ///\r
+ UINT32 MaxTurboLimitStatus:1;\r
+ ///\r
+ /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
+ /// is reduced below the operating system request due to Turbo transition\r
+ /// attenuation. This prevents performance degradation due to frequent\r
+ /// operating ratio changes.\r
+ ///\r
+ UINT32 TurboTransitionAttenuationStatus:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 20] Residency State Regulation Log When set, indicates that the\r
+ /// Residency State Regulation Status bit has asserted since the log bit\r
+ /// was last cleared. This log bit will remain set until cleared by\r
+ /// software writing 0.\r
+ ///\r
+ UINT32 ResidencyStateRegulationLog:1;\r
+ ///\r
+ /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
+ /// the RATL Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 RunningAverageThermalLimitLog:1;\r
+ ///\r
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ ///\r
+ /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
+ /// VR TDC Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermalDesignCurrentLog:1;\r
+ ///\r
+ /// [Bit 24] Other Log When set, indicates that the Other Status bit has\r
+ /// asserted since the log bit was last cleared. This log bit will remain\r
+ /// set until cleared by software writing 0.\r
+ ///\r
+ UINT32 OtherLog:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
+ /// indicates that the Package or Platform Level PL1 Power Limiting Status\r
+ /// bit has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PL1Log:1;\r
+ ///\r
+ /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
+ /// indicates that the Package or Platform Level PL2/PL3 Power Limiting\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PL2Log:1;\r
+ ///\r
+ /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
+ /// Limit Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 MaxTurboLimitLog:1;\r
+ ///\r
+ /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
+ /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
+ /// was last cleared. This log bit will remain set until cleared by\r
+ /// software writing 0.\r
+ ///\r
+ UINT32 TurboTransitionAttenuationLog:1;\r
+ UINT32 Reserved6:2;\r
+ UINT32 Reserved7:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. HDC Configuration (R/W)..\r
+\r
+ @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.\r
+**/\r
+#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for\r
+ /// MSR_PKG_HDC_DEEP_RESIDENCY.\r
+ ///\r
+ UINT32 PKG_Cx_Monitor:3;\r
+ UINT32 Reserved1:29;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.\r
+\r
+ @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);\r
+ @endcode\r
+ @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653\r
+\r
+\r
+/**\r
+ Package. Accumulate the cycles the package was in C2 state and at least one\r
+ logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.\r
+\r
+ @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);\r
+ @endcode\r
+ @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655\r
+\r
+\r
+/**\r
+ Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.\r
+\r
+ @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);\r
+ @endcode\r
+ @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.\r
+**/\r
+#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656\r
+\r
+\r
+/**\r
+ Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate\r
+ as the TSC. The increment each cycle is weighted by the number of processor\r
+ cores in the package that reside in C0. If N cores are simultaneously in C0,\r
+ then each cycle the counter increments by N.\r
+\r
+ @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);\r
+ @endcode\r
+ @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658\r
+\r
+\r
+/**\r
+ Package. Any Core C0 Residency. (R/O). Increment at the same rate as the\r
+ TSC. The increment each cycle is one if any processor core in the package is\r
+ in C0.\r
+\r
+ @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);\r
+ @endcode\r
+ @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659\r
+\r
+\r
+/**\r
+ Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate\r
+ as the TSC. The increment each cycle is one if any processor graphic\r
+ device's compute engines are in C0.\r
+\r
+ @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);\r
+ @endcode\r
+ @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A\r
+\r
+\r
+/**\r
+ Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment\r
+ at the same rate as the TSC. The increment each cycle is one if at least one\r
+ compute engine of the processor graphics is in C0 and at least one processor\r
+ core in the package is also in C0.\r
+\r
+ @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);\r
+ @endcode\r
+ @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B\r
+\r
+\r
+/**\r
+ Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to\r
+ limit power consumption of the platform devices to the specified values. The\r
+ Long Duration power consumption is specified via Platform_Power_Limit_1 and\r
+ Platform_Power_Limit_1_Time. The Short Duration power consumption limit is\r
+ specified via the Platform_Power_Limit_2 with duration chosen by the\r
+ processor. The processor implements an exponential-weighted algorithm in the\r
+ placement of the time windows.\r
+\r
+ @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which\r
+ /// the platform must not exceed over a time window as specified by\r
+ /// Power_Limit_1_TIME field. The default value is the Thermal Design\r
+ /// Power (TDP) and varies with product skus. The unit is specified in\r
+ /// MSR_RAPLPOWER_UNIT.\r
+ ///\r
+ UINT32 PlatformPowerLimit1:15;\r
+ ///\r
+ /// [Bit 15] Enable Platform Power Limit #1. When set, enables the\r
+ /// processor to apply control policy such that the platform power does\r
+ /// not exceed Platform Power limit #1 over the time window specified by\r
+ /// Power Limit #1 Time Window.\r
+ ///\r
+ UINT32 EnablePlatformPowerLimit1:1;\r
+ ///\r
+ /// [Bit 16] Platform Clamping Limitation #1. When set, allows the\r
+ /// processor to go below the OS requested P states in order to maintain\r
+ /// the power below specified Platform Power Limit #1 value. This bit is\r
+ /// writeable only when CPUID (EAX=6):EAX[4] is set.\r
+ ///\r
+ UINT32 PlatformClampingLimitation1:1;\r
+ ///\r
+ /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the\r
+ /// duration of the time window over which Platform Power Limit 1 value\r
+ /// should be maintained for sustained long duration. This field is made\r
+ /// up of two numbers from the following equation: Time Window = (float)\r
+ /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =\r
+ /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is\r
+ /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,\r
+ /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].\r
+ ///\r
+ UINT32 Time:7;\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which\r
+ /// the platform must not exceed over the Short Duration time window\r
+ /// chosen by the processor. The recommended default value is 1.25 times\r
+ /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).\r
+ ///\r
+ UINT32 PlatformPowerLimit2:15;\r
+ ///\r
+ /// [Bit 47] Enable Platform Power Limit #2. When set, enables the\r
+ /// processor to apply control policy such that the platform power does\r
+ /// not exceed Platform Power limit #2 over the Short Duration time window.\r
+ ///\r
+ UINT32 EnablePlatformPowerLimit2:1;\r
+ ///\r
+ /// [Bit 48] Platform Clamping Limitation #2. When set, allows the\r
+ /// processor to go below the OS requested P states in order to maintain\r
+ /// the power below specified Platform Power Limit #2 value.\r
+ ///\r
+ UINT32 PlatformClampingLimitation2:1;\r
+ UINT32 Reserved2:14;\r
+ ///\r
+ /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR\r
+ /// until system RESET.\r
+ ///\r
+ UINT32 Lock:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last\r
+ branch record registers on the last branch record stack. This part of the\r
+ stack contains pointers to the source instruction. See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.10.\r
+\r
+ @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690\r
+#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691\r
+#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692\r
+#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693\r
+#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694\r
+#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695\r
+#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696\r
+#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697\r
+#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698\r
+#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699\r
+#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A\r
+#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B\r
+#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C\r
+#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D\r
+#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E\r
+#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
+ (frequency refers to processor graphics frequency).\r
+\r
+ @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r
+**/\r
+#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
+ /// assertion of external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
+ /// thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
+ /// is reduced due to running average thermal limit.\r
+ ///\r
+ UINT32 RunningAverageThermalLimitStatus:1;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
+ /// to a thermal alert from a processor Voltage Regulator.\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ ///\r
+ /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
+ /// reduced due to VR TDC limit.\r
+ ///\r
+ UINT32 VRThermalDesignCurrentStatus:1;\r
+ ///\r
+ /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
+ /// electrical or other constraints.\r
+ ///\r
+ UINT32 OtherStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
+ /// set, frequency is reduced due to package/platform-level power limiting\r
+ /// PL1.\r
+ ///\r
+ UINT32 PL1Status:1;\r
+ ///\r
+ /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
+ /// set, frequency is reduced due to package/platform-level power limiting\r
+ /// PL2/PL3.\r
+ ///\r
+ UINT32 PL2Status:1;\r
+ ///\r
+ /// [Bit 12] Inefficient Operation Status (R0) When set, processor\r
+ /// graphics frequency is operating below target frequency.\r
+ ///\r
+ UINT32 InefficientOperationStatus:1;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ UINT32 Reserved4:3;\r
+ ///\r
+ /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
+ /// the RATL Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 RunningAverageThermalLimitLog:1;\r
+ ///\r
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ ///\r
+ /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
+ /// VR Therm Alert Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 VRThermalDesignCurrentLog:1;\r
+ ///\r
+ /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
+ /// asserted since the log bit was last cleared. This log bit will remain\r
+ /// set until cleared by software writing 0.\r
+ ///\r
+ UINT32 OtherLog:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
+ /// indicates that the Package/Platform Level PL1 Power Limiting Status\r
+ /// bit has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PL1Log:1;\r
+ ///\r
+ /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
+ /// indicates that the Package/Platform Level PL2 Power Limiting Status\r
+ /// bit has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PL2Log:1;\r
+ ///\r
+ /// [Bit 28] Inefficient Operation Log When set, indicates that the\r
+ /// Inefficient Operation Status bit has asserted since the log bit was\r
+ /// last cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 InefficientOperationLog:1;\r
+ UINT32 Reserved6:3;\r
+ UINT32 Reserved7:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
+ (frequency refers to ring interconnect in the uncore).\r
+\r
+ @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
+**/\r
+#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
+ /// assertion of external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
+ /// thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
+ /// is reduced due to running average thermal limit.\r
+ ///\r
+ UINT32 RunningAverageThermalLimitStatus:1;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
+ /// to a thermal alert from a processor Voltage Regulator.\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ ///\r
+ /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
+ /// reduced due to VR TDC limit.\r
+ ///\r
+ UINT32 VRThermalDesignCurrentStatus:1;\r
+ ///\r
+ /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
+ /// electrical or other constraints.\r
+ ///\r
+ UINT32 OtherStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
+ /// set, frequency is reduced due to package/Platform-level power limiting\r
+ /// PL1.\r
+ ///\r
+ UINT32 PL1Status:1;\r
+ ///\r
+ /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
+ /// set, frequency is reduced due to package/Platform-level power limiting\r
+ /// PL2/PL3.\r
+ ///\r
+ UINT32 PL2Status:1;\r
+ UINT32 Reserved3:4;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ UINT32 Reserved4:3;\r
+ ///\r
+ /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
+ /// the RATL Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 RunningAverageThermalLimitLog:1;\r
+ ///\r
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ ///\r
+ /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
+ /// VR Therm Alert Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 VRThermalDesignCurrentLog:1;\r
+ ///\r
+ /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
+ /// asserted since the log bit was last cleared. This log bit will remain\r
+ /// set until cleared by software writing 0.\r
+ ///\r
+ UINT32 OtherLog:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
+ /// indicates that the Package/Platform Level PL1 Power Limiting Status\r
+ /// bit has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PL1Log:1;\r
+ ///\r
+ /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
+ /// indicates that the Package/Platform Level PL2 Power Limiting Status\r
+ /// bit has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PL2Log:1;\r
+ UINT32 Reserved6:4;\r
+ UINT32 Reserved7:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch\r
+ record registers on the last branch record stack. This part of the stack\r
+ contains pointers to the destination instruction. See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.10.\r
+\r
+ @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.\r
+ MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
+ @{\r
+**/\r
+#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0\r
+#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1\r
+#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2\r
+#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3\r
+#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4\r
+#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5\r
+#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6\r
+#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7\r
+#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8\r
+#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9\r
+#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA\r
+#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB\r
+#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC\r
+#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD\r
+#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE\r
+#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF\r
+/// @}\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet\r
+ of last branch record registers on the last branch record stack. This part\r
+ of the stack contains flag, TSX-related and elapsed cycle information. See\r
+ also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR\r
+ Stack.".\r
+\r
+ @param ECX MSR_SKYLAKE_LBR_INFO_n\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.\r
+ MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.\r
+ @{\r
+**/\r
+#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0\r
+#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1\r
+#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2\r
+#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3\r
+#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4\r
+#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5\r
+#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6\r
+#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7\r
+#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8\r
+#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9\r
+#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA\r
+#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB\r
+#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC\r
+#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD\r
+#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE\r
+#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF\r
+#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0\r
+#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1\r
+#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2\r
+#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3\r
+#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4\r
+#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5\r
+#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6\r
+#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7\r
+#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8\r
+#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9\r
+#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA\r
+#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB\r
+#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC\r
+#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD\r
+#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE\r
+#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore fixed counter control (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:20;\r
+ ///\r
+ /// [Bit 20] Enable overflow propagation.\r
+ ///\r
+ UINT32 EnableOverflow:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 22] Enable counting.\r
+ ///\r
+ UINT32 EnableCounting:1;\r
+ UINT32 Reserved3:9;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore fixed counter.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Current count.\r
+ ///\r
+ UINT32 CurrentCount:32;\r
+ ///\r
+ /// [Bits 43:32] Current count.\r
+ ///\r
+ UINT32 CurrentCountHi:12;\r
+ UINT32 Reserved:20;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box configuration information (R/O).\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Specifies the number of C-Box units with programmable\r
+ /// counters (including processor cores and processor graphics),.\r
+ ///\r
+ UINT32 CBox:4;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, performance counter 0.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, performance counter 1.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
+\r
+\r
+/**\r
+ Package. Uncore Arb unit, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 0, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 0, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 0, performance counter 0.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 0, performance counter 1.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 1, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 1, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 1, performance counter 0.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 1, performance counter 1.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 2, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 2, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 2, performance counter 0.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 2, performance counter 1.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 3, counter 0 event select MSR.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 3, counter 1 event select MSR.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 3, performance counter 0.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736\r
+\r
+\r
+/**\r
+ Package. Uncore C-Box 3, performance counter 1.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737\r
+\r
+\r
+/**\r
+ Package. Uncore PMU global control.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Slice 0 select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice0:1;\r
+ ///\r
+ /// [Bit 1] Slice 1 select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice1:1;\r
+ ///\r
+ /// [Bit 2] Slice 2 select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice2:1;\r
+ ///\r
+ /// [Bit 3] Slice 3 select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice3:1;\r
+ ///\r
+ /// [Bit 4] Slice 4select.\r
+ ///\r
+ UINT32 PMI_Sel_Slice4:1;\r
+ UINT32 Reserved1:14;\r
+ UINT32 Reserved2:10;\r
+ ///\r
+ /// [Bit 29] Enable all uncore counters.\r
+ ///\r
+ UINT32 EN:1;\r
+ ///\r
+ /// [Bit 30] Enable wake on PMI.\r
+ ///\r
+ UINT32 WakePMI:1;\r
+ ///\r
+ /// [Bit 31] Enable Freezing counter when overflow.\r
+ ///\r
+ UINT32 FREEZE:1;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore PMU main status.\r
+\r
+ @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
+**/\r
+#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fixed counter overflowed.\r
+ ///\r
+ UINT32 Fixed:1;\r
+ ///\r
+ /// [Bit 1] An ARB counter overflowed.\r
+ ///\r
+ UINT32 ARB:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 3] A CBox counter overflowed (on any slice).\r
+ ///\r
+ UINT32 CBox:1;\r
+ UINT32 Reserved2:28;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. NPK Address Used by AET Messages (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock\r
+ /// bit has to be set in order for the AET packets to be directed to NPK\r
+ /// MMIO.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ UINT32 Reserved:17;\r
+ ///\r
+ /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
+ ///\r
+ UINT32 ACPIBAR_BASE_ADDRESS:14;\r
+ ///\r
+ /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
+ ///\r
+ UINT32 Fix_Me_2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Processor Reserved Memory Range Register - Physical Base Control\r
+ Register (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] MemType PRMRR BASE MemType.\r
+ ///\r
+ UINT32 MemTypePRMRRBASEMemType:3;\r
+ UINT32 Reserved1:9;\r
+ ///\r
+ /// [Bits 31:12] Base PRMRR Base Address.\r
+ ///\r
+ UINT32 BasePRMRRBaseAddress:20;\r
+ ///\r
+ /// [Bits 45:32] Base PRMRR Base Address.\r
+ ///\r
+ UINT32 Fix_Me_1:14;\r
+ UINT32 Reserved2:18;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Processor Reserved Memory Range Register - Physical Mask Control\r
+ Register (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:10;\r
+ ///\r
+ /// [Bit 10] Lock Lock bit for the PRMRR.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ ///\r
+ /// [Bit 11] VLD Enable bit for the PRMRR.\r
+ ///\r
+ UINT32 VLD:1;\r
+ ///\r
+ /// [Bits 31:12] Mask PRMRR MASK bits.\r
+ ///\r
+ UINT32 Fix_Me_2:20;\r
+ ///\r
+ /// [Bits 45:32] Mask PRMRR MASK bits.\r
+ ///\r
+ UINT32 Fix_Me_3:14;\r
+ UINT32 Reserved2:18;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Valid PRMRR Configurations (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] 1M supported MEE size.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bit 5] 32M supported MEE size.\r
+ ///\r
+ UINT32 Fix_Me_2:1;\r
+ ///\r
+ /// [Bit 6] 64M supported MEE size.\r
+ ///\r
+ UINT32 Fix_Me_3:1;\r
+ ///\r
+ /// [Bit 7] 128M supported MEE size.\r
+ ///\r
+ UINT32 Fix_Me_4:1;\r
+ UINT32 Reserved2:24;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Package. (R/W) The PRMRR range is used to protect Xucode memory from\r
+ unauthorized reads and writes. Any IO access to this range is aborted. This\r
+ register controls the location of the PRMRR range by indicating its starting\r
+ address. It functions in tandem with the PRMRR mask register.\r
+\r
+ @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:12;\r
+ ///\r
+ /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the\r
+ /// base address memory range which is allocated to PRMRR memory.\r
+ ///\r
+ UINT32 Fix_Me_1:20;\r
+ ///\r
+ /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the\r
+ /// base address memory range which is allocated to PRMRR memory.\r
+ ///\r
+ UINT32 Fix_Me_2:7;\r
+ UINT32 Reserved2:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Package. (R/W) This register controls the size of the PRMRR range by\r
+ indicating which address bits must match the PRMRR base register value.\r
+\r
+ @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:10;\r
+ ///\r
+ /// [Bit 10] Lock Setting this bit locks all writeable settings in this\r
+ /// register, including itself.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ ///\r
+ /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and\r
+ /// valid.\r
+ ///\r
+ UINT32 Fix_Me_2:1;\r
+ UINT32 Reserved2:20;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;\r
+\r
+/**\r
+ Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits\r
+ for the LLC and Ring.\r
+\r
+ @param ECX MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 Fix_Me_1:7;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 Fix_Me_2:7;\r
+ UINT32 Reserved2:17;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Branch Monitoring Global Control (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] EnMonitoring Global enable for branch monitoring.\r
+ ///\r
+ UINT32 EnMonitoring:1;\r
+ ///\r
+ /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold\r
+ /// trip. The branch monitoring event handler is signaled via the existing\r
+ /// PMI signaling mechanism as programmed from the corresponding local\r
+ /// APIC LVT entry.\r
+ ///\r
+ UINT32 EnExcept:1;\r
+ ///\r
+ /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause\r
+ /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a\r
+ /// triggering condition occurs and this bit is enabled.\r
+ ///\r
+ UINT32 EnLBRFrz:1;\r
+ ///\r
+ /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event\r
+ /// triggering and LBR freeze actions are disabled when operating at VMX\r
+ /// non-root operation.\r
+ ///\r
+ UINT32 DisableInGuest:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -\r
+ /// 1023 are supported. Once the Window counter reaches the WindowSize\r
+ /// count both the Window Counter and all Branch Monitoring Counters are\r
+ /// cleared.\r
+ ///\r
+ UINT32 WindowSize:10;\r
+ UINT32 Reserved2:6;\r
+ ///\r
+ /// [Bits 25:24] WindowCntSel Window event count select: '00 =\r
+ /// Instructions retired. '01 = Branch instructions retired '10 = Return\r
+ /// instructions retired. '11 = Indirect branch instructions retired.\r
+ ///\r
+ UINT32 WindowCntSel:2;\r
+ ///\r
+ /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring\r
+ /// event triggering condition is true only if all enabled counters'\r
+ /// threshold conditions are true. When '0', the threshold tripping\r
+ /// condition is true if any enabled counters' threshold is true.\r
+ ///\r
+ UINT32 CntAndMode:1;\r
+ UINT32 Reserved3:5;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;\r
+\r
+/**\r
+ Branch Monitoring Global Status (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch\r
+ /// Monitoring event signaling is blocked until this bit is cleared by\r
+ /// software.\r
+ ///\r
+ UINT32 BranchMonitoringEventSignaled:1;\r
+ ///\r
+ /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is\r
+ /// considered valid for sampling by branch monitoring software.\r
+ ///\r
+ UINT32 LBRsValid:1;\r
+ UINT32 Reserved1:6;\r
+ ///\r
+ /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This\r
+ /// status bit is sticky and once set requires clearing by software.\r
+ /// Counter operation continues independent of the state of the bit.\r
+ ///\r
+ UINT32 CntrHit0:1;\r
+ ///\r
+ /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This\r
+ /// status bit is sticky and once set requires clearing by software.\r
+ /// Counter operation continues independent of the state of the bit.\r
+ ///\r
+ UINT32 CntrHit1:1;\r
+ UINT32 Reserved2:6;\r
+ ///\r
+ /// [Bits 25:16] CountWindow The current value of the window counter. The\r
+ /// count value is frozen on a valid branch monitoring triggering\r
+ /// condition. This is a 10-bit unsigned value.\r
+ ///\r
+ UINT32 CountWindow:10;\r
+ UINT32 Reserved3:6;\r
+ ///\r
+ /// [Bits 39:32] Count0 The current value of counter 0 updated after each\r
+ /// occurrence of the event being counted. The count value is frozen on a\r
+ /// valid branch monitoring triggering condition (in which case CntrHit0\r
+ /// will also be set). This is an 8-bit signed value (2's complement).\r
+ /// Heuristic events which only increment will saturate and freeze at\r
+ /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
+ /// value 0x7F (+127) and minimum value 0x80 (-128).\r
+ ///\r
+ UINT32 Count0:8;\r
+ ///\r
+ /// [Bits 47:40] Count1 The current value of counter 1 updated after each\r
+ /// occurrence of the event being counted. The count value is frozen on a\r
+ /// valid branch monitoring triggering condition (in which case CntrHit1\r
+ /// will also be set). This is an 8-bit signed value (2's complement).\r
+ /// Heuristic events which only increment will saturate and freeze at\r
+ /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
+ /// value 0x7F (+127) and minimum value 0x80 (-128).\r
+ ///\r
+ UINT32 Count1:8;\r
+ UINT32 Reserved4:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Package C3 Residency Counter (R/O). Note: C-state values are\r
+ processor specific C-state code names, unrelated to MWAIT extension C-state\r
+ parameters or ACPI C-states.\r
+\r
+ @param ECX MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8\r
+\r
+\r
+/**\r
+ Core. Core C1 Residency Counter (R/O). Value since last reset for the Core\r
+ C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC).\r
+ This counter counts in case both of the core's threads are in an idle state\r
+ and at least one of the core's thread residency is in a C1 state or in one\r
+ of its sub states. The counter is updated only after a core C state exit.\r
+ Note: Always reads 0 if core C1 is unsupported. A value of zero indicates\r
+ that this processor does not support core C1 or never entered core C1 level\r
+ state.\r
+\r
+ @param ECX MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660\r
+\r
+\r
+/**\r
+ Core. Core C3 Residency Counter (R/O). Will always return 0.\r
+\r
+ @param ECX MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662\r
+\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number Enable Control (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_PPIN_CTL (0x0000004E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PPIN_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PPIN_CTL 0x0000004E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LockOut (R/WO) See Table 2-25.\r
+ ///\r
+ UINT32 LockOut:1;\r
+ ///\r
+ /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
+ ///\r
+ UINT32 Enable_PPIN:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PPIN_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number (R/O). Protected Processor\r
+ Inventory Number (R/O) See Table 2-25.\r
+\r
+ @param ECX MSR_SKYLAKE_PPIN (0x0000004F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PPIN 0x0000004F\r
+\r
+\r
+/**\r
+ Package. Platform Information Contains power management and other model\r
+ specific features enumeration. See http://biosbits.org.\r
+\r
+ @param ECX MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 MaximumNon_TurboRatio:8;\r
+ UINT32 Reserved2:7;\r
+ ///\r
+ /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 PPIN_CAP:1;\r
+ UINT32 Reserved3:4;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
+ /// Table 2-25.\r
+ ///\r
+ UINT32 ProgrammableRatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
+ /// Table 2-25.\r
+ ///\r
+ UINT32 ProgrammableTDPLimit:1;\r
+ ///\r
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 ProgrammableTJOFFSET:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 Reserved6:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__.\r
+\r
+ @param ECX MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power) for\r
+ /// the package. The default is set as factory-configured package Cstate\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
+ /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
+ /// supported by the processor are available.\r
+ ///\r
+ UINT32 C_StateLimit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 MWAITRedirectionEnable:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ ///\r
+ /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
+ /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
+ ///\r
+ UINT32 AutomaticC_StateConversionEnable:1;\r
+ UINT32 Reserved3:8;\r
+ ///\r
+ /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C3StateAutoDemotionEnable:1;\r
+ ///\r
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C1StateAutoDemotionEnable:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 EnableC3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 EnableC1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Package C State Demotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateDemotionEnable:1;\r
+ ///\r
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateUnDemotionEnable:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Global Machine Check Capability (R/O).\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Count.\r
+ ///\r
+ UINT32 Count:8;\r
+ ///\r
+ /// [Bit 8] MCG_CTL_P.\r
+ ///\r
+ UINT32 MCG_CTL_P:1;\r
+ ///\r
+ /// [Bit 9] MCG_EXT_P.\r
+ ///\r
+ UINT32 MCG_EXT_P:1;\r
+ ///\r
+ /// [Bit 10] MCP_CMCI_P.\r
+ ///\r
+ UINT32 MCP_CMCI_P:1;\r
+ ///\r
+ /// [Bit 11] MCG_TES_P.\r
+ ///\r
+ UINT32 MCG_TES_P:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 23:16] MCG_EXT_CNT.\r
+ ///\r
+ UINT32 MCG_EXT_CNT:8;\r
+ ///\r
+ /// [Bit 24] MCG_SER_P.\r
+ ///\r
+ UINT32 MCG_SER_P:1;\r
+ ///\r
+ /// [Bit 25] MCG_EM_P.\r
+ ///\r
+ UINT32 MCG_EM_P:1;\r
+ ///\r
+ /// [Bit 26] MCG_ELOG_P.\r
+ ///\r
+ UINT32 MCG_ELOG_P:1;\r
+ UINT32 Reserved2:5;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and a host-space interface is\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and a host-space interface is\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Temperature Target.\r
+\r
+ @param ECX MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ ///\r
+ /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
+ ///\r
+ UINT32 TCCActivationOffset:4;\r
+ UINT32 Reserved2:4;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;\r
+\r
+/**\r
+ Package. This register defines the active core ranges for each frequency\r
+ point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must\r
+ be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored.\r
+ The last valid entry must have NUMCORE >= the number of cores in the SKU. If\r
+ any of the rules above are broken, the configuration is silently rejected.\r
+\r
+ @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency\r
+ /// point.\r
+ ///\r
+ UINT32 NUMCORE_0:8;\r
+ ///\r
+ /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_1:8;\r
+ ///\r
+ /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_2:8;\r
+ ///\r
+ /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_3:8;\r
+ ///\r
+ /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_4:8;\r
+ ///\r
+ /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_5:8;\r
+ ///\r
+ /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_6:8;\r
+ ///\r
+ /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_7:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers Used in RAPL Interfaces (R/O).\r
+\r
+ @param ECX MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Package. Energy Status Units Energy related information\r
+ /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
+ /// micro-joules).\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
+ /// Interfaces.".\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
+\r
+ @param ECX MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
+ /// to enable DRAM RAPL mode 0 (Direct VR).\r
+ ///\r
+ UINT32 Energy:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
+ fields represent the widest possible range of uncore frequencies. Writing to\r
+ these fields allows software to control the minimum and the maximum\r
+ frequency that hardware will select.\r
+\r
+ @param ECX MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 MAX_RATIO:7;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 MIN_RATIO:7;\r
+ UINT32 Reserved2:17;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Reserved (R/O) Reads return 0.\r
+\r
+ @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,\r
+ ECX=0):EBX.RDT-M[bit 12] = 1.\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3\r
+ /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:\r
+ /// Local memory bandwidth monitoring. All other encoding reserved.\r
+ ///\r
+ UINT32 EventID:8;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bits 41:32] RMID (RW).\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved2:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Resource Association Register (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] RMID.\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved1:22;\r
+ ///\r
+ /// [Bits 51:32] COS (R/W).\r
+ ///\r
+ UINT32 COS:20;\r
+ UINT32 Reserved2:12;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;\r
+\r
+\r
+/**\r
+ Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,\r
+ ECX=1):EDX.COS_MAX[15:0] >=0.\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.\r
+ ///\r
+ UINT32 CBM:20;\r
+ UINT32 Reserved2:12;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;\r
+\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __XEON_5600_MSR_H__\r
+#define __XEON_5600_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel(R) Xeon(R) Processor Series 5600?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x25 || \\r
+ DisplayModel == 0x2C \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+ handler to handle unsuccessful read of this MSR.\r
+\r
+ @param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);\r
+ AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
+**/\r
+#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
+ /// MSR, the configuration of AES instruction set availability is as\r
+ /// follows: 11b: AES instructions are not available until next RESET.\r
+ /// otherwise, AES instructions are available. Note, AES instruction set\r
+ /// is not available if read is unsuccessful. If the configuration is not\r
+ /// 01b, AES instruction can be mis-configured if a privileged agent\r
+ /// unintentionally writes 11b.\r
+ ///\r
+ UINT32 AESConfiguration:2;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);\r
+ AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);\r
+ @endcode\r
+ @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
+**/\r
+#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+ @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
+ /// limit of 5 core active.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
+ /// limit of 6 core active.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. See Table 2-2.\r
+\r
+ @param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);\r
+ AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);\r
+ @endcode\r
+ @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
+**/\r
+#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel(R) Xeon(R) Processor D product Family.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __XEON_D_MSR_H__\r
+#define __XEON_D_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel(R) Xeon(R) Processor D product Family?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x4F || \\r
+ DisplayModel == 0x56 \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number Enable Control (R/W).\r
+\r
+ @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_PPIN_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);\r
+ AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
+**/\r
+#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LockOut (R/WO) See Table 2-25.\r
+ ///\r
+ UINT32 LockOut:1;\r
+ ///\r
+ /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
+ ///\r
+ UINT32 Enable_PPIN:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_PPIN_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number (R/O). Protected Processor\r
+ Inventory Number (R/O) See Table 2-25.\r
+\r
+ @param ECX MSR_XEON_D_PPIN (0x0000004F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);\r
+ @endcode\r
+ @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.\r
+**/\r
+#define MSR_XEON_D_PPIN 0x0000004F\r
+\r
+\r
+/**\r
+ Package. See http://biosbits.org.\r
+\r
+ @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
+**/\r
+#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 MaximumNonTurboRatio:8;\r
+ UINT32 Reserved2:7;\r
+ ///\r
+ /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 PPIN_CAP:1;\r
+ UINT32 Reserved3:4;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
+ /// Table 2-25.\r
+ ///\r
+ UINT32 RatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
+ /// Table 2-25.\r
+ ///\r
+ UINT32 TDPLimit:1;\r
+ ///\r
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 TJOFFSET:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 Reserved6:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
+\r
+ @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
+**/\r
+#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power) for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
+ /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
+ /// supported by the processor are available.\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ ///\r
+ /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
+ /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
+ ///\r
+ UINT32 CStateConversion:1;\r
+ UINT32 Reserved3:8;\r
+ ///\r
+ /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C3AutoDemotion:1;\r
+ ///\r
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C1AutoDemotion:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Package C State Demotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateDemotion:1;\r
+ ///\r
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateUndemotion:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Global Machine Check Capability (R/O).\r
+\r
+ @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);\r
+ @endcode\r
+ @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
+**/\r
+#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Count.\r
+ ///\r
+ UINT32 Count:8;\r
+ ///\r
+ /// [Bit 8] MCG_CTL_P.\r
+ ///\r
+ UINT32 MCG_CTL_P:1;\r
+ ///\r
+ /// [Bit 9] MCG_EXT_P.\r
+ ///\r
+ UINT32 MCG_EXT_P:1;\r
+ ///\r
+ /// [Bit 10] MCP_CMCI_P.\r
+ ///\r
+ UINT32 MCP_CMCI_P:1;\r
+ ///\r
+ /// [Bit 11] MCG_TES_P.\r
+ ///\r
+ UINT32 MCG_TES_P:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 23:16] MCG_EXT_CNT.\r
+ ///\r
+ UINT32 MCG_EXT_CNT:8;\r
+ ///\r
+ /// [Bit 24] MCG_SER_P.\r
+ ///\r
+ UINT32 MCG_SER_P:1;\r
+ ///\r
+ /// [Bit 25] MCG_EM_P.\r
+ ///\r
+ UINT32 MCG_EM_P:1;\r
+ ///\r
+ /// [Bit 26] MCG_ELOG_P.\r
+ ///\r
+ UINT32 MCG_ELOG_P:1;\r
+ UINT32 Reserved2:5;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_IA32_MCG_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
+**/\r
+#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
+**/\r
+#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ ///\r
+ /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
+ ///\r
+ UINT32 TCCActivationOffset:4;\r
+ UINT32 Reserved2:4;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+ @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.\r
+ ///\r
+ UINT32 Maximum7C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.\r
+ ///\r
+ UINT32 Maximum8C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);\r
+ @endcode\r
+ @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
+**/\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.\r
+ ///\r
+ UINT32 Maximum9C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.\r
+ ///\r
+ UINT32 Maximum10C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.\r
+ ///\r
+ UINT32 Maximum11C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.\r
+ ///\r
+ UINT32 Maximum12C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.\r
+ ///\r
+ UINT32 Maximum13C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.\r
+ ///\r
+ UINT32 Maximum14C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.\r
+ ///\r
+ UINT32 Maximum15C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.\r
+ ///\r
+ UINT32 Maximum16C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
+\r
+ @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);\r
+ @endcode\r
+ @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
+**/\r
+#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Package. Energy Status Units Energy related information\r
+ /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
+ /// micro-joules).\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
+ /// Interfaces.".\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
+\r
+ @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
+ /// to enable DRAM RAPL mode 0 (Direct VR).\r
+ ///\r
+ UINT32 Energy:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+ @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
+**/\r
+#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
+ fields represent the widest possible range of uncore frequencies. Writing to\r
+ these fields allows software to control the minimum and the maximum\r
+ frequency that hardware will select.\r
+\r
+ @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 MAX_RATIO:7;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 MIN_RATIO:7;\r
+ UINT32 Reserved2:17;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
+\r
+/**\r
+ Package. Reserved (R/O) Reads return 0.\r
+\r
+ @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
+ refers to processor core frequency).\r
+\r
+ @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
+**/\r
+#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
+ /// reduced below the operating system request due to assertion of\r
+ /// external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to a thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ ///\r
+ /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to PBM limit.\r
+ ///\r
+ UINT32 PowerBudgetManagementStatus:1;\r
+ ///\r
+ /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to PCS\r
+ /// limit.\r
+ ///\r
+ UINT32 PlatformConfigurationServicesStatus:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
+ /// When set, frequency is reduced below the operating system request\r
+ /// because the processor has detected that utilization is low.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to a thermal alert from the\r
+ /// Voltage Regulator.\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to electrical design\r
+ /// point constraints (e.g. maximum electrical current consumption).\r
+ ///\r
+ UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to Multi-Core Turbo limits.\r
+ ///\r
+ UINT32 MultiCoreTurboStatus:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
+ /// below max non-turbo P1.\r
+ ///\r
+ UINT32 FrequencyP1Status:1;\r
+ ///\r
+ /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
+ /// set, frequency is reduced below max n-core turbo frequency.\r
+ ///\r
+ UINT32 TurboFrequencyLimitingStatus:1;\r
+ ///\r
+ /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
+ /// reduced below the operating system request.\r
+ ///\r
+ UINT32 FrequencyLimitingStatus:1;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ ///\r
+ /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PowerBudgetManagementLog:1;\r
+ ///\r
+ /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
+ /// the PCS Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PlatformConfigurationServicesLog:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
+ /// indicates that the AUBFC Status bit has asserted since the log bit was\r
+ /// last cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ ///\r
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 Reserved7:1;\r
+ ///\r
+ /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
+ /// Turbo Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 MultiCoreTurboLog:1;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
+ /// Frequency P1 Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CoreFrequencyP1Log:1;\r
+ ///\r
+ /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
+ /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 TurboFrequencyLimitingLog:1;\r
+ ///\r
+ /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
+ /// Frequency Limiting Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CoreFrequencyLimitingLog:1;\r
+ UINT32 Reserved9:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
+ ECX=0):EBX.RDT-M[bit 12] = 1.\r
+\r
+ @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);\r
+ AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
+**/\r
+#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3\r
+ /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:\r
+ /// Local memory bandwidth monitoring All other encoding reserved.\r
+ ///\r
+ UINT32 EventID:8;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bits 41:32] RMID (RW).\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved2:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Resource Association Register (R/W).\r
+\r
+ @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);\r
+ AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
+**/\r
+#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] RMID.\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved1:22;\r
+ ///\r
+ /// [Bits 51:32] COS (R/W).\r
+ ///\r
+ UINT32 COS:20;\r
+ UINT32 Reserved2:12;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;\r
+\r
+\r
+/**\r
+ Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
+ ECX=1):EDX.COS_MAX[15:0] >= n.\r
+\r
+ @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);\r
+ AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM.\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.\r
+ @{\r
+**/\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0\r
+ to #MSR_XEON_D_IA32_L3_QOS_MASK_15.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.\r
+ ///\r
+ UINT32 CBM:20;\r
+ UINT32 Reserved2:12;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);\r
+ @endcode\r
+ @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.\r
+**/\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:31;\r
+ ///\r
+ /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
+ /// the processor uses override configuration specified in\r
+ /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
+ /// uses factory-set configuration (Default).\r
+ ///\r
+ UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Cache Allocation Technology Configuration (R/W).\r
+\r
+ @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);\r
+ AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
+**/\r
+#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.\r
+ ///\r
+ UINT32 CAT:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __XEON_E7_MSR_H__\r
+#define __XEON_E7_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel(R) Xeon(R) Processor E7 Family?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x2F \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+ handler to handle unsuccessful read of this MSR.\r
+\r
+ @param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);\r
+ AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
+**/\r
+#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
+ /// MSR, the configuration of AES instruction set availability is as\r
+ /// follows: 11b: AES instructions are not available until next RESET.\r
+ /// otherwise, AES instructions are available. Note, AES instruction set\r
+ /// is not available if read is unsuccessful. If the configuration is not\r
+ /// 01b, AES instruction can be mis-configured if a privileged agent\r
+ /// unintentionally writes 11b.\r
+ ///\r
+ UINT32 AESConfiguration:2;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);\r
+ AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
+**/\r
+#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7\r
+\r
+\r
+/**\r
+ Package. Reserved Attempt to read/write will cause #UD.\r
+\r
+ @param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select MSR.\r
+\r
+ @param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.\r
+ MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.\r
+ MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.\r
+ MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.\r
+ MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.\r
+ MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r
+ @{\r
+**/\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter MSR.\r
+\r
+ @param ECX MSR_XEON_E7_C8_PMON_CTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
+ MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
+ MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
+ MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
+ MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.\r
+ MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r
+ @{\r
+**/\r
+#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51\r
+#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53\r
+#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55\r
+#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57\r
+#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59\r
+#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon local box control MSR.\r
+\r
+ @param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r
+ AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r
+**/\r
+#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon local box status MSR.\r
+\r
+ @param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon local box overflow control MSR.\r
+\r
+ @param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r
+**/\r
+#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select MSR.\r
+\r
+ @param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r
+ AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.\r
+ MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.\r
+ MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.\r
+ MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.\r
+ MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.\r
+ MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r
+ @{\r
+**/\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter MSR.\r
+\r
+ @param ECX MSR_XEON_E7_C9_PMON_CTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r
+ @endcode\r
+ @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
+ MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
+ MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
+ MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
+ MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.\r
+ MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r
+ @{\r
+**/\r
+#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1\r
+#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3\r
+#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5\r
+#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7\r
+#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9\r
+#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB\r
+/// @}\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
+ May 2018, Volume 4: Model-Specific-Registers (MSR)\r
+\r
+**/\r
+\r
+#ifndef __XEON_PHI_MSR_H__\r
+#define __XEON_PHI_MSR_H__\r
+\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Is Intel(R) Xeon(R) Phi(TM) processor Family?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x57 || \\r
+ DisplayModel == 0x85 \\r
+ ) \\r
+ )\r
+\r
+/**\r
+ Thread. SMI Counter (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);\r
+ @endcode\r
+ @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
+**/\r
+#define MSR_XEON_PHI_SMI_COUNT 0x00000034\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] SMI Count (R/O).\r
+ ///\r
+ UINT32 SMICount:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_SMI_COUNT_REGISTER;\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number Enable Control (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PPIN_CTL 0x0000004E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to\r
+ /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if\r
+ /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an\r
+ /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a\r
+ /// privileged inventory initialization agent to access MSR_PPIN. After\r
+ /// reading MSR_PPIN, the privileged inventory initialization agent should\r
+ /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
+ /// prevent unauthorized modification to MSR_PPIN_CTL.\r
+ ///\r
+ UINT32 LockOut:1;\r
+ ///\r
+ /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
+ /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]\r
+ /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.\r
+ /// Default is 0.\r
+ ///\r
+ UINT32 Enable_PPIN:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_PPIN_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number (R/O). Protected Processor\r
+ Inventory Number (R/O) A unique value within a given CPUID\r
+ family/model/stepping signature that a privileged inventory initialization\r
+ agent can access to identify each physical processor, when access to\r
+ MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r
+ MSR_PPIN_CTL[bits 1:0] = '10b'.\r
+\r
+ @param ECX MSR_XEON_PHI_PPIN (0x0000004F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_PPIN 0x0000004F\r
+\r
+/**\r
+ Package. Platform Information Contains power management and other model\r
+ specific features enumeration. See http://biosbits.org.\r
+\r
+ @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
+ /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
+ /// MHz.\r
+ ///\r
+ UINT32 MaximumNonTurboRatio:8;\r
+ UINT32 Reserved2:12;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
+ /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
+ /// Turbo mode is disabled.\r
+ ///\r
+ UINT32 RatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
+ /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
+ /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
+ /// programmable.\r
+ ///\r
+ UINT32 TDPLimit:1;\r
+ UINT32 Reserved3:2;\r
+ UINT32 Reserved4:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
+ /// minimum ratio (maximum efficiency) that the processor can operates, in\r
+ /// units of 100MHz.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 Reserved5:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Module. C-State Configuration Control (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code\r
+ /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No\r
+ /// Retention 011b: C6 Retention 111b: No limit.\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved5:10;\r
+ ///\r
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor\r
+ /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
+ /// auto-demote information.\r
+ ///\r
+ UINT32 C1StateAutoDemotionEnable:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables\r
+ /// Undemotion from Demoted C1.\r
+ ///\r
+ UINT32 C1StateAutoUndemotionEnable:1;\r
+ ///\r
+ /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables\r
+ /// Package C state demotion.\r
+ ///\r
+ UINT32 PKGC_StateAutoDemotionEnable:1;\r
+ UINT32 Reserved7:2;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Module. Power Management IO Redirection in C-state (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] LVL_2 Base Address (R/W).\r
+ ///\r
+ UINT32 Lvl2Base:16;\r
+ ///\r
+ /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which\r
+ /// IO-redirection will be executed (0-127). Should be programmed based on\r
+ /// the number of LVLx registers existing in the chipset.\r
+ ///\r
+ UINT32 CStateRange:7;\r
+ UINT32 Reserved3:9;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+ handler to handle unsuccessful read of this MSR.\r
+\r
+ @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
+**/\r
+#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
+ /// MSR, the configuration of AES instruction set availability is as\r
+ /// follows: 11b: AES instructions are not available until next RESET.\r
+ /// otherwise, AES instructions are available. Note, AES instruction set\r
+ /// is not available if read is unsuccessful. If the configuration is not\r
+ /// 01b, AES instruction can be mis-configured if a privileged agent\r
+ /// unintentionally writes 11b.\r
+ ///\r
+ UINT32 AESConfiguration:2;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. MISC_FEATURE_ENABLES.\r
+\r
+ @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and\r
+ /// MWAIT instructions do not cause invalid-opcode exceptions when\r
+ /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed\r
+ /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state\r
+ /// other than C0 or C1, the instruction operates as if EAX indicated the\r
+ /// C-state C1.\r
+ ///\r
+ UINT32 UserModeMonitorAndMwait:1;\r
+ UINT32 Reserved2:30;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;\r
+\r
+/**\r
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
+**/\r
+#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is\r
+ /// set, that bank supports Enhanced MCA (Default all 0; does not support\r
+ /// EMCA).\r
+ ///\r
+ UINT32 BankSupport:32;\r
+ UINT32 Reserved4:24;\r
+ ///\r
+ /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.\r
+ ///\r
+ UINT32 TargetedSMI:1;\r
+ ///\r
+ /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature\r
+ /// is supported.\r
+ ///\r
+ UINT32 SMM_CPU_SVRSTR:1;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
+**/\r
+#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fast-Strings Enable.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value\r
+ /// is 1.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Performance Monitoring Available (R).\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 11] Branch Trace Storage Unavailable (RO).\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Processor Event Based Sampling Unavailable (RO).\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved4:3;\r
+ ///\r
+ /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 18] ENABLE MONITOR FSM (R/W).\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ UINT32 Reserved6:3;\r
+ ///\r
+ /// [Bit 22] Limit CPUID Maxval (R/W).\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] xTPR Message Disable (R/W).\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved7:8;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 34] XD Bit Disable (R/W).\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved9:3;\r
+ ///\r
+ /// [Bit 38] Turbo Mode Disable (R/W).\r
+ ///\r
+ UINT32 TurboModeDisable:1;\r
+ UINT32 Reserved10:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
+**/\r
+#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (R).\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ ///\r
+ /// [Bits 29:24] Target Offset (R/W).\r
+ ///\r
+ UINT32 TargetOffset:6;\r
+ UINT32 Reserved2:2;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r
+\r
+\r
+/**\r
+ Miscellaneous Feature Control (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
+**/\r
+#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L1 data cache prefetcher.\r
+ ///\r
+ UINT32 DCUHardwarePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
+ /// L2 hardware prefetcher.\r
+ ///\r
+ UINT32 L2HardwarePrefetcherDisable:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
+**/\r
+#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r
+\r
+\r
+/**\r
+ Shared. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
+**/\r
+#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).\r
+\r
+ @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
+**/\r
+#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved:1;\r
+ ///\r
+ /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active\r
+ /// processor cores which operates under the maximum ratio limit for group\r
+ /// 0.\r
+ ///\r
+ UINT32 MaxCoresGroup0:7;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo\r
+ /// ratio limit when the number of active cores are not more than the\r
+ /// group 0 maximum core count.\r
+ ///\r
+ UINT32 MaxRatioLimitGroup0:8;\r
+ ///\r
+ /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1\r
+ /// Group 1, which includes the specified number of additional cores plus\r
+ /// the cores in group 0, operates under the group 1 turbo max ratio limit\r
+ /// = "group 0 Max ratio limit" - "group ratio delta for group 1".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup1:5;\r
+ ///\r
+ /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// to Group 0.\r
+ ///\r
+ UINT32 DeltaRatioGroup1:3;\r
+ ///\r
+ /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2\r
+ /// Group 2, which includes the specified number of additional cores plus\r
+ /// all the cores in group 1, operates under the group 2 turbo max ratio\r
+ /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup2:5;\r
+ ///\r
+ /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// for Group 1.\r
+ ///\r
+ UINT32 DeltaRatioGroup2:3;\r
+ ///\r
+ /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3\r
+ /// Group 3, which includes the specified number of additional cores plus\r
+ /// all the cores in group 2, operates under the group 3 turbo max ratio\r
+ /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup3:5;\r
+ ///\r
+ /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// for Group 2.\r
+ ///\r
+ UINT32 DeltaRatioGroup3:3;\r
+ ///\r
+ /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4\r
+ /// Group 4, which includes the specified number of additional cores plus\r
+ /// all the cores in group 3, operates under the group 4 turbo max ratio\r
+ /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup4:5;\r
+ ///\r
+ /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// for Group 3.\r
+ ///\r
+ UINT32 DeltaRatioGroup4:3;\r
+ ///\r
+ /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5\r
+ /// Group 5, which includes the specified number of additional cores plus\r
+ /// all the cores in group 4, operates under the group 5 turbo max ratio\r
+ /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup5:5;\r
+ ///\r
+ /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// for Group 4.\r
+ ///\r
+ UINT32 DeltaRatioGroup5:3;\r
+ ///\r
+ /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6\r
+ /// Group 6, which includes the specified number of additional cores plus\r
+ /// all the cores in group 5, operates under the group 6 turbo max ratio\r
+ /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".\r
+ ///\r
+ UINT32 MaxIncrementalCoresGroup6:5;\r
+ ///\r
+ /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned\r
+ /// integer specifying the ratio decrement relative to the Max ratio limit\r
+ /// for Group 5.\r
+ ///\r
+ UINT32 DeltaRatioGroup6:3;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Last Branch Record Filtering Select Register (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
+**/\r
+#define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r
+\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] CPL_EQ_0.\r
+ ///\r
+ UINT32 CPL_EQ_0:1;\r
+ ///\r
+ /// [Bit 1] CPL_NEQ_0.\r
+ ///\r
+ UINT32 CPL_NEQ_0:1;\r
+ ///\r
+ /// [Bit 2] JCC.\r
+ ///\r
+ UINT32 JCC:1;\r
+ ///\r
+ /// [Bit 3] NEAR_REL_CALL.\r
+ ///\r
+ UINT32 NEAR_REL_CALL:1;\r
+ ///\r
+ /// [Bit 4] NEAR_IND_CALL.\r
+ ///\r
+ UINT32 NEAR_IND_CALL:1;\r
+ ///\r
+ /// [Bit 5] NEAR_RET.\r
+ ///\r
+ UINT32 NEAR_RET:1;\r
+ ///\r
+ /// [Bit 6] NEAR_IND_JMP.\r
+ ///\r
+ UINT32 NEAR_IND_JMP:1;\r
+ ///\r
+ /// [Bit 7] NEAR_REL_JMP.\r
+ ///\r
+ UINT32 NEAR_REL_JMP:1;\r
+ ///\r
+ /// [Bit 8] FAR_BRANCH.\r
+ ///\r
+ UINT32 FAR_BRANCH:1;\r
+ UINT32 Reserved1:23;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_LBR_SELECT_REGISTER;\r
+\r
+/**\r
+ Thread. Last Branch Record Stack TOS (R/W).\r
+\r
+ @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
+**/\r
+#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Thread. Last Exception Record From Linear IP (R).\r
+\r
+ @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);\r
+ @endcode\r
+ @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
+**/\r
+#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Thread. Last Exception Record To Linear IP (R).\r
+\r
+ @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);\r
+ @endcode\r
+ @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
+**/\r
+#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r
+\r
+\r
+/**\r
+ Thread. See Table 2-2.\r
+\r
+ @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3\r
+ Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r
+\r
+\r
+/**\r
+ Package. Package C6 Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r
+\r
+\r
+/**\r
+ Package. Package C7 Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r
+\r
+\r
+/**\r
+ Module. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0\r
+ Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.\r
+**/\r
+#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r
+\r
+\r
+/**\r
+ Module. Module C6 Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6\r
+ Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
+**/\r
+#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r
+\r
+\r
+/**\r
+ Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
+\r
+ @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);\r
+ @endcode\r
+ @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
+**/\r
+#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
+\r
+\r
+/**\r
+ Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r
+ 2-2.\r
+\r
+ @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);\r
+ @endcode\r
+ @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
+**/\r
+#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);\r
+ @endcode\r
+ @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
+**/\r
+#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Package. Energy Status Units Energy related information\r
+ /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
+ /// micro-joules).\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
+ /// Interfaces.".\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2\r
+ Residency Counter. (R/O).\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r
+\r
+\r
+/**\r
+ Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r
+\r
+\r
+/**\r
+ Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);\r
+ @endcode\r
+ @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
+**/\r
+#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
+ fields represent the widest possible range of uncore frequencies. Writing to\r
+ these fields allows software to control the minimum and the maximum\r
+ frequency that hardware will select.\r
+\r
+ @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 MAX_RATIO:7;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 MIN_RATIO:7;\r
+ UINT32 Reserved2:17;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
+ RAPL Domains.".\r
+\r
+ @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r
+\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains.".\r
+\r
+ @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);\r
+ @endcode\r
+ @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Package. Base TDP Ratio (R/O) See Table 2-24.\r
+\r
+ @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);\r
+ @endcode\r
+ @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
+**/\r
+#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.\r
+\r
+ @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);\r
+ @endcode\r
+ @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
+**/\r
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.\r
+\r
+ @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);\r
+ @endcode\r
+ @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
+**/\r
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Control (R/W) See Table 2-24.\r
+\r
+ @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
+**/\r
+#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r
+\r
+\r
+/**\r
+ Package. ConfigTDP Control (R/W) See Table 2-24.\r
+\r
+ @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);\r
+ @endcode\r
+ @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
+**/\r
+#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
+ refers to processor core frequency).\r
+\r
+ @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+ @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
+**/\r
+#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0).\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0).\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0).\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 8] Electrical Design Point Status (R0).\r
+ ///\r
+ UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 Reserved3:23;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+SMRAM Save State Map Definitions.\r
+\r
+SMRAM Save State Map definitions based on contents of the\r
+Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+ Volume 3C, Section 34.4 SMRAM\r
+ Volume 3C, Section 34.5 SMI Handler Execution Environment\r
+ Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs\r
+\r
+Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef __INTEL_SMRAM_SAVE_STATE_MAP_H__\r
+#define __INTEL_SMRAM_SAVE_STATE_MAP_H__\r
+\r
+///\r
+/// Default SMBASE address\r
+///\r
+#define SMM_DEFAULT_SMBASE 0x30000\r
+\r
+///\r
+/// Offset of SMM handler from SMBASE\r
+///\r
+#define SMM_HANDLER_OFFSET 0x8000\r
+\r
+///\r
+/// Offset of SMRAM Save State Map from SMBASE\r
+///\r
+#define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00\r
+\r
+#pragma pack (1)\r
+\r
+///\r
+/// 32-bit SMRAM Save State Map\r
+///\r
+typedef struct {\r
+ UINT8 Reserved[0x200]; // 7c00h\r
+ // Padded an extra 0x200 bytes so 32-bit and 64-bit\r
+ // SMRAM Save State Maps are the same size\r
+ UINT8 Reserved1[0xf8]; // 7e00h\r
+ UINT32 SMBASE; // 7ef8h\r
+ UINT32 SMMRevId; // 7efch\r
+ UINT16 IORestart; // 7f00h\r
+ UINT16 AutoHALTRestart; // 7f02h\r
+ UINT8 Reserved2[0x9C]; // 7f08h\r
+ UINT32 IOMemAddr; // 7fa0h\r
+ UINT32 IOMisc; // 7fa4h\r
+ UINT32 _ES; // 7fa8h\r
+ UINT32 _CS; // 7fach\r
+ UINT32 _SS; // 7fb0h\r
+ UINT32 _DS; // 7fb4h\r
+ UINT32 _FS; // 7fb8h\r
+ UINT32 _GS; // 7fbch\r
+ UINT32 Reserved3; // 7fc0h\r
+ UINT32 _TR; // 7fc4h\r
+ UINT32 _DR7; // 7fc8h\r
+ UINT32 _DR6; // 7fcch\r
+ UINT32 _EAX; // 7fd0h\r
+ UINT32 _ECX; // 7fd4h\r
+ UINT32 _EDX; // 7fd8h\r
+ UINT32 _EBX; // 7fdch\r
+ UINT32 _ESP; // 7fe0h\r
+ UINT32 _EBP; // 7fe4h\r
+ UINT32 _ESI; // 7fe8h\r
+ UINT32 _EDI; // 7fech\r
+ UINT32 _EIP; // 7ff0h\r
+ UINT32 _EFLAGS; // 7ff4h\r
+ UINT32 _CR3; // 7ff8h\r
+ UINT32 _CR0; // 7ffch\r
+} SMRAM_SAVE_STATE_MAP32;\r
+\r
+///\r
+/// 64-bit SMRAM Save State Map\r
+///\r
+typedef struct {\r
+ UINT8 Reserved1[0x1d0]; // 7c00h\r
+ UINT32 GdtBaseHiDword; // 7dd0h\r
+ UINT32 LdtBaseHiDword; // 7dd4h\r
+ UINT32 IdtBaseHiDword; // 7dd8h\r
+ UINT8 Reserved2[0xc]; // 7ddch\r
+ UINT64 IO_EIP; // 7de8h\r
+ UINT8 Reserved3[0x50]; // 7df0h\r
+ UINT32 _CR4; // 7e40h\r
+ UINT8 Reserved4[0x48]; // 7e44h\r
+ UINT32 GdtBaseLoDword; // 7e8ch\r
+ UINT32 Reserved5; // 7e90h\r
+ UINT32 IdtBaseLoDword; // 7e94h\r
+ UINT32 Reserved6; // 7e98h\r
+ UINT32 LdtBaseLoDword; // 7e9ch\r
+ UINT8 Reserved7[0x38]; // 7ea0h\r
+ UINT64 EptVmxControl; // 7ed8h\r
+ UINT32 EnEptVmxControl; // 7ee0h\r
+ UINT8 Reserved8[0x14]; // 7ee4h\r
+ UINT32 SMBASE; // 7ef8h\r
+ UINT32 SMMRevId; // 7efch\r
+ UINT16 IORestart; // 7f00h\r
+ UINT16 AutoHALTRestart; // 7f02h\r
+ UINT8 Reserved9[0x18]; // 7f04h\r
+ UINT64 _R15; // 7f1ch\r
+ UINT64 _R14;\r
+ UINT64 _R13;\r
+ UINT64 _R12;\r
+ UINT64 _R11;\r
+ UINT64 _R10;\r
+ UINT64 _R9;\r
+ UINT64 _R8;\r
+ UINT64 _RAX; // 7f5ch\r
+ UINT64 _RCX;\r
+ UINT64 _RDX;\r
+ UINT64 _RBX;\r
+ UINT64 _RSP;\r
+ UINT64 _RBP;\r
+ UINT64 _RSI;\r
+ UINT64 _RDI;\r
+ UINT64 IOMemAddr; // 7f9ch\r
+ UINT32 IOMisc; // 7fa4h\r
+ UINT32 _ES; // 7fa8h\r
+ UINT32 _CS;\r
+ UINT32 _SS;\r
+ UINT32 _DS;\r
+ UINT32 _FS;\r
+ UINT32 _GS;\r
+ UINT32 _LDTR; // 7fc0h\r
+ UINT32 _TR;\r
+ UINT64 _DR7; // 7fc8h\r
+ UINT64 _DR6;\r
+ UINT64 _RIP; // 7fd8h\r
+ UINT64 IA32_EFER; // 7fe0h\r
+ UINT64 _RFLAGS; // 7fe8h\r
+ UINT64 _CR3; // 7ff0h\r
+ UINT64 _CR0; // 7ff8h\r
+} SMRAM_SAVE_STATE_MAP64;\r
+\r
+///\r
+/// Union of 32-bit and 64-bit SMRAM Save State Maps\r
+///\r
+typedef union {\r
+ SMRAM_SAVE_STATE_MAP32 x86;\r
+ SMRAM_SAVE_STATE_MAP64 x64;\r
+} SMRAM_SAVE_STATE_MAP;\r
+\r
+///\r
+/// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map\r
+///\r
+#define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC 0x30004\r
+\r
+///\r
+/// SMRAM Save State Map IOMisc I/O Length Values\r
+///\r
+#define SMM_IO_LENGTH_BYTE 0x01\r
+#define SMM_IO_LENGTH_WORD 0x02\r
+#define SMM_IO_LENGTH_DWORD 0x04\r
+\r
+///\r
+/// SMRAM Save State Map IOMisc I/O Instruction Type Values\r
+///\r
+#define SMM_IO_TYPE_IN_IMMEDIATE 0x9\r
+#define SMM_IO_TYPE_IN_DX 0x1\r
+#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8\r
+#define SMM_IO_TYPE_OUT_DX 0x0\r
+#define SMM_IO_TYPE_INS 0x3\r
+#define SMM_IO_TYPE_OUTS 0x2\r
+#define SMM_IO_TYPE_REP_INS 0x7\r
+#define SMM_IO_TYPE_REP_OUTS 0x6\r
+\r
+///\r
+/// SMRAM Save State Map IOMisc structure\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT32 SmiFlag:1;\r
+ UINT32 Length:3;\r
+ UINT32 Type:4;\r
+ UINT32 Reserved1:8;\r
+ UINT32 Port:16;\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} SMRAM_SAVE_STATE_IOMISC;\r
+\r
+#pragma pack ()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ STM API definition\r
+\r
+ Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ SMI Transfer Monitor (STM) User Guide Revision 1.00\r
+\r
+**/\r
+\r
+#ifndef _INTEL_STM_API_H_\r
+#define _INTEL_STM_API_H_\r
+\r
+#include <Register/Intel/StmStatusCode.h>\r
+#include <Register/Intel/StmResourceDescriptor.h>\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
+\r
+#pragma pack (1)\r
+\r
+/**\r
+ STM Header Structures\r
+**/\r
+\r
+typedef struct {\r
+ UINT32 Intel64ModeSupported :1; ///> bitfield\r
+ UINT32 EptSupported :1; ///> bitfield\r
+ UINT32 Reserved :30; ///> must be 0\r
+} STM_FEAT;\r
+\r
+#define STM_SPEC_VERSION_MAJOR 1\r
+#define STM_SPEC_VERSION_MINOR 0\r
+\r
+typedef struct {\r
+ UINT8 StmSpecVerMajor;\r
+ UINT8 StmSpecVerMinor;\r
+ ///\r
+ /// Must be zero\r
+ ///\r
+ UINT16 Reserved;\r
+ UINT32 StaticImageSize;\r
+ UINT32 PerProcDynamicMemorySize;\r
+ UINT32 AdditionalDynamicMemorySize;\r
+ STM_FEAT StmFeatures;\r
+ UINT32 NumberOfRevIDs;\r
+ UINT32 StmSmmRevID[1];\r
+ ///\r
+ /// The total STM_HEADER should be 4K.\r
+ ///\r
+} SOFTWARE_STM_HEADER;\r
+\r
+typedef struct {\r
+ MSEG_HEADER HwStmHdr;\r
+ SOFTWARE_STM_HEADER SwStmHdr;\r
+} STM_HEADER;\r
+\r
+\r
+/**\r
+ VMCALL API Numbers\r
+ API number convention: BIOS facing VMCALL interfaces have bit 16 clear\r
+**/\r
+\r
+/**\r
+ StmMapAddressRange enables a SMM guest to create a non-1:1 virtual to\r
+ physical mapping of an address range into the SMM guest's virtual\r
+ memory space.\r
+\r
+ @param EAX #STM_API_MAP_ADDRESS_RANGE (0x00000001)\r
+ @param EBX Low 32 bits of physical address of caller allocated\r
+ STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure.\r
+ @param ECX High 32 bits of physical address of caller allocated\r
+ STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is\r
+ clear (0), ECX must be 0.\r
+\r
+ @note All fields of STM_MAP_ADDRESS_RANGE_DESCRIPTOR are inputs only. They\r
+ are not modified by StmMapAddressRange.\r
+\r
+ @retval CF 0\r
+ No error, EAX set to STM_SUCCESS.\r
+ The memory range was mapped as requested.\r
+ @retval CF 1\r
+ An error occurred, EAX holds relevant error value.\r
+ @retval EAX #ERROR_STM_SECURITY_VIOLATION\r
+ The requested mapping contains a protected resource.\r
+ @retval EAX #ERROR_STM_CACHE_TYPE_NOT_SUPPORTED\r
+ The requested cache type could not be satisfied.\r
+ @retval EAX #ERROR_STM_PAGE_NOT_FOUND\r
+ Page count must not be zero.\r
+ @retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED\r
+ STM supports EPT and has not implemented StmMapAddressRange().\r
+ @retval EAX #ERROR_STM_UNSPECIFIED\r
+ An unspecified error occurred.\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_MAP_ADDRESS_RANGE 0x00000001\r
+\r
+/**\r
+ STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL\r
+**/\r
+typedef struct {\r
+ UINT64 PhysicalAddress;\r
+ UINT64 VirtualAddress;\r
+ UINT32 PageCount;\r
+ UINT32 PatCacheType;\r
+} STM_MAP_ADDRESS_RANGE_DESCRIPTOR;\r
+\r
+/**\r
+ Define values for PatCacheType field of #STM_MAP_ADDRESS_RANGE_DESCRIPTOR\r
+ @{\r
+**/\r
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_ST_UC 0x00\r
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WC 0x01\r
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WT 0x04\r
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WP 0x05\r
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WB 0x06\r
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_UC 0x07\r
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_FOLLOW_MTRR 0xFFFFFFFF\r
+/// @}\r
+\r
+/**\r
+ StmUnmapAddressRange enables a SMM guest to remove mappings from its page\r
+ table.\r
+\r
+ If TXT_PROCESSOR_SMM_DESCRIPTOR.EptEnabled bit is set by the STM, BIOS can\r
+ control its own page tables. In this case, the STM implementation may\r
+ optionally return ERROR_STM_FUNCTION_NOT_SUPPORTED.\r
+\r
+ @param EAX #STM_API_UNMAP_ADDRESS_RANGE (0x00000002)\r
+ @param EBX Low 32 bits of virtual address of caller allocated\r
+ STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure.\r
+ @param ECX High 32 bits of virtual address of caller allocated\r
+ STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is\r
+ clear (0), ECX must be zero.\r
+\r
+ @retval CF 0\r
+ No error, EAX set to STM_SUCCESS. The memory range was unmapped\r
+ as requested.\r
+ @retval CF 1\r
+ An error occurred, EAX holds relevant error value.\r
+ @retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED\r
+ STM supports EPT and has not implemented StmUnmapAddressRange().\r
+ @retval EAX #ERROR_STM_UNSPECIFIED\r
+ An unspecified error occurred.\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002\r
+\r
+/**\r
+ STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL\r
+**/\r
+typedef struct {\r
+ UINT64 VirtualAddress;\r
+ UINT32 Length;\r
+} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;\r
+\r
+\r
+/**\r
+ Since the normal OS environment runs with a different set of page tables than\r
+ the SMM guest, virtual mappings will certainly be different. In order to do a\r
+ guest virtual to host physical translation of an address from the normal OS\r
+ code (EIP for example), it is necessary to walk the page tables governing the\r
+ OS page mappings. Since the SMM guest has no direct access to the page tables,\r
+ it must ask the STM to do this page table walk. This is supported via the\r
+ StmAddressLookup VMCALL. All OS page table formats need to be supported,\r
+ (e.g. PAE, PSE, Intel64, EPT, etc.)\r
+\r
+ StmAddressLookup takes a CR3 value and a virtual address from the interrupted\r
+ code as input and returns the corresponding physical address. It also\r
+ optionally maps the physical address into the SMM guest's virtual address\r
+ space. This new mapping persists ONLY for the duration of the SMI and if\r
+ needed in subsequent SMIs it must be remapped. PAT cache types follow the\r
+ interrupted environment's page table.\r
+\r
+ If EPT is enabled, OS CR3 only provides guest physical address information,\r
+ but the SMM guest might also need to know the host physical address. Since\r
+ SMM does not have direct access rights to EPT (it is protected by the STM),\r
+ SMM can input InterruptedEptp to let STM help to walk through it, and output\r
+ the host physical address.\r
+\r
+ @param EAX #STM_API_ADDRESS_LOOKUP (0x00000003)\r
+ @param EBX Low 32 bits of virtual address of caller allocated\r
+ STM_ADDRESS_LOOKUP_DESCRIPTOR structure.\r
+ @param ECX High 32 bits of virtual address of caller allocated\r
+ STM_ADDRESS_LOOKUP_DESCRIPTOR structure. If Intel64Mode is\r
+ clear (0), ECX must be zero.\r
+\r
+ @retval CF 0\r
+ No error, EAX set to STM_SUCCESS. PhysicalAddress contains the\r
+ host physical address determined by walking the interrupted SMM\r
+ guest's page tables. SmmGuestVirtualAddress contains the SMM\r
+ guest's virtual mapping of the requested address.\r
+ @retval CF 1\r
+ An error occurred, EAX holds relevant error value.\r
+ @retval EAX #ERROR_STM_SECURITY_VIOLATION\r
+ The requested page was a protected page.\r
+ @retval EAX #ERROR_STM_PAGE_NOT_FOUND\r
+ The requested virtual address did not exist in the page given\r
+ page table.\r
+ @retval EAX #ERROR_STM_BAD_CR3\r
+ The CR3 input was invalid. CR3 values must be from one of the\r
+ interrupted guest, or from the interrupted guest of another\r
+ processor.\r
+ @retval EAX #ERROR_STM_PHYSICAL_OVER_4G\r
+ The resulting physical address is greater than 4G and no virtual\r
+ address was supplied. The STM could not determine what address\r
+ within the SMM guest's virtual address space to do the mapping.\r
+ STM_ADDRESS_LOOKUP_DESCRIPTOR field PhysicalAddress contains the\r
+ physical address determined by walking the interrupted\r
+ environment's page tables.\r
+ @retval EAX #ERROR_STM_VIRTUAL_SPACE_TOO_SMALL\r
+ A specific virtual mapping was requested, but\r
+ SmmGuestVirtualAddress + Length exceeds 4G and the SMI handler\r
+ is running in 32 bit mode.\r
+ @retval EAX #ERROR_STM_UNSPECIFIED\r
+ An unspecified error occurred.\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_ADDRESS_LOOKUP 0x00000003\r
+\r
+/**\r
+ STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL\r
+**/\r
+typedef struct {\r
+ UINT64 InterruptedGuestVirtualAddress;\r
+ UINT32 Length;\r
+ UINT64 InterruptedCr3;\r
+ UINT64 InterruptedEptp;\r
+ UINT32 MapToSmmGuest:2;\r
+ UINT32 InterruptedCr4Pae:1;\r
+ UINT32 InterruptedCr4Pse:1;\r
+ UINT32 InterruptedIa32eMode:1;\r
+ UINT32 Reserved1:27;\r
+ UINT32 Reserved2;\r
+ UINT64 PhysicalAddress;\r
+ UINT64 SmmGuestVirtualAddress;\r
+} STM_ADDRESS_LOOKUP_DESCRIPTOR;\r
+\r
+/**\r
+ Define values for the MapToSmmGuest field of #STM_ADDRESS_LOOKUP_DESCRIPTOR\r
+ @{\r
+**/\r
+#define STM_ADDRESS_LOOKUP_DESCRIPTOR_DO_NOT_MAP 0\r
+#define STM_ADDRESS_LOOKUP_DESCRIPTOR_ONE_TO_ONE 1\r
+#define STM_ADDRESS_LOOKUP_DESCRIPTOR_VIRTUAL_ADDRESS_SPECIFIED 3\r
+/// @}\r
+\r
+\r
+/**\r
+ When returning from a protection exception (see section 6.2), the SMM guest\r
+ can instruct the STM to take one of two paths. It can either request a value\r
+ be logged to the TXT.ERRORCODE register and subsequently reset the machine\r
+ (indicating it couldn't resolve the problem), or it can request that the STM\r
+ resume the SMM guest again with the specified register state.\r
+\r
+ Unlike other VMCALL interfaces, StmReturnFromProtectionException behaves more\r
+ like a jump or an IRET instruction than a "call". It does not return directly\r
+ to the caller, but indirectly to a different location specified on the\r
+ caller's stack (see section 6.2) or not at all.\r
+\r
+ If the SMM guest STM protection exception handler itself causes a protection\r
+ exception (e.g. a single nested exception), or more than 100 un-nested\r
+ exceptions occur within the scope of a single SMI event, the STM must write\r
+ STM_CRASH_PROTECTION_EXCEPTION_FAILURE to the TXT.ERRORCODE register and\r
+ assert TXT.CMD.SYS_RESET. The reason for these restrictions is to simplify\r
+ the code requirements while still enabling a reasonable debugging capability.\r
+\r
+ @param EAX #STM_API_RETURN_FROM_PROTECTION_EXCEPTION (0x00000004)\r
+ @param EBX If 0, resume SMM guest using register state found on exception\r
+ stack. If in range 0x01..0x0F, EBX contains a BIOS error code\r
+ which the STM must record in the TXT.ERRORCODE register and\r
+ subsequently reset the system via TXT.CMD.SYS_RESET. The value\r
+ of the TXT.ERRORCODE register is calculated as follows:\r
+\r
+ TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC\r
+\r
+ Values 0x10..0xFFFFFFFF are reserved, do not use.\r
+\r
+**/\r
+#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004\r
+\r
+\r
+/**\r
+ VMCALL API Numbers\r
+ API number convention: MLE facing VMCALL interfaces have bit 16 set.\r
+\r
+ The STM configuration lifecycle is as follows:\r
+ 1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked).\r
+ 2. MLE invokes #STM_API_INITIALIZE_PROTECTION VMCALL to prepare STM for\r
+ setup of initial protection profile. This is done on a single CPU and\r
+ has global effect.\r
+ 3. MLE invokes #STM_API_PROTECT_RESOURCE VMCALL to define the initial\r
+ protection profile. The protection profile is global across all CPUs.\r
+ 4. MLE invokes #STM_API_START VMCALL to enable the STM to begin receiving\r
+ SMI events. This must be done on every logical CPU.\r
+ 5. MLE may invoke #STM_API_PROTECT_RESOURCE VMCALL or\r
+ #STM_API_UNPROTECT_RESOURCE VMCALL during runtime as many times as\r
+ necessary.\r
+ 6. MLE invokes #STM_API_STOP VMCALL to disable the STM. SMI is again masked\r
+ following #STM_API_STOP VMCALL.\r
+**/\r
+\r
+/**\r
+ StartStmVmcall() is used to configure an STM that is present in MSEG. SMIs\r
+ should remain disabled from the invocation of GETSEC[SENTER] until they are\r
+ re-enabled by StartStmVMCALL(). When StartStmVMCALL() returns, SMI is\r
+ enabled and the STM has been started and is active. Prior to invoking\r
+ StartStmVMCALL(), the MLE root should first invoke\r
+ InitializeProtectionVMCALL() followed by as many iterations of\r
+ ProtectResourceVMCALL() as necessary to establish the initial protection\r
+ profile. StartStmVmcall() must be invoked on all processor threads.\r
+\r
+ @param EAX #STM_API_START (0x00010001)\r
+ @param EDX STM configuration options. These provide the MLE with the\r
+ ability to pass configuration parameters to the STM.\r
+\r
+ @retval CF 0\r
+ No error, EAX set to STM_SUCCESS. The STM has been configured\r
+ and is now active and the guarding all requested resources.\r
+ @retval CF 1\r
+ An error occurred, EAX holds relevant error value.\r
+ @retval EAX #ERROR_STM_ALREADY_STARTED\r
+ The STM is already configured and active. STM remains active and\r
+ guarding previously enabled resource list.\r
+ @retval EAX #ERROR_STM_WITHOUT_SMX_UNSUPPORTED\r
+ The StartStmVMCALL() was invoked from VMX root mode, but outside\r
+ of SMX. This error code indicates the STM or platform does not\r
+ support the STM outside of SMX. The SMI handler remains active\r
+ and operates in legacy mode. See Appendix C\r
+ @retval EAX #ERROR_STM_UNSUPPORTED_MSR_BIT\r
+ The CPU doesn't support the MSR bit. The STM is not active.\r
+ @retval EAX #ERROR_STM_UNSPECIFIED\r
+ An unspecified error occurred.\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_START (BIT16 | 1)\r
+\r
+/**\r
+ Bit values for EDX input parameter to #STM_API_START VMCALL\r
+ @{\r
+**/\r
+#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF BIT0\r
+/// @}\r
+\r
+\r
+/**\r
+ The StopStmVMCALL() is invoked by the MLE to teardown an active STM. This is\r
+ normally done as part of a full teardown of the SMX environment when the\r
+ system is being shut down. At the time the call is invoked, SMI is enabled\r
+ and the STM is active. When the call returns, the STM has been stopped and\r
+ all STM context is discarded and SMI is disabled.\r
+\r
+ @param EAX #STM_API_STOP (0x00010002)\r
+\r
+ @retval CF 0\r
+ No error, EAX set to STM_SUCCESS. The STM has been stopped and\r
+ is no longer processing SMI events. SMI is blocked.\r
+ @retval CF 1\r
+ An error occurred, EAX holds relevant error value.\r
+ @retval EAX #ERROR_STM_STOPPED\r
+ The STM was not active.\r
+ @retval EAX #ERROR_STM_UNSPECIFIED\r
+ An unspecified error occurred.\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_STOP (BIT16 | 2)\r
+\r
+\r
+/**\r
+ The ProtectResourceVMCALL() is invoked by the MLE root to request protection\r
+ of specific resources. The request is defined by a STM_RESOURCE_LIST, which\r
+ may contain more than one resource descriptor. Each resource descriptor is\r
+ processed separately by the STM. Whether or not protection for any specific\r
+ resource is granted is returned by the STM via the ReturnStatus bit in the\r
+ associated STM_RSC_DESC_HEADER.\r
+\r
+ @param EAX #STM_API_PROTECT_RESOURCE (0x00010003)\r
+ @param EBX Low 32 bits of physical address of caller allocated\r
+ STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,\r
+ making the buffer 4K aligned.\r
+ @param ECX High 32 bits of physical address of caller allocated\r
+ STM_RESOURCE_LIST.\r
+\r
+ @note All fields of STM_RESOURCE_LIST are inputs only, except for the\r
+ ReturnStatus bit. On input, the ReturnStatus bit must be clear. On\r
+ return, the ReturnStatus bit is set for each resource request granted,\r
+ and clear for each resource request denied. There are no other fields\r
+ modified by ProtectResourceVMCALL(). The STM_RESOURCE_LIST must be\r
+ contained entirely within a single 4K page.\r
+\r
+ @retval CF 0\r
+ No error, EAX set to STM_SUCCESS. The STM has successfully\r
+ merged the entire protection request into the active protection\r
+ profile. There is therefore no need to check the ReturnStatus\r
+ bits in the STM_RESOURCE_LIST.\r
+ @retval CF 1\r
+ An error occurred, EAX holds relevant error value.\r
+ @retval EAX #ERROR_STM_UNPROTECTABLE_RESOURCE\r
+ At least one of the requested resource protections intersects a\r
+ BIOS required resource. Therefore, the caller must walk through\r
+ the STM_RESOURCE_LIST to determine which of the requested\r
+ resources was not granted protection. The entire list must be\r
+ traversed since there may be multiple failures.\r
+ @retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST\r
+ The resource list could not be parsed correctly, or did not\r
+ terminate before crossing a 4K page boundary. The caller must\r
+ walk through the STM_RESOURCE_LIST to determine which of the\r
+ requested resources was not granted protection. The entire list\r
+ must be traversed since there may be multiple failures.\r
+ @retval EAX #ERROR_STM_OUT_OF_RESOURCES\r
+ The STM has encountered an internal error and cannot complete\r
+ the request.\r
+ @retval EAX #ERROR_STM_UNSPECIFIED\r
+ An unspecified error occurred.\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_PROTECT_RESOURCE (BIT16 | 3)\r
+\r
+\r
+/**\r
+ The UnProtectResourceVMCALL() is invoked by the MLE root to request that the\r
+ STM allow the SMI handler access to the specified resources.\r
+\r
+ @param EAX #STM_API_UNPROTECT_RESOURCE (0x00010004)\r
+ @param EBX Low 32 bits of physical address of caller allocated\r
+ STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,\r
+ making the buffer 4K aligned.\r
+ @param ECX High 32 bits of physical address of caller allocated\r
+ STM_RESOURCE_LIST.\r
+\r
+ @note All fields of STM_RESOURCE_LIST are inputs only, except for the\r
+ ReturnStatus bit. On input, the ReturnStatus bit must be clear. On\r
+ return, the ReturnStatus bit is set for each resource processed. For\r
+ a properly formed STM_RESOURCE_LIST, this should be all resources\r
+ listed. There are no other fields modified by\r
+ UnProtectResourceVMCALL(). The STM_RESOURCE_LIST must be contained\r
+ entirely within a single 4K page.\r
+\r
+ @retval CF 0\r
+ No error, EAX set to STM_SUCCESS. The requested resources are\r
+ not being guarded by the STM.\r
+ @retval CF 1\r
+ An error occurred, EAX holds relevant error value.\r
+ @retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST\r
+ The resource list could not be parsed correctly, or did not\r
+ terminate before crossing a 4K page boundary. The caller must\r
+ walk through the STM_RESOURCE_LIST to determine which of the\r
+ requested resources were not able to be unprotected. The entire\r
+ list must be traversed since there may be multiple failures.\r
+ @retval EAX #ERROR_STM_UNSPECIFIED\r
+ An unspecified error occurred.\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_UNPROTECT_RESOURCE (BIT16 | 4)\r
+\r
+\r
+/**\r
+ The GetBiosResourcesVMCALL() is invoked by the MLE root to request the list\r
+ of BIOS required resources from the STM.\r
+\r
+ @param EAX #STM_API_GET_BIOS_RESOURCES (0x00010005)\r
+ @param EBX Low 32 bits of physical address of caller allocated destination\r
+ buffer. Bits 11:0 are ignored and assumed to be zero, making the\r
+ buffer 4K aligned.\r
+ @param ECX High 32 bits of physical address of caller allocated destination\r
+ buffer.\r
+ @param EDX Indicates which page of the BIOS resource list to copy into the\r
+ destination buffer. The first page is indicated by 0, the second\r
+ page by 1, etc.\r
+\r
+ @retval CF 0\r
+ No error, EAX set to STM_SUCCESS. The destination buffer\r
+ contains the BIOS required resources. If the page retrieved is\r
+ the last page, EDX will be cleared to 0. If there are more pages\r
+ to retrieve, EDX is incremented to the next page index. Calling\r
+ software should iterate on GetBiosResourcesVMCALL() until EDX is\r
+ returned cleared to 0.\r
+ @retval CF 1\r
+ An error occurred, EAX holds relevant error value.\r
+ @retval EAX #ERROR_STM_PAGE_NOT_FOUND\r
+ The page index supplied in EDX input was out of range.\r
+ @retval EAX #ERROR_STM_UNSPECIFIED\r
+ An unspecified error occurred.\r
+ @retval EDX Page index of next page to read. A return of EDX=0 signifies\r
+ that the entire list has been read.\r
+ @note EDX is both an input and an output register.\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_GET_BIOS_RESOURCES (BIT16 | 5)\r
+\r
+\r
+/**\r
+ The ManageVmcsDatabaseVMCALL() is invoked by the MLE root to add or remove an\r
+ MLE guest (including the MLE root) from the list of protected domains.\r
+\r
+ @param EAX #STM_API_MANAGE_VMCS_DATABASE (0x00010006)\r
+ @param EBX Low 32 bits of physical address of caller allocated\r
+ STM_VMCS_DATABASE_REQUEST. Bits 11:0 are ignored and assumed to\r
+ be zero, making the buffer 4K aligned.\r
+ @param ECX High 32 bits of physical address of caller allocated\r
+ STM_VMCS_DATABASE_REQUEST.\r
+\r
+ @note All fields of STM_VMCS_DATABASE_REQUEST are inputs only. They are not\r
+ modified by ManageVmcsDatabaseVMCALL().\r
+\r
+ @retval CF 0\r
+ No error, EAX set to STM_SUCCESS.\r
+ @retval CF 1\r
+ An error occurred, EAX holds relevant error value.\r
+ @retval EAX #ERROR_STM_INVALID_VMCS\r
+ Indicates a request to remove a VMCS from the database was made,\r
+ but the referenced VMCS was not found in the database.\r
+ @retval EAX #ERROR_STM_VMCS_PRESENT\r
+ Indicates a request to add a VMCS to the database was made, but\r
+ the referenced VMCS was already present in the database.\r
+ @retval EAX #ERROR_INVALID_PARAMETER\r
+ Indicates non-zero reserved field.\r
+ @retval EAX #ERROR_STM_UNSPECIFIED\r
+ An unspecified error occurred\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_MANAGE_VMCS_DATABASE (BIT16 | 6)\r
+\r
+/**\r
+ STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL\r
+**/\r
+typedef struct {\r
+ ///\r
+ /// bits 11:0 are reserved and must be 0\r
+ ///\r
+ UINT64 VmcsPhysPointer;\r
+ UINT32 DomainType :4;\r
+ UINT32 XStatePolicy :2;\r
+ UINT32 DegradationPolicy :4;\r
+ ///\r
+ /// Must be 0\r
+ ///\r
+ UINT32 Reserved1 :22;\r
+ UINT32 AddOrRemove;\r
+} STM_VMCS_DATABASE_REQUEST;\r
+\r
+/**\r
+ Values for the DomainType field of #STM_VMCS_DATABASE_REQUEST\r
+ @{\r
+**/\r
+#define DOMAIN_UNPROTECTED 0\r
+#define DOMAIN_DISALLOWED_IO_OUT BIT0\r
+#define DOMAIN_DISALLOWED_IO_IN BIT1\r
+#define DOMAIN_INTEGRITY BIT2\r
+#define DOMAIN_CONFIDENTIALITY BIT3\r
+#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY)\r
+#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY)\r
+#define DOMAIN_FULLY_PROT (DOMAIN_FULLY_PROT_OUT_IN | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT)\r
+/// @}\r
+\r
+/**\r
+ Values for the XStatePolicy field of #STM_VMCS_DATABASE_REQUEST\r
+ @{\r
+**/\r
+#define XSTATE_READWRITE 0x00\r
+#define XSTATE_READONLY 0x01\r
+#define XSTATE_SCRUB 0x03\r
+/// @}\r
+\r
+/**\r
+ Values for the AddOrRemove field of #STM_VMCS_DATABASE_REQUEST\r
+ @{\r
+**/\r
+#define STM_VMCS_DATABASE_REQUEST_ADD 1\r
+#define STM_VMCS_DATABASE_REQUEST_REMOVE 0\r
+/// @}\r
+\r
+\r
+/**\r
+ InitializeProtectionVMCALL() prepares the STM for setup of the initial\r
+ protection profile which is subsequently communicated via one or more\r
+ invocations of ProtectResourceVMCALL(), prior to invoking StartStmVMCALL().\r
+ It is only necessary to invoke InitializeProtectionVMCALL() on one processor\r
+ thread. InitializeProtectionVMCALL() does not alter whether SMIs are masked\r
+ or unmasked. The STM should return back to the MLE with "Blocking by SMI" set\r
+ to 1 in the GUEST_INTERRUPTIBILITY field for the VMCS the STM created for the\r
+ MLE guest.\r
+\r
+ @param EAX #STM_API_INITIALIZE_PROTECTION (0x00010007)\r
+\r
+ @retval CF 0\r
+ No error, EAX set to STM_SUCCESS, EBX bits set to indicate STM\r
+ capabilities as defined below. The STM has set up an empty\r
+ protection profile, except for the resources that it sets up to\r
+ protect itself. The STM must not allow the SMI handler to map\r
+ any pages from the MSEG Base to the top of TSEG. The STM must\r
+ also not allow SMI handler access to those MSRs which the STM\r
+ requires for its own protection.\r
+ @retval CF 1\r
+ An error occurred, EAX holds relevant error value.\r
+ @retval EAX #ERROR_STM_ALREADY_STARTED\r
+ The STM is already configured and active. The STM remains active\r
+ and guarding the previously enabled resource list.\r
+ @retval EAX #ERROR_STM_UNPROTECTABLE\r
+ The STM determines that based on the platform configuration, the\r
+ STM is unable to protect itself. For example, the BIOS required\r
+ resource list contains memory pages in MSEG.\r
+ @retval EAX #ERROR_STM_UNSPECIFIED\r
+ An unspecified error occurred.\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_INITIALIZE_PROTECTION (BIT16 | 7)\r
+\r
+/**\r
+ Byte granular support bits returned in EBX from #STM_API_INITIALIZE_PROTECTION\r
+ @{\r
+**/\r
+#define STM_RSC_BGI BIT1\r
+#define STM_RSC_BGM BIT2\r
+#define STM_RSC_MSR BIT3\r
+/// @}\r
+\r
+\r
+/**\r
+ The ManageEventLogVMCALL() is invoked by the MLE root to control the logging\r
+ feature. It consists of several sub-functions to facilitate establishment of\r
+ the log itself, configuring what events will be logged, and functions to\r
+ start, stop, and clear the log.\r
+\r
+ @param EAX #STM_API_MANAGE_EVENT_LOG (0x00010008)\r
+ @param EBX Low 32 bits of physical address of caller allocated\r
+ STM_EVENT_LOG_MANAGEMENT_REQUEST. Bits 11:0 are ignored and\r
+ assumed to be zero, making the buffer 4K aligned.\r
+ @param ECX High 32 bits of physical address of caller allocated\r
+ STM_EVENT_LOG_MANAGEMENT_REQUEST.\r
+\r
+ @retval CF=0\r
+ No error, EAX set to STM_SUCCESS.\r
+ @retval CF=1\r
+ An error occurred, EAX holds relevant error value. See subfunction\r
+ descriptions below for details.\r
+\r
+ @note All other registers unmodified.\r
+**/\r
+#define STM_API_MANAGE_EVENT_LOG (BIT16 | 8)\r
+\r
+///\r
+/// STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL\r
+///\r
+typedef struct {\r
+ UINT32 SubFunctionIndex;\r
+ union {\r
+ struct {\r
+ UINT32 PageCount;\r
+ //\r
+ // number of elements is PageCount\r
+ //\r
+ UINT64 Pages[];\r
+ } LogBuffer;\r
+ //\r
+ // bitmap of EVENT_TYPE\r
+ //\r
+ UINT32 EventEnableBitmap;\r
+ } Data;\r
+} STM_EVENT_LOG_MANAGEMENT_REQUEST;\r
+\r
+/**\r
+ Defines values for the SubFunctionIndex field of\r
+ #STM_EVENT_LOG_MANAGEMENT_REQUEST\r
+ @{\r
+**/\r
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_NEW_LOG 1\r
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CONFIGURE_LOG 2\r
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_START_LOG 3\r
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_STOP_LOG 4\r
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CLEAR_LOG 5\r
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_DELETE_LOG 6\r
+/// @}\r
+\r
+/**\r
+ Log Entry Header\r
+**/\r
+typedef struct {\r
+ UINT32 EventSerialNumber;\r
+ UINT16 Type;\r
+ UINT16 Lock :1;\r
+ UINT16 Valid :1;\r
+ UINT16 ReadByMle :1;\r
+ UINT16 Wrapped :1;\r
+ UINT16 Reserved :12;\r
+} LOG_ENTRY_HEADER;\r
+\r
+/**\r
+ Enum values for the Type field of #LOG_ENTRY_HEADER\r
+**/\r
+typedef enum {\r
+ EvtLogStarted,\r
+ EvtLogStopped,\r
+ EvtLogInvalidParameterDetected,\r
+ EvtHandledProtectionException,\r
+ ///\r
+ /// unhandled protection exceptions result in reset & cannot be logged\r
+ ///\r
+ EvtBiosAccessToUnclaimedResource,\r
+ EvtMleResourceProtectionGranted,\r
+ EvtMleResourceProtectionDenied,\r
+ EvtMleResourceUnprotect,\r
+ EvtMleResourceUnprotectError,\r
+ EvtMleDomainTypeDegraded,\r
+ ///\r
+ /// add more here\r
+ ///\r
+ EvtMleMax,\r
+ ///\r
+ /// Not used\r
+ ///\r
+ EvtInvalid = 0xFFFFFFFF,\r
+} EVENT_TYPE;\r
+\r
+typedef struct {\r
+ UINT32 Reserved;\r
+} ENTRY_EVT_LOG_STARTED;\r
+\r
+typedef struct {\r
+ UINT32 Reserved;\r
+} ENTRY_EVT_LOG_STOPPED;\r
+\r
+typedef struct {\r
+ UINT32 VmcallApiNumber;\r
+} ENTRY_EVT_LOG_INVALID_PARAM;\r
+\r
+typedef struct {\r
+ STM_RSC Resource;\r
+} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION;\r
+\r
+typedef struct {\r
+ STM_RSC Resource;\r
+} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC;\r
+\r
+typedef struct {\r
+ STM_RSC Resource;\r
+} ENTRY_EVT_MLE_RSC_PROT_GRANTED;\r
+\r
+typedef struct {\r
+ STM_RSC Resource;\r
+} ENTRY_EVT_MLE_RSC_PROT_DENIED;\r
+\r
+typedef struct {\r
+ STM_RSC Resource;\r
+} ENTRY_EVT_MLE_RSC_UNPROT;\r
+\r
+typedef struct {\r
+ STM_RSC Resource;\r
+} ENTRY_EVT_MLE_RSC_UNPROT_ERROR;\r
+\r
+typedef struct {\r
+ UINT64 VmcsPhysPointer;\r
+ UINT8 ExpectedDomainType;\r
+ UINT8 DegradedDomainType;\r
+} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED;\r
+\r
+typedef union {\r
+ ENTRY_EVT_LOG_STARTED Started;\r
+ ENTRY_EVT_LOG_STOPPED Stopped;\r
+ ENTRY_EVT_LOG_INVALID_PARAM InvalidParam;\r
+ ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException;\r
+ ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc;\r
+ ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted;\r
+ ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied;\r
+ ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot;\r
+ ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError;\r
+ ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded;\r
+} LOG_ENTRY_DATA;\r
+\r
+typedef struct {\r
+ LOG_ENTRY_HEADER Hdr;\r
+ LOG_ENTRY_DATA Data;\r
+} STM_LOG_ENTRY;\r
+\r
+/**\r
+ Maximum STM Log Entry Size\r
+**/\r
+#define STM_LOG_ENTRY_SIZE 256\r
+\r
+\r
+/**\r
+ STM Protection Exception Stack Frame Structures\r
+**/\r
+\r
+typedef struct {\r
+ UINT32 Rdi;\r
+ UINT32 Rsi;\r
+ UINT32 Rbp;\r
+ UINT32 Rdx;\r
+ UINT32 Rcx;\r
+ UINT32 Rbx;\r
+ UINT32 Rax;\r
+ UINT32 Cr3;\r
+ UINT32 Cr2;\r
+ UINT32 Cr0;\r
+ UINT32 VmcsExitInstructionInfo;\r
+ UINT32 VmcsExitInstructionLength;\r
+ UINT64 VmcsExitQualification;\r
+ ///\r
+ /// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value\r
+ ///\r
+ UINT32 ErrorCode;\r
+ UINT32 Rip;\r
+ UINT32 Cs;\r
+ UINT32 Rflags;\r
+ UINT32 Rsp;\r
+ UINT32 Ss;\r
+} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32;\r
+\r
+typedef struct {\r
+ UINT64 R15;\r
+ UINT64 R14;\r
+ UINT64 R13;\r
+ UINT64 R12;\r
+ UINT64 R11;\r
+ UINT64 R10;\r
+ UINT64 R9;\r
+ UINT64 R8;\r
+ UINT64 Rdi;\r
+ UINT64 Rsi;\r
+ UINT64 Rbp;\r
+ UINT64 Rdx;\r
+ UINT64 Rcx;\r
+ UINT64 Rbx;\r
+ UINT64 Rax;\r
+ UINT64 Cr8;\r
+ UINT64 Cr3;\r
+ UINT64 Cr2;\r
+ UINT64 Cr0;\r
+ UINT64 VmcsExitInstructionInfo;\r
+ UINT64 VmcsExitInstructionLength;\r
+ UINT64 VmcsExitQualification;\r
+ ///\r
+ /// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value\r
+ ///\r
+ UINT64 ErrorCode;\r
+ UINT64 Rip;\r
+ UINT64 Cs;\r
+ UINT64 Rflags;\r
+ UINT64 Rsp;\r
+ UINT64 Ss;\r
+} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64;\r
+\r
+typedef union {\r
+ STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame;\r
+ STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame;\r
+} STM_PROTECTION_EXCEPTION_STACK_FRAME;\r
+\r
+/**\r
+ Enum values for the ErrorCode field in\r
+ #STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 and\r
+ #STM_PROTECTION_EXCEPTION_STACK_FRAME_X64\r
+**/\r
+typedef enum {\r
+ TxtSmmPageViolation = 1,\r
+ TxtSmmMsrViolation,\r
+ TxtSmmRegisterViolation,\r
+ TxtSmmIoViolation,\r
+ TxtSmmPciViolation\r
+} TXT_SMM_PROTECTION_EXCEPTION_TYPE;\r
+\r
+/**\r
+ TXT Pocessor SMM Descriptor (PSD) structures\r
+**/\r
+\r
+typedef struct {\r
+ UINT64 SpeRip;\r
+ UINT64 SpeRsp;\r
+ UINT16 SpeSs;\r
+ UINT16 PageViolationException:1;\r
+ UINT16 MsrViolationException:1;\r
+ UINT16 RegisterViolationException:1;\r
+ UINT16 IoViolationException:1;\r
+ UINT16 PciViolationException:1;\r
+ UINT16 Reserved1:11;\r
+ UINT32 Reserved2;\r
+} STM_PROTECTION_EXCEPTION_HANDLER;\r
+\r
+typedef struct {\r
+ UINT8 ExecutionDisableOutsideSmrr:1;\r
+ UINT8 Intel64Mode:1;\r
+ UINT8 Cr4Pae : 1;\r
+ UINT8 Cr4Pse : 1;\r
+ UINT8 Reserved1 : 4;\r
+} STM_SMM_ENTRY_STATE;\r
+\r
+typedef struct {\r
+ UINT8 SmramToVmcsRestoreRequired : 1; ///> BIOS restore hint\r
+ UINT8 ReinitializeVmcsRequired : 1; ///> BIOS request\r
+ UINT8 Reserved2 : 6;\r
+} STM_SMM_RESUME_STATE;\r
+\r
+typedef struct {\r
+ UINT8 DomainType : 4; ///> STM input to BIOS on each SMI\r
+ UINT8 XStatePolicy : 2; ///> STM input to BIOS on each SMI\r
+ UINT8 EptEnabled : 1;\r
+ UINT8 Reserved3 : 1;\r
+} STM_SMM_STATE;\r
+\r
+#define TXT_SMM_PSD_OFFSET 0xfb00\r
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE SIGNATURE_64('T', 'X', 'T', 'P', 'S', 'S', 'I', 'G')\r
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1\r
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0\r
+\r
+typedef struct {\r
+ UINT64 Signature;\r
+ UINT16 Size;\r
+ UINT8 SmmDescriptorVerMajor;\r
+ UINT8 SmmDescriptorVerMinor;\r
+ UINT32 LocalApicId;\r
+ STM_SMM_ENTRY_STATE SmmEntryState;\r
+ STM_SMM_RESUME_STATE SmmResumeState;\r
+ STM_SMM_STATE StmSmmState;\r
+ UINT8 Reserved4;\r
+ UINT16 SmmCs;\r
+ UINT16 SmmDs;\r
+ UINT16 SmmSs;\r
+ UINT16 SmmOtherSegment;\r
+ UINT16 SmmTr;\r
+ UINT16 Reserved5;\r
+ UINT64 SmmCr3;\r
+ UINT64 SmmStmSetupRip;\r
+ UINT64 SmmStmTeardownRip;\r
+ UINT64 SmmSmiHandlerRip;\r
+ UINT64 SmmSmiHandlerRsp;\r
+ UINT64 SmmGdtPtr;\r
+ UINT32 SmmGdtSize;\r
+ UINT32 RequiredStmSmmRevId;\r
+ STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler;\r
+ UINT64 Reserved6;\r
+ UINT64 BiosHwResourceRequirementsPtr;\r
+ // extend area\r
+ UINT64 AcpiRsdp;\r
+ UINT8 PhysicalAddressBits;\r
+} TXT_PROCESSOR_SMM_DESCRIPTOR;\r
+\r
+#pragma pack ()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ STM Resource Descriptor\r
+\r
+ Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ SMI Transfer Monitor (STM) User Guide Revision 1.00\r
+\r
+**/\r
+\r
+#ifndef _INTEL_STM_RESOURCE_DESCRIPTOR_H_\r
+#define _INTEL_STM_RESOURCE_DESCRIPTOR_H_\r
+\r
+#pragma pack (1)\r
+\r
+/**\r
+ STM Resource Descriptor Header\r
+**/\r
+typedef struct {\r
+ UINT32 RscType;\r
+ UINT16 Length;\r
+ UINT16 ReturnStatus:1;\r
+ UINT16 Reserved:14;\r
+ UINT16 IgnoreResource:1;\r
+} STM_RSC_DESC_HEADER;\r
+\r
+/**\r
+ Define values for the RscType field of #STM_RSC_DESC_HEADER\r
+ @{\r
+**/\r
+#define END_OF_RESOURCES 0\r
+#define MEM_RANGE 1\r
+#define IO_RANGE 2\r
+#define MMIO_RANGE 3\r
+#define MACHINE_SPECIFIC_REG 4\r
+#define PCI_CFG_RANGE 5\r
+#define TRAPPED_IO_RANGE 6\r
+#define ALL_RESOURCES 7\r
+#define REGISTER_VIOLATION 8\r
+#define MAX_DESC_TYPE 8\r
+/// @}\r
+\r
+/**\r
+ STM Resource End Descriptor\r
+**/\r
+typedef struct {\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT64 ResourceListContinuation;\r
+} STM_RSC_END;\r
+\r
+/**\r
+ STM Resource Memory Descriptor\r
+**/\r
+typedef struct {\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT32 RWXAttributes:3;\r
+ UINT32 Reserved:29;\r
+ UINT32 Reserved_2;\r
+} STM_RSC_MEM_DESC;\r
+\r
+/**\r
+ Define values for the RWXAttributes field of #STM_RSC_MEM_DESC\r
+ @{\r
+**/\r
+#define STM_RSC_MEM_R 0x1\r
+#define STM_RSC_MEM_W 0x2\r
+#define STM_RSC_MEM_X 0x4\r
+/// @}\r
+\r
+/**\r
+ STM Resource I/O Descriptor\r
+**/\r
+typedef struct {\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT16 Base;\r
+ UINT16 Length;\r
+ UINT32 Reserved;\r
+} STM_RSC_IO_DESC;\r
+\r
+/**\r
+ STM Resource MMIO Descriptor\r
+**/\r
+typedef struct {\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT32 RWXAttributes:3;\r
+ UINT32 Reserved:29;\r
+ UINT32 Reserved_2;\r
+} STM_RSC_MMIO_DESC;\r
+\r
+/**\r
+ Define values for the RWXAttributes field of #STM_RSC_MMIO_DESC\r
+ @{\r
+**/\r
+#define STM_RSC_MMIO_R 0x1\r
+#define STM_RSC_MMIO_W 0x2\r
+#define STM_RSC_MMIO_X 0x4\r
+/// @}\r
+\r
+/**\r
+ STM Resource MSR Descriptor\r
+**/\r
+typedef struct {\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT32 MsrIndex;\r
+ UINT32 KernelModeProcessing:1;\r
+ UINT32 Reserved:31;\r
+ UINT64 ReadMask;\r
+ UINT64 WriteMask;\r
+} STM_RSC_MSR_DESC;\r
+\r
+/**\r
+ STM PCI Device Path node used for the PciDevicePath field of\r
+ #STM_RSC_PCI_CFG_DESC\r
+**/\r
+typedef struct {\r
+ ///\r
+ /// Must be 1, indicating Hardware Device Path\r
+ ///\r
+ UINT8 Type;\r
+ ///\r
+ /// Must be 1, indicating PCI\r
+ ///\r
+ UINT8 Subtype;\r
+ ///\r
+ /// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6\r
+ ///\r
+ UINT16 Length;\r
+ UINT8 PciFunction;\r
+ UINT8 PciDevice;\r
+} STM_PCI_DEVICE_PATH_NODE;\r
+\r
+/**\r
+ STM Resource PCI Configuration Descriptor\r
+**/\r
+typedef struct {\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT16 RWAttributes:2;\r
+ UINT16 Reserved:14;\r
+ UINT16 Base;\r
+ UINT16 Length;\r
+ UINT8 OriginatingBusNumber;\r
+ UINT8 LastNodeIndex;\r
+ STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];\r
+//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];\r
+} STM_RSC_PCI_CFG_DESC;\r
+\r
+/**\r
+ Define values for the RWAttributes field of #STM_RSC_PCI_CFG_DESC\r
+ @{\r
+**/\r
+#define STM_RSC_PCI_CFG_R 0x1\r
+#define STM_RSC_PCI_CFG_W 0x2\r
+/// @}\r
+\r
+/**\r
+ STM Resource Trapped I/O Descriptor\r
+**/\r
+typedef struct {\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT16 Base;\r
+ UINT16 Length;\r
+ UINT16 In:1;\r
+ UINT16 Out:1;\r
+ UINT16 Api:1;\r
+ UINT16 Reserved1:13;\r
+ UINT16 Reserved2;\r
+} STM_RSC_TRAPPED_IO_DESC;\r
+\r
+/**\r
+ STM Resource All Descriptor\r
+**/\r
+typedef struct {\r
+ STM_RSC_DESC_HEADER Hdr;\r
+} STM_RSC_ALL_RESOURCES_DESC;\r
+\r
+/**\r
+ STM Register Volation Descriptor\r
+**/\r
+typedef struct {\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT32 RegisterType;\r
+ UINT32 Reserved;\r
+ UINT64 ReadMask;\r
+ UINT64 WriteMask;\r
+} STM_REGISTER_VIOLATION_DESC;\r
+\r
+/**\r
+ Enum values for the RWAttributes field of #STM_REGISTER_VIOLATION_DESC\r
+**/\r
+typedef enum {\r
+ StmRegisterCr0,\r
+ StmRegisterCr2,\r
+ StmRegisterCr3,\r
+ StmRegisterCr4,\r
+ StmRegisterCr8,\r
+ StmRegisterMax,\r
+} STM_REGISTER_VIOLATION_TYPE;\r
+\r
+/**\r
+ Union of all STM resource types\r
+**/\r
+typedef union {\r
+ STM_RSC_DESC_HEADER Header;\r
+ STM_RSC_END End;\r
+ STM_RSC_MEM_DESC Mem;\r
+ STM_RSC_IO_DESC Io;\r
+ STM_RSC_MMIO_DESC Mmio;\r
+ STM_RSC_MSR_DESC Msr;\r
+ STM_RSC_PCI_CFG_DESC PciCfg;\r
+ STM_RSC_TRAPPED_IO_DESC TrappedIo;\r
+ STM_RSC_ALL_RESOURCES_DESC All;\r
+ STM_REGISTER_VIOLATION_DESC RegisterViolation;\r
+} STM_RSC;\r
+\r
+#pragma pack ()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ STM Status Codes\r
+\r
+ Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Specification Reference:\r
+ SMI Transfer Monitor (STM) User Guide Revision 1.00\r
+\r
+**/\r
+\r
+#ifndef _INTEL_STM_STATUS_CODE_H_\r
+#define _INTEL_STM_STATUS_CODE_H_\r
+\r
+/**\r
+ STM Status Codes\r
+**/\r
+typedef UINT32 STM_STATUS;\r
+\r
+/**\r
+ Success code have BIT31 clear.\r
+ All error codes have BIT31 set.\r
+ STM errors have BIT16 set.\r
+ SMM errors have BIT17 set\r
+ Errors that apply to both STM and SMM have bits BIT15, BT16, and BIT17 set.\r
+ STM TXT.ERRORCODE codes have BIT30 set.\r
+ @{\r
+**/\r
+#define STM_SUCCESS 0x00000000\r
+#define SMM_SUCCESS 0x00000000\r
+#define ERROR_STM_SECURITY_VIOLATION (BIT31 | BIT16 | 0x0001)\r
+#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED (BIT31 | BIT16 | 0x0002)\r
+#define ERROR_STM_PAGE_NOT_FOUND (BIT31 | BIT16 | 0x0003)\r
+#define ERROR_STM_BAD_CR3 (BIT31 | BIT16 | 0x0004)\r
+#define ERROR_STM_PHYSICAL_OVER_4G (BIT31 | BIT16 | 0x0005)\r
+#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL (BIT31 | BIT16 | 0x0006)\r
+#define ERROR_STM_UNPROTECTABLE_RESOURCE (BIT31 | BIT16 | 0x0007)\r
+#define ERROR_STM_ALREADY_STARTED (BIT31 | BIT16 | 0x0008)\r
+#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED (BIT31 | BIT16 | 0x0009)\r
+#define ERROR_STM_STOPPED (BIT31 | BIT16 | 0x000A)\r
+#define ERROR_STM_BUFFER_TOO_SMALL (BIT31 | BIT16 | 0x000B)\r
+#define ERROR_STM_INVALID_VMCS_DATABASE (BIT31 | BIT16 | 0x000C)\r
+#define ERROR_STM_MALFORMED_RESOURCE_LIST (BIT31 | BIT16 | 0x000D)\r
+#define ERROR_STM_INVALID_PAGECOUNT (BIT31 | BIT16 | 0x000E)\r
+#define ERROR_STM_LOG_ALLOCATED (BIT31 | BIT16 | 0x000F)\r
+#define ERROR_STM_LOG_NOT_ALLOCATED (BIT31 | BIT16 | 0x0010)\r
+#define ERROR_STM_LOG_NOT_STOPPED (BIT31 | BIT16 | 0x0011)\r
+#define ERROR_STM_LOG_NOT_STARTED (BIT31 | BIT16 | 0x0012)\r
+#define ERROR_STM_RESERVED_BIT_SET (BIT31 | BIT16 | 0x0013)\r
+#define ERROR_STM_NO_EVENTS_ENABLED (BIT31 | BIT16 | 0x0014)\r
+#define ERROR_STM_OUT_OF_RESOURCES (BIT31 | BIT16 | 0x0015)\r
+#define ERROR_STM_FUNCTION_NOT_SUPPORTED (BIT31 | BIT16 | 0x0016)\r
+#define ERROR_STM_UNPROTECTABLE (BIT31 | BIT16 | 0x0017)\r
+#define ERROR_STM_UNSUPPORTED_MSR_BIT (BIT31 | BIT16 | 0x0018)\r
+#define ERROR_STM_UNSPECIFIED (BIT31 | BIT16 | 0xFFFF)\r
+#define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)\r
+#define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)\r
+#define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)\r
+#define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)\r
+#define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)\r
+#define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)\r
+#define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)\r
+#define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)\r
+#define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)\r
+#define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)\r
+#define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)\r
+#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)\r
+#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)\r
+#define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)\r
+/// @}\r
+\r
+#endif\r
+++ /dev/null
-/** @file\r
- CPUID leaf definitions.\r
-\r
- Provides defines for CPUID leaf indexes. Data structures are provided for\r
- registers returned by a CPUID leaf that contain one or more bit fields.\r
- If a register returned is a single 32-bit value, then a data structure is\r
- not provided for that register.\r
-\r
- Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r
-\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r
-\r
-**/\r
-\r
-#ifndef __AMD_CPUID_H__\r
-#define __AMD_CPUID_H__\r
-\r
-/**\r
-CPUID Signature Information\r
-\r
-@param EAX CPUID_SIGNATURE (0x00)\r
-\r
-@retval EAX Returns the highest value the CPUID instruction recognizes for\r
- returning basic processor information. The value is returned is\r
- processor specific.\r
-@retval EBX First 4 characters of a vendor identification string.\r
-@retval ECX Last 4 characters of a vendor identification string.\r
-@retval EDX Middle 4 characters of a vendor identification string.\r
-\r
-**/\r
-\r
-///\r
-/// @{ CPUID signature values returned by AMD processors\r
-///\r
-#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')\r
-#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')\r
-#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')\r
-///\r
-/// @}\r
-///\r
-\r
-\r
-/**\r
- CPUID Extended Processor Signature and Features\r
-\r
- @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)\r
-\r
- @retval EAX Extended Family, Model, Stepping Identifiers\r
- described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.\r
- @retval EBX Brand Identifier\r
- described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.\r
- @retval ECX Extended Feature Identifiers\r
- described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.\r
- @retval EDX Extended Feature Identifiers\r
- described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.\r
-**/\r
-\r
-/**\r
- CPUID Extended Processor Signature and Features EAX for CPUID leaf\r
- #CPUID_EXTENDED_CPU_SIG.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Stepping.\r
- ///\r
- UINT32 Stepping:4;\r
- ///\r
- /// [Bits 7:4] Base Model.\r
- ///\r
- UINT32 BaseModel:4;\r
- ///\r
- /// [Bits 11:8] Base Family.\r
- ///\r
- UINT32 BaseFamily:4;\r
- ///\r
- /// [Bit 15:12] Reserved.\r
- ///\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 19:16] Extended Model.\r
- ///\r
- UINT32 ExtModel:4;\r
- ///\r
- /// [Bits 27:20] Extended Family.\r
- ///\r
- UINT32 ExtFamily:8;\r
- ///\r
- /// [Bit 31:28] Reserved.\r
- ///\r
- UINT32 Reserved2:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_AMD_EXTENDED_CPU_SIG_EAX;\r
-\r
-/**\r
- CPUID Extended Processor Signature and Features EBX for CPUID leaf\r
- #CPUID_EXTENDED_CPU_SIG.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 27:0] Reserved.\r
- ///\r
- UINT32 Reserved:28;\r
- ///\r
- /// [Bit 31:28] Package Type.\r
- ///\r
- UINT32 PkgType:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_AMD_EXTENDED_CPU_SIG_EBX;\r
-\r
-/**\r
- CPUID Extended Processor Signature and Features ECX for CPUID leaf\r
- #CPUID_EXTENDED_CPU_SIG.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r
- ///\r
- UINT32 LAHF_SAHF:1;\r
- ///\r
- /// [Bit 1] Core multi-processing legacy mode.\r
- ///\r
- UINT32 CmpLegacy:1;\r
- ///\r
- /// [Bit 2] Secure Virtual Mode feature.\r
- ///\r
- UINT32 SVM:1;\r
- ///\r
- /// [Bit 3] Extended APIC register space.\r
- ///\r
- UINT32 ExtApicSpace:1;\r
- ///\r
- /// [Bit 4] LOCK MOV CR0 means MOV CR8.\r
- ///\r
- UINT32 AltMovCr8:1;\r
- ///\r
- /// [Bit 5] LZCNT instruction support.\r
- ///\r
- UINT32 LZCNT:1;\r
- ///\r
- /// [Bit 6] SSE4A instruction support.\r
- ///\r
- UINT32 SSE4A:1;\r
- ///\r
- /// [Bit 7] Misaligned SSE Mode.\r
- ///\r
- UINT32 MisAlignSse:1;\r
- ///\r
- /// [Bit 8] ThreeDNow Prefetch instructions.\r
- ///\r
- UINT32 PREFETCHW:1;\r
- ///\r
- /// [Bit 9] OS Visible Work-around support.\r
- ///\r
- UINT32 OSVW:1;\r
- ///\r
- /// [Bit 10] Instruction Based Sampling.\r
- ///\r
- UINT32 IBS:1;\r
- ///\r
- /// [Bit 11] Extended Operation Support.\r
- ///\r
- UINT32 XOP:1;\r
- ///\r
- /// [Bit 12] SKINIT and STGI support.\r
- ///\r
- UINT32 SKINIT:1;\r
- ///\r
- /// [Bit 13] Watchdog Timer support.\r
- ///\r
- UINT32 WDT:1;\r
- ///\r
- /// [Bit 14] Reserved.\r
- ///\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 15] Lightweight Profiling support.\r
- ///\r
- UINT32 LWP:1;\r
- ///\r
- /// [Bit 16] 4-Operand FMA instruction support.\r
- ///\r
- UINT32 FMA4:1;\r
- ///\r
- /// [Bit 17] Translation Cache Extension.\r
- ///\r
- UINT32 TCE:1;\r
- ///\r
- /// [Bit 21:18] Reserved.\r
- ///\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 22] Topology Extensions support.\r
- ///\r
- UINT32 TopologyExtensions:1;\r
- ///\r
- /// [Bit 23] Core Performance Counter Extensions.\r
- ///\r
- UINT32 PerfCtrExtCore:1;\r
- ///\r
- /// [Bit 25:24] Reserved.\r
- ///\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 26] Data Breakpoint Extension.\r
- ///\r
- UINT32 DataBreakpointExtension:1;\r
- ///\r
- /// [Bit 27] Performance Time-Stamp Counter.\r
- ///\r
- UINT32 PerfTsc:1;\r
- ///\r
- /// [Bit 28] L3 Performance Counter Extensions.\r
- ///\r
- UINT32 PerfCtrExtL3:1;\r
- ///\r
- /// [Bit 29] MWAITX and MONITORX capability.\r
- ///\r
- UINT32 MwaitExtended:1;\r
- ///\r
- /// [Bit 31:30] Reserved.\r
- ///\r
- UINT32 Reserved4:2;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_AMD_EXTENDED_CPU_SIG_ECX;\r
-\r
-/**\r
- CPUID Extended Processor Signature and Features EDX for CPUID leaf\r
- #CPUID_EXTENDED_CPU_SIG.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] x87 floating point unit on-chip.\r
- ///\r
- UINT32 FPU:1;\r
- ///\r
- /// [Bit 1] Virtual-mode enhancements.\r
- ///\r
- UINT32 VME:1;\r
- ///\r
- /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.\r
- ///\r
- UINT32 DE:1;\r
- ///\r
- /// [Bit 3] Page-size extensions (4 MB pages).\r
- ///\r
- UINT32 PSE:1;\r
- ///\r
- /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.\r
- ///\r
- UINT32 TSC:1;\r
- ///\r
- /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.\r
- ///\r
- UINT32 MSR:1;\r
- ///\r
- /// [Bit 6] Physical-address extensions (PAE).\r
- ///\r
- UINT32 PAE:1;\r
- ///\r
- /// [Bit 7] Machine check exception, CR4.MCE.\r
- ///\r
- UINT32 MCE:1;\r
- ///\r
- /// [Bit 8] CMPXCHG8B instruction.\r
- ///\r
- UINT32 CMPXCHG8B:1;\r
- ///\r
- /// [Bit 9] APIC exists and is enabled.\r
- ///\r
- UINT32 APIC:1;\r
- ///\r
- /// [Bit 10] Reserved.\r
- ///\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 11] SYSCALL and SYSRET instructions.\r
- ///\r
- UINT32 SYSCALL_SYSRET:1;\r
- ///\r
- /// [Bit 12] Memory-type range registers.\r
- ///\r
- UINT32 MTRR:1;\r
- ///\r
- /// [Bit 13] Page global extension, CR4.PGE.\r
- ///\r
- UINT32 PGE:1;\r
- ///\r
- /// [Bit 14] Machine check architecture, MCG_CAP.\r
- ///\r
- UINT32 MCA:1;\r
- ///\r
- /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.\r
- ///\r
- UINT32 CMOV:1;\r
- ///\r
- /// [Bit 16] Page attribute table.\r
- ///\r
- UINT32 PAT:1;\r
- ///\r
- /// [Bit 17] Page-size extensions.\r
- ///\r
- UINT32 PSE36 : 1;\r
- ///\r
- /// [Bit 19:18] Reserved.\r
- ///\r
- UINT32 Reserved2:2;\r
- ///\r
- /// [Bit 20] No-execute page protection.\r
- ///\r
- UINT32 NX:1;\r
- ///\r
- /// [Bit 21] Reserved.\r
- ///\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 22] AMD Extensions to MMX instructions.\r
- ///\r
- UINT32 MmxExt:1;\r
- ///\r
- /// [Bit 23] MMX instructions.\r
- ///\r
- UINT32 MMX:1;\r
- ///\r
- /// [Bit 24] FXSAVE and FXRSTOR instructions.\r
- ///\r
- UINT32 FFSR:1;\r
- ///\r
- /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.\r
- ///\r
- UINT32 FFXSR:1;\r
- ///\r
- /// [Bit 26] 1-GByte large page support.\r
- ///\r
- UINT32 Page1GB:1;\r
- ///\r
- /// [Bit 27] RDTSCP intructions.\r
- ///\r
- UINT32 RDTSCP:1;\r
- ///\r
- /// [Bit 28] Reserved.\r
- ///\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bit 29] Long Mode.\r
- ///\r
- UINT32 LM:1;\r
- ///\r
- /// [Bit 30] 3DNow! instructions.\r
- ///\r
- UINT32 ThreeDNow:1;\r
- ///\r
- /// [Bit 31] AMD Extensions to 3DNow! instructions.\r
- ///\r
- UINT32 ThreeDNowExt:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_AMD_EXTENDED_CPU_SIG_EDX;\r
-\r
-\r
-/**\r
-CPUID Linear Physical Address Size\r
-\r
-@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)\r
-\r
-@retval EAX Linear/Physical Address Size described by the type\r
- CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.\r
-@retval EBX Linear/Physical Address Size described by the type\r
- CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.\r
-@retval ECX Linear/Physical Address Size described by the type\r
- CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.\r
-@retval EDX Reserved.\r
-**/\r
-\r
-/**\r
- CPUID Linear Physical Address Size EAX for CPUID leaf\r
- #CPUID_VIR_PHY_ADDRESS_SIZE.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Maximum physical byte address size in bits.\r
- ///\r
- UINT32 PhysicalAddressBits:8;\r
- ///\r
- /// [Bits 15:8] Maximum linear byte address size in bits.\r
- ///\r
- UINT32 LinearAddressBits:8;\r
- ///\r
- /// [Bits 23:16] Maximum guest physical byte address size in bits.\r
- ///\r
- UINT32 GuestPhysAddrSize:8;\r
- ///\r
- /// [Bit 31:24] Reserved.\r
- ///\r
- UINT32 Reserved:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;\r
-\r
-/**\r
- CPUID Linear Physical Address Size EBX for CPUID leaf\r
- #CPUID_VIR_PHY_ADDRESS_SIZE.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 0] Clear Zero Instruction.\r
- ///\r
- UINT32 CLZERO:1;\r
- ///\r
- /// [Bits 1] Instructions retired count support.\r
- ///\r
- UINT32 IRPerf:1;\r
- ///\r
- /// [Bits 2] Restore error pointers for XSave instructions.\r
- ///\r
- UINT32 XSaveErPtr:1;\r
- ///\r
- /// [Bit 31:3] Reserved.\r
- ///\r
- UINT32 Reserved:29;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;\r
-\r
-/**\r
- CPUID Linear Physical Address Size ECX for CPUID leaf\r
- #CPUID_VIR_PHY_ADDRESS_SIZE.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Number of threads - 1.\r
- ///\r
- UINT32 NC:8;\r
- ///\r
- /// [Bit 11:8] Reserved.\r
- ///\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 15:12] APIC ID size.\r
- ///\r
- UINT32 ApicIdCoreIdSize:4;\r
- ///\r
- /// [Bits 17:16] Performance time-stamp counter size.\r
- ///\r
- UINT32 PerfTscSize:2;\r
- ///\r
- /// [Bit 31:18] Reserved.\r
- ///\r
- UINT32 Reserved2:14;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;\r
-\r
-\r
-/**\r
- CPUID AMD Processor Topology\r
-\r
- @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)\r
-\r
- @retval EAX Extended APIC ID described by the type\r
- CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.\r
- @retval EBX Core Indentifiers described by the type\r
- CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.\r
- @retval ECX Node Indentifiers described by the type\r
- CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.\r
- @retval EDX Reserved.\r
-**/\r
-#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E\r
-\r
-/**\r
- CPUID AMD Processor Topology EAX for CPUID leaf\r
- #CPUID_AMD_PROCESSOR_TOPOLOGY.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 31:0] Extended APIC Id.\r
- ///\r
- UINT32 ExtendedApicId;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;\r
-\r
-/**\r
- CPUID AMD Processor Topology EBX for CPUID leaf\r
- #CPUID_AMD_PROCESSOR_TOPOLOGY.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Core Id.\r
- ///\r
- UINT32 CoreId:8;\r
- ///\r
- /// [Bits 15:8] Threads per core.\r
- ///\r
- UINT32 ThreadsPerCore:8;\r
- ///\r
- /// [Bit 31:16] Reserved.\r
- ///\r
- UINT32 Reserved:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;\r
-\r
-/**\r
- CPUID AMD Processor Topology ECX for CPUID leaf\r
- #CPUID_AMD_PROCESSOR_TOPOLOGY.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Node Id.\r
- ///\r
- UINT32 NodeId:8;\r
- ///\r
- /// [Bits 10:8] Nodes per processor.\r
- ///\r
- UINT32 NodesPerProcessor:3;\r
- ///\r
- /// [Bit 31:11] Reserved.\r
- ///\r
- UINT32 Reserved:21;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;\r
-\r
-\r
-/**\r
- CPUID Memory Encryption Information\r
-\r
- @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)\r
-\r
- @retval EAX Returns the memory encryption feature support status.\r
- @retval EBX If memory encryption feature is present then return\r
- the page table bit number used to enable memory encryption support\r
- and reducing of physical address space in bits.\r
- @retval ECX Returns number of encrypted guest supported simultaneously.\r
- @retval EDX Returns minimum SEV enabled and SEV disabled ASID.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT32 Eax;\r
- UINT32 Ebx;\r
- UINT32 Ecx;\r
- UINT32 Edx;\r
-\r
- AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);\r
- @endcode\r
-**/\r
-\r
-#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F\r
-\r
-/**\r
- CPUID Memory Encryption support information EAX for CPUID leaf\r
- #CPUID_MEMORY_ENCRYPTION_INFO.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Secure Memory Encryption (Sme) Support\r
- ///\r
- UINT32 SmeBit:1;\r
-\r
- ///\r
- /// [Bit 1] Secure Encrypted Virtualization (Sev) Support\r
- ///\r
- UINT32 SevBit:1;\r
-\r
- ///\r
- /// [Bit 2] Page flush MSR support\r
- ///\r
- UINT32 PageFlushMsrBit:1;\r
-\r
- ///\r
- /// [Bit 3] Encrypted state support\r
- ///\r
- UINT32 SevEsBit:1;\r
-\r
- ///\r
- /// [Bit 31:4] Reserved\r
- ///\r
- UINT32 ReservedBits:28;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_MEMORY_ENCRYPTION_INFO_EAX;\r
-\r
-/**\r
- CPUID Memory Encryption support information EBX for CPUID leaf\r
- #CPUID_MEMORY_ENCRYPTION_INFO.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 5:0] Page table bit number used to enable memory encryption\r
- ///\r
- UINT32 PtePosBits:6;\r
-\r
- ///\r
- /// [Bit 11:6] Reduction of system physical address space bits when\r
- /// memory encryption is enabled\r
- ///\r
- UINT32 ReducedPhysBits:5;\r
-\r
- ///\r
- /// [Bit 31:12] Reserved\r
- ///\r
- UINT32 ReservedBits:21;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_MEMORY_ENCRYPTION_INFO_EBX;\r
-\r
-/**\r
- CPUID Memory Encryption support information ECX for CPUID leaf\r
- #CPUID_MEMORY_ENCRYPTION_INFO.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 31:0] Number of encrypted guest supported simultaneously\r
- ///\r
- UINT32 NumGuests;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_MEMORY_ENCRYPTION_INFO_ECX;\r
-\r
-/**\r
- CPUID Memory Encryption support information EDX for CPUID leaf\r
- #CPUID_MEMORY_ENCRYPTION_INFO.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID\r
- ///\r
- UINT32 MinAsid;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
-} CPUID_MEMORY_ENCRYPTION_INFO_EDX;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r
-\r
-**/\r
-\r
-#ifndef __FAM17_MSR_H__\r
-#define __FAM17_MSR_H__\r
-\r
-/**\r
- Secure Encrypted Virtualization (SEV) status register\r
-\r
-**/\r
-#define MSR_SEV_STATUS 0xc0010131\r
-\r
-/**\r
- MSR information returned for #MSR_SEV_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled\r
- ///\r
- UINT32 SevBit:1;\r
-\r
- ///\r
- /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled\r
- ///\r
- UINT32 SevEsBit:1;\r
-\r
- UINT32 Reserved:30;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SEV_STATUS_REGISTER;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r
-\r
-**/\r
-\r
-#ifndef __AMD_MSR_H__\r
-#define __AMD_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-#include <Register/Amd/Fam17Msr.h>\r
-\r
-#endif\r
/** @file\r
- Architectural MSR Definitions.\r
+ Wrapper header file to include <Register/Intel/ArchitecturalMsr.h> in MdePkg.\r
\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
**/\r
\r
#ifndef __ARCHITECTURAL_MSR_H__\r
#define __ARCHITECTURAL_MSR_H__\r
\r
-/**\r
- See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
-\r
- @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);\r
- AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);\r
- @endcode\r
- @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.\r
-**/\r
-#define MSR_IA32_P5_MC_ADDR 0x00000000\r
-\r
-\r
-/**\r
- See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
-\r
- @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);\r
- AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);\r
- @endcode\r
- @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.\r
-**/\r
-#define MSR_IA32_P5_MC_TYPE 0x00000001\r
-\r
-\r
-/**\r
- See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced\r
- at Display Family / Display Model 0F_03H.\r
-\r
- @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);\r
- AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);\r
- @endcode\r
- @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.\r
-**/\r
-#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r
-\r
-\r
-/**\r
- See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /\r
- Display Model 05_01H.\r
-\r
- @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);\r
- AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);\r
- @endcode\r
- @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.\r
-**/\r
-#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r
-\r
-\r
-/**\r
- Platform ID (RO) The operating system can use this MSR to determine "slot"\r
- information for the processor and the proper microcode update to load.\r
- Introduced at Display Family / Display Model 06_01H.\r
-\r
- @param ECX MSR_IA32_PLATFORM_ID (0x00000017)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PLATFORM_ID_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r
- @endcode\r
- @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r
-**/\r
-#define MSR_IA32_PLATFORM_ID 0x00000017\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PLATFORM_ID\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:18;\r
- ///\r
- /// [Bits 52:50] Platform Id (RO) Contains information concerning the\r
- /// intended platform for the processor.\r
- /// 52 51 50\r
- /// -- -- --\r
- /// 0 0 0 Processor Flag 0.\r
- /// 0 0 1 Processor Flag 1\r
- /// 0 1 0 Processor Flag 2\r
- /// 0 1 1 Processor Flag 3\r
- /// 1 0 0 Processor Flag 4\r
- /// 1 0 1 Processor Flag 5\r
- /// 1 1 0 Processor Flag 6\r
- /// 1 1 1 Processor Flag 7\r
- ///\r
- UINT32 PlatformId:3;\r
- UINT32 Reserved3:11;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PLATFORM_ID_REGISTER;\r
-\r
-\r
-/**\r
- 06_01H.\r
-\r
- @param ECX MSR_IA32_APIC_BASE (0x0000001B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_APIC_BASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_APIC_BASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_APIC_BASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
- AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.\r
-**/\r
-#define MSR_IA32_APIC_BASE 0x0000001B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_APIC_BASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bit 8] BSP flag (R/W).\r
- ///\r
- UINT32 BSP:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display\r
- /// Model 06_1AH.\r
- ///\r
- UINT32 EXTD:1;\r
- ///\r
- /// [Bit 11] APIC Global Enable (R/W).\r
- ///\r
- UINT32 EN:1;\r
- ///\r
- /// [Bits 31:12] APIC Base (R/W).\r
- ///\r
- UINT32 ApicBase:20;\r
- ///\r
- /// [Bits 63:32] APIC Base (R/W).\r
- ///\r
- UINT32 ApicBaseHi:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_APIC_BASE_REGISTER;\r
-\r
-\r
-/**\r
- Control Features in Intel 64 Processor (R/W). If any one enumeration\r
- condition for defined bit field holds.\r
-\r
- @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_IA32_FEATURE_CONTROL 0x0000003A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from\r
- /// being written, writes to this bit will result in GP(0). Note: Once the\r
- /// Lock bit is set, the contents of this register cannot be modified.\r
- /// Therefore the lock bit must be set after configuring support for Intel\r
- /// Virtualization Technology and prior to transferring control to an\r
- /// option ROM or the OS. Hence, once the Lock bit is set, the entire\r
- /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD\r
- /// is not deasserted. If any one enumeration condition for defined bit\r
- /// field position greater than bit 0 holds.\r
- ///\r
- UINT32 Lock:1;\r
- ///\r
- /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a\r
- /// system executive to use VMX in conjunction with SMX to support\r
- /// Intel(R) Trusted Execution Technology. BIOS must set this bit only\r
- /// when the CPUID function 1 returns VMX feature flag and SMX feature\r
- /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&\r
- /// CPUID.01H:ECX[6] = 1.\r
- ///\r
- UINT32 EnableVmxInsideSmx:1;\r
- ///\r
- /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX\r
- /// for system executive that do not require SMX. BIOS must set this bit\r
- /// only when the CPUID function 1 returns VMX feature flag set (ECX bit\r
- /// 5). If CPUID.01H:ECX[5] = 1.\r
- ///\r
- UINT32 EnableVmxOutsideSmx:1;\r
- UINT32 Reserved1:5;\r
- ///\r
- /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit\r
- /// in the field represents an enable control for a corresponding SENTER\r
- /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If\r
- /// CPUID.01H:ECX[6] = 1.\r
- ///\r
- UINT32 SenterLocalFunctionEnables:7;\r
- ///\r
- /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable\r
- /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit\r
- /// 6] is set. If CPUID.01H:ECX[6] = 1.\r
- ///\r
- UINT32 SenterGlobalEnable:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r
- /// enable runtime reconfiguration of SGX Launch Control via\r
- /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r
- ///\r
- UINT32 SgxLaunchControlEnable:1;\r
- ///\r
- /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r
- /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
- ///\r
- UINT32 SgxEnable:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 20] LMCE On (R/WL): When set, system software can program the\r
- /// MSRs associated with LMCE to configure delivery of some machine check\r
- /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.\r
- ///\r
- UINT32 LmceOn:1;\r
- UINT32 Reserved4:11;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,\r
- ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for\r
- a logical processor. Reset value is Zero. A write to IA32_TSC will modify\r
- the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does\r
- not affect the internal invariant TSC hardware.\r
-\r
- @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);\r
- AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);\r
- @endcode\r
- @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.\r
-**/\r
-#define MSR_IA32_TSC_ADJUST 0x0000003B\r
-\r
-\r
-/**\r
- BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a\r
- microcode update to be loaded into the processor. See Section 9.11.6,\r
- "Microcode Update Loader." A processor may prevent writing to this MSR when\r
- loading guest states on VM entries or saving guest states on VM exits.\r
- Introduced at Display Family / Display Model 06_01H.\r
-\r
- @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = 0;\r
- AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);\r
- @endcode\r
- @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.\r
-**/\r
-#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r
-\r
-\r
-/**\r
- BIOS Update Signature (RO) Returns the microcode update signature following\r
- the execution of CPUID.01H. A processor may prevent writing to this MSR when\r
- loading guest states on VM entries or saving guest states on VM exits.\r
- Introduced at Display Family / Display Model 06_01H.\r
-\r
- @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r
- @endcode\r
- @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.\r
-**/\r
-#define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved:32;\r
- ///\r
- /// [Bits 63:32] Microcode update signature. This field contains the\r
- /// signature of the currently loaded microcode update when read following\r
- /// the execution of the CPUID instruction, function 1. It is required\r
- /// that this register field be pre-loaded with zero prior to executing\r
- /// the CPUID, function 1. If the field remains equal to zero, then there\r
- /// is no microcode update loaded. Another nonzero value will be the\r
- /// signature.\r
- ///\r
- UINT32 MicrocodeUpdateSignature:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_BIOS_SIGN_ID_REGISTER;\r
-\r
-\r
-/**\r
- IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r
- SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r
- default value is the digest of Intel's signing key. Read permitted If\r
- CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):\r
- EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.\r
-\r
- @param ECX MSR_IA32_SGXLEPUBKEYHASHn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);\r
- AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);\r
- @endcode\r
- @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.\r
- MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.\r
- MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.\r
- MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r
-#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r
-#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r
-#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r
-/// @}\r
-\r
-\r
-/**\r
- SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r
- 1.\r
-\r
- @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r
- AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.\r
-**/\r
-#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this\r
- /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment\r
- /// (see Section 34.15.6), the dual-monitor treatment cannot be activated\r
- /// if the bit is 0. This bit is cleared when the logical processor is\r
- /// reset.\r
- ///\r
- UINT32 Valid:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If\r
- /// IA32_VMX_MISC[28].\r
- ///\r
- UINT32 BlockSmi:1;\r
- UINT32 Reserved2:9;\r
- ///\r
- /// [Bits 31:12] MSEG Base (R/W).\r
- ///\r
- UINT32 MsegBase:20;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r
-\r
-/**\r
- MSEG header that is located at the physical address specified by the MsegBase\r
- field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
-**/\r
-typedef struct {\r
- ///\r
- /// Different processors may use different MSEG revision identifiers. These\r
- /// identifiers enable software to avoid using an MSEG header formatted for\r
- /// one processor on a processor that uses a different format. Software can\r
- /// discover the MSEG revision identifier that a processor uses by reading\r
- /// the VMX capability MSR IA32_VMX_MISC.\r
- //\r
- UINT32 MsegHeaderRevision;\r
- ///\r
- /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r
- /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r
- /// processor will be in IA-32e mode after the STM is activated.\r
- ///\r
- UINT32 MonitorFeatures;\r
- UINT32 GdtrLimit;\r
- UINT32 GdtrBaseOffset;\r
- UINT32 CsSelector;\r
- UINT32 EipOffset;\r
- UINT32 EspOffset;\r
- UINT32 Cr3Offset;\r
- ///\r
- /// Pad header so total size is 2KB\r
- ///\r
- UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
-} MSEG_HEADER;\r
-\r
-///\r
-/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r
-///\r
-#define STM_FEATURES_IA32E 0x1\r
-///\r
-/// @}\r
-///\r
-\r
-/**\r
- Base address of the logical processor's SMRAM image (RO, SMM only). If\r
- IA32_VMX_MISC[15].\r
-\r
- @param ECX MSR_IA32_SMBASE (0x0000009E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_SMBASE);\r
- @endcode\r
- @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.\r
-**/\r
-#define MSR_IA32_SMBASE 0x0000009E\r
-\r
-\r
-/**\r
- General Performance Counters (R/W).\r
- MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.\r
-\r
- @param ECX MSR_IA32_PMCn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_PMC0);\r
- AsmWriteMsr64 (MSR_IA32_PMC0, Msr);\r
- @endcode\r
- @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.\r
- MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.\r
- MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.\r
- MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.\r
- MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.\r
- MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.\r
- MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.\r
- MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_PMC0 0x000000C1\r
-#define MSR_IA32_PMC1 0x000000C2\r
-#define MSR_IA32_PMC2 0x000000C3\r
-#define MSR_IA32_PMC3 0x000000C4\r
-#define MSR_IA32_PMC4 0x000000C5\r
-#define MSR_IA32_PMC5 0x000000C6\r
-#define MSR_IA32_PMC6 0x000000C7\r
-#define MSR_IA32_PMC7 0x000000C8\r
-/// @}\r
-\r
-\r
-/**\r
- TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.\r
- C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative\r
- to TSC freq.) when the logical processor is in C0. Cleared upon overflow /\r
- wrap-around of IA32_APERF.\r
-\r
- @param ECX MSR_IA32_MPERF (0x000000E7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MPERF);\r
- AsmWriteMsr64 (MSR_IA32_MPERF, Msr);\r
- @endcode\r
- @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.\r
-**/\r
-#define MSR_IA32_MPERF 0x000000E7\r
-\r
-\r
-/**\r
- Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =\r
- 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at\r
- the coordinated clock frequency, when the logical processor is in C0.\r
- Cleared upon overflow / wrap-around of IA32_MPERF.\r
-\r
- @param ECX MSR_IA32_APERF (0x000000E8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_APERF);\r
- AsmWriteMsr64 (MSR_IA32_APERF, Msr);\r
- @endcode\r
- @note MSR_IA32_APERF is defined as IA32_APERF in SDM.\r
-**/\r
-#define MSR_IA32_APERF 0x000000E8\r
-\r
-\r
-/**\r
- MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".\r
- Introduced at Display Family / Display Model 06_01H.\r
-\r
- @param ECX MSR_IA32_MTRRCAP (0x000000FE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_MTRRCAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_MTRRCAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_MTRRCAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
- @endcode\r
- @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.\r
-**/\r
-#define MSR_IA32_MTRRCAP 0x000000FE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_MTRRCAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] VCNT: The number of variable memory type ranges in the\r
- /// processor.\r
- ///\r
- UINT32 VCNT:8;\r
- ///\r
- /// [Bit 8] Fixed range MTRRs are supported when set.\r
- ///\r
- UINT32 FIX:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 10] WC Supported when set.\r
- ///\r
- UINT32 WC:1;\r
- ///\r
- /// [Bit 11] SMRR Supported when set.\r
- ///\r
- UINT32 SMRR:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_MTRRCAP_REGISTER;\r
-\r
-\r
-/**\r
- SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
-\r
- @param ECX MSR_IA32_SYSENTER_CS (0x00000174)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_SYSENTER_CS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);\r
- AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.\r
-**/\r
-#define MSR_IA32_SYSENTER_CS 0x00000174\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_SYSENTER_CS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] CS Selector.\r
- ///\r
- UINT32 CS:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_SYSENTER_CS_REGISTER;\r
-\r
-\r
-/**\r
- SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
-\r
- @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);\r
- AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);\r
- @endcode\r
- @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.\r
-**/\r
-#define MSR_IA32_SYSENTER_ESP 0x00000175\r
-\r
-\r
-/**\r
- SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
-\r
- @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);\r
- AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);\r
- @endcode\r
- @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.\r
-**/\r
-#define MSR_IA32_SYSENTER_EIP 0x00000176\r
-\r
-\r
-/**\r
- Global Machine Check Capability (RO). Introduced at Display Family / Display\r
- Model 06_01H.\r
-\r
- @param ECX MSR_IA32_MCG_CAP (0x00000179)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_MCG_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_MCG_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_MCG_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
- @endcode\r
- @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
-**/\r
-#define MSR_IA32_MCG_CAP 0x00000179\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_MCG_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Count: Number of reporting banks.\r
- ///\r
- UINT32 Count:8;\r
- ///\r
- /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.\r
- ///\r
- UINT32 MCG_CTL_P:1;\r
- ///\r
- /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present\r
- /// if this bit is set.\r
- ///\r
- UINT32 MCG_EXT_P:1;\r
- ///\r
- /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.\r
- /// Introduced at Display Family / Display Model 06_01H.\r
- ///\r
- UINT32 MCP_CMCI_P:1;\r
- ///\r
- /// [Bit 11] MCG_TES_P: Threshold-based error status register are present\r
- /// if this bit is set.\r
- ///\r
- UINT32 MCG_TES_P:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state\r
- /// registers present.\r
- ///\r
- UINT32 MCG_EXT_CNT:8;\r
- ///\r
- /// [Bit 24] MCG_SER_P: The processor supports software error recovery if\r
- /// this bit is set.\r
- ///\r
- UINT32 MCG_SER_P:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform\r
- /// firmware to be invoked when an error is detected so that it may\r
- /// provide additional platform specific information in an ACPI format\r
- /// "Generic Error Data Entry" that augments the data included in machine\r
- /// check bank registers. Introduced at Display Family / Display Model\r
- /// 06_3EH.\r
- ///\r
- UINT32 MCG_ELOG_P:1;\r
- ///\r
- /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended\r
- /// state in IA32_MCG_STATUS and associated MSR necessary to configure\r
- /// Local Machine Check Exception (LMCE). Introduced at Display Family /\r
- /// Display Model 06_3EH.\r
- ///\r
- UINT32 MCG_LMCE_P:1;\r
- UINT32 Reserved3:4;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_MCG_CAP_REGISTER;\r
-\r
-\r
-/**\r
- Global Machine Check Status (R/W0). Introduced at Display Family / Display\r
- Model 06_01H.\r
-\r
- @param ECX MSR_IA32_MCG_STATUS (0x0000017A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_MCG_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r
- AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.\r
-**/\r
-#define MSR_IA32_MCG_STATUS 0x0000017A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_MCG_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display\r
- /// Model 06_01H.\r
- ///\r
- UINT32 RIPV:1;\r
- ///\r
- /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display\r
- /// Model 06_01H.\r
- ///\r
- UINT32 EIPV:1;\r
- ///\r
- /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family\r
- /// / Display Model 06_01H.\r
- ///\r
- UINT32 MCIP:1;\r
- ///\r
- /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.\r
- ///\r
- UINT32 LMCE_S:1;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_MCG_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.\r
-\r
- @param ECX MSR_IA32_MCG_CTL (0x0000017B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);\r
- AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);\r
- @endcode\r
- @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.\r
-**/\r
-#define MSR_IA32_MCG_CTL 0x0000017B\r
-\r
-\r
-/**\r
- Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.\r
-\r
- @param ECX MSR_IA32_PERFEVTSELn\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PERFEVTSEL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r
- MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r
- MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r
- MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_PERFEVTSEL0 0x00000186\r
-#define MSR_IA32_PERFEVTSEL1 0x00000187\r
-#define MSR_IA32_PERFEVTSEL2 0x00000188\r
-#define MSR_IA32_PERFEVTSEL3 0x00000189\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to\r
- #MSR_IA32_PERFEVTSEL3\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
- ///\r
- UINT32 EventSelect:8;\r
- ///\r
- /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
- /// detect on the selected event logic.\r
- ///\r
- UINT32 UMASK:8;\r
- ///\r
- /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
- ///\r
- UINT32 USR:1;\r
- ///\r
- /// [Bit 17] OS: Counts while in privilege level is ring 0.\r
- ///\r
- UINT32 OS:1;\r
- ///\r
- /// [Bit 18] Edge: Enables edge detection if set.\r
- ///\r
- UINT32 E:1;\r
- ///\r
- /// [Bit 19] PC: enables pin control.\r
- ///\r
- UINT32 PC:1;\r
- ///\r
- /// [Bit 20] INT: enables interrupt on counter overflow.\r
- ///\r
- UINT32 INT:1;\r
- ///\r
- /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
- /// event conditions occurring across all logical processors sharing a\r
- /// processor core. When set to 0, the counter only increments the\r
- /// associated event conditions occurring in the logical processor which\r
- /// programmed the MSR.\r
- ///\r
- UINT32 ANY:1;\r
- ///\r
- /// [Bit 22] EN: enables the corresponding performance counter to commence\r
- /// counting when this bit is set.\r
- ///\r
- UINT32 EN:1;\r
- ///\r
- /// [Bit 23] INV: invert the CMASK.\r
- ///\r
- UINT32 INV:1;\r
- ///\r
- /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
- /// performance counter increments each cycle if the event count is\r
- /// greater than or equal to the CMASK.\r
- ///\r
- UINT32 CMASK:8;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PERFEVTSEL_REGISTER;\r
-\r
-\r
-/**\r
- Current performance state(P-State) operating point (RO). Introduced at\r
- Display Family / Display Model 0F_03H.\r
-\r
- @param ECX MSR_IA32_PERF_STATUS (0x00000198)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PERF_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);\r
- @endcode\r
- @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_IA32_PERF_STATUS 0x00000198\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PERF_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] Current performance State Value.\r
- ///\r
- UINT32 State:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PERF_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- (R/W). Introduced at Display Family / Display Model 0F_03H.\r
-\r
- @param ECX MSR_IA32_PERF_CTL (0x00000199)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PERF_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);\r
- AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.\r
-**/\r
-#define MSR_IA32_PERF_CTL 0x00000199\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PERF_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] Target performance State Value.\r
- ///\r
- UINT32 TargetState:16;\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH\r
- /// (Mobile only).\r
- ///\r
- UINT32 IDA:1;\r
- UINT32 Reserved2:31;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PERF_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r
- Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r
-\r
- @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_CLOCK_MODULATION_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r
- AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
-**/\r
-#define MSR_IA32_CLOCK_MODULATION 0x0000019A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If\r
- /// CPUID.06H:EAX[5] = 1.\r
- ///\r
- UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r
- ///\r
- /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r
- /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 OnDemandClockModulationDutyCycle:3;\r
- ///\r
- /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r
- /// If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 OnDemandClockModulationEnable:1;\r
- UINT32 Reserved1:27;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_CLOCK_MODULATION_REGISTER;\r
-\r
-\r
-/**\r
- Thermal Interrupt Control (R/W) Enables and disables the generation of an\r
- interrupt on temperature transitions detected with the processor's thermal\r
- sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r
- If CPUID.01H:EDX[22] = 1\r
-\r
- @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_THERM_INTERRUPT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);\r
- AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.\r
-**/\r
-#define MSR_IA32_THERM_INTERRUPT 0x0000019B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 HighTempEnable:1;\r
- ///\r
- /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 LowTempEnable:1;\r
- ///\r
- /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 PROCHOT_Enable:1;\r
- ///\r
- /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 FORCEPR_Enable:1;\r
- ///\r
- /// [Bit 4] Critical Temperature Interrupt Enable.\r
- /// If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 CriticalTempEnable:1;\r
- UINT32 Reserved1:3;\r
- ///\r
- /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 Threshold1:7;\r
- ///\r
- /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 Threshold1Enable:1;\r
- ///\r
- /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 Threshold2:7;\r
- ///\r
- /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 Threshold2Enable:1;\r
- ///\r
- /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.\r
- ///\r
- UINT32 PowerLimitNotificationEnable:1;\r
- UINT32 Reserved2:7;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_THERM_INTERRUPT_REGISTER;\r
-\r
-\r
-/**\r
- Thermal Status Information (RO) Contains status information about the\r
- processor's thermal sensor and automatic thermal monitoring facilities. See\r
- Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.\r
-\r
- @param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_THERM_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);\r
- @endcode\r
- @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.\r
-**/\r
-#define MSR_IA32_THERM_STATUS 0x0000019C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_THERM_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- ///\r
- /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 ThermalStatusLog:1;\r
- ///\r
- /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 PROCHOT_FORCEPR_Event:1;\r
- ///\r
- /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 PROCHOT_FORCEPR_Log:1;\r
- ///\r
- /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 CriticalTempStatus:1;\r
- ///\r
- /// [Bit 5] Critical Temperature Status log (R/WC0).\r
- /// If CPUID.01H:EDX[22] = 1.\r
- ///\r
- UINT32 CriticalTempStatusLog:1;\r
- ///\r
- /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.\r
- ///\r
- UINT32 ThermalThreshold1Status:1;\r
- ///\r
- /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r
- ///\r
- UINT32 ThermalThreshold1Log:1;\r
- ///\r
- /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.\r
- ///\r
- UINT32 ThermalThreshold2Status:1;\r
- ///\r
- /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r
- ///\r
- UINT32 ThermalThreshold2Log:1;\r
- ///\r
- /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.\r
- ///\r
- UINT32 PowerLimitStatus:1;\r
- ///\r
- /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.\r
- ///\r
- UINT32 PowerLimitLog:1;\r
- ///\r
- /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r
- ///\r
- UINT32 CurrentLimitStatus:1;\r
- ///\r
- /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r
- ///\r
- UINT32 CurrentLimitLog:1;\r
- ///\r
- /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r
- ///\r
- UINT32 CrossDomainLimitStatus:1;\r
- ///\r
- /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r
- ///\r
- UINT32 CrossDomainLimitLog:1;\r
- ///\r
- /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.\r
- ///\r
- UINT32 DigitalReadout:7;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =\r
- /// 1.\r
- ///\r
- UINT32 ResolutionInDegreesCelsius:4;\r
- ///\r
- /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.\r
- ///\r
- UINT32 ReadingValid:1;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_THERM_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Enable Misc. Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for\r
- /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings\r
- /// are disabled. Introduced at Display Family / Display Model 0F_0H.\r
- ///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
- /// this bit enables the thermal control circuit (TCC) portion of the\r
- /// Intel Thermal Monitor feature. This allows the processor to\r
- /// automatically reduce power consumption in response to TCC activation.\r
- /// 0 = Disabled. Note: In some products clearing this bit might be\r
- /// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r
- /// thermal throttling will still be activated. The default value of this\r
- /// field varies with product. See respective tables where default value is\r
- /// listed. Introduced at Display Family / Display Model 0F_0H.\r
- ///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
- /// monitoring enabled 0 = Performance monitoring disabled. Introduced at\r
- /// Display Family / Display Model 0F_0H.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
- ///\r
- /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't\r
- /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at\r
- /// Display Family / Display Model 0F_0H.\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
- /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r
- /// Family / Display Model 06_0FH.\r
- ///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
- ///\r
- /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced\r
- /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep\r
- /// Technology enabled. If CPUID.01H: ECX[7] =1.\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the\r
- /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This\r
- /// indicates that MONITOR/MWAIT are not supported. Software attempts to\r
- /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit\r
- /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit\r
- /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit\r
- /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it\r
- /// in the default state. Writing this bit when the SSE3 feature flag is\r
- /// set to 0 may generate a #GP exception. Introduced at Display Family /\r
- /// Display Model 0F_03H.\r
- ///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
- ///\r
- /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r
- /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r
- /// question that allows users to specify when the installed OS does not\r
- /// support CPUID functions greater than 2. Before setting this bit, BIOS\r
- /// must execute the CPUID.0H and examine the maximum value returned in\r
- /// EAX[7:0]. If the maximum value is greater than 2, this bit is\r
- /// supported. Otherwise, this bit is not supported. Setting this bit when\r
- /// the maximum value is not greater than 2 may generate a #GP exception.\r
- /// Setting this bit may cause unexpected behavior in software that\r
- /// depends on the availability of CPUID leaves greater than 2. Introduced\r
- /// at Display Family / Display Model 0F_03H.\r
- ///\r
- UINT32 LimitCpuidMaxval:1;\r
- ///\r
- /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
- /// disabled. xTPR messages are optional messages that allow the processor\r
- /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit\r
- /// feature (XD Bit) is disabled and the XD Bit extended feature flag will\r
- /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the\r
- /// Execute Disable Bit feature (if available) allows the OS to enable PAE\r
- /// paging and take advantage of data only pages. BIOS must not alter the\r
- /// contents of this bit location, if XD bit is not supported. Writing\r
- /// this bit to 1 when the XD Bit extended feature flag is set to 0 may\r
- /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.\r
- ///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:29;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.\r
-\r
- @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);\r
- AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
-**/\r
-#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest\r
- /// performance. 15 indicates preference to maximize energy saving.\r
- ///\r
- UINT32 PowerPolicyPreference:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;\r
-\r
-\r
-/**\r
- Package Thermal Status Information (RO) Contains status information about\r
- the package's thermal sensor. See Section 14.8, "Package Level Thermal\r
- Management.". If CPUID.06H: EAX[6] = 1.\r
-\r
- @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);\r
- @endcode\r
- @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.\r
-**/\r
-#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Pkg Thermal Status (RO):.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- ///\r
- /// [Bit 1] Pkg Thermal Status Log (R/W):.\r
- ///\r
- UINT32 ThermalStatusLog:1;\r
- ///\r
- /// [Bit 2] Pkg PROCHOT # event (RO).\r
- ///\r
- UINT32 PROCHOT_Event:1;\r
- ///\r
- /// [Bit 3] Pkg PROCHOT # log (R/WC0).\r
- ///\r
- UINT32 PROCHOT_Log:1;\r
- ///\r
- /// [Bit 4] Pkg Critical Temperature Status (RO).\r
- ///\r
- UINT32 CriticalTempStatus:1;\r
- ///\r
- /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).\r
- ///\r
- UINT32 CriticalTempStatusLog:1;\r
- ///\r
- /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).\r
- ///\r
- UINT32 ThermalThreshold1Status:1;\r
- ///\r
- /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).\r
- ///\r
- UINT32 ThermalThreshold1Log:1;\r
- ///\r
- /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).\r
- ///\r
- UINT32 ThermalThreshold2Status:1;\r
- ///\r
- /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).\r
- ///\r
- UINT32 ThermalThreshold2Log:1;\r
- ///\r
- /// [Bit 10] Pkg Power Limitation Status (RO).\r
- ///\r
- UINT32 PowerLimitStatus:1;\r
- ///\r
- /// [Bit 11] Pkg Power Limitation log (R/WC0).\r
- ///\r
- UINT32 PowerLimitLog:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 22:16] Pkg Digital Readout (RO).\r
- ///\r
- UINT32 DigitalReadout:7;\r
- UINT32 Reserved2:9;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of\r
- an interrupt on temperature transitions detected with the package's thermal\r
- sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:\r
- EAX[6] = 1.\r
-\r
- @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);\r
- AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.\r
-**/\r
-#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Pkg High-Temperature Interrupt Enable.\r
- ///\r
- UINT32 HighTempEnable:1;\r
- ///\r
- /// [Bit 1] Pkg Low-Temperature Interrupt Enable.\r
- ///\r
- UINT32 LowTempEnable:1;\r
- ///\r
- /// [Bit 2] Pkg PROCHOT# Interrupt Enable.\r
- ///\r
- UINT32 PROCHOT_Enable:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 4] Pkg Overheat Interrupt Enable.\r
- ///\r
- UINT32 OverheatEnable:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bits 14:8] Pkg Threshold #1 Value.\r
- ///\r
- UINT32 Threshold1:7;\r
- ///\r
- /// [Bit 15] Pkg Threshold #1 Interrupt Enable.\r
- ///\r
- UINT32 Threshold1Enable:1;\r
- ///\r
- /// [Bits 22:16] Pkg Threshold #2 Value.\r
- ///\r
- UINT32 Threshold2:7;\r
- ///\r
- /// [Bit 23] Pkg Threshold #2 Interrupt Enable.\r
- ///\r
- UINT32 Threshold2Enable:1;\r
- ///\r
- /// [Bit 24] Pkg Power Limit Notification Enable.\r
- ///\r
- UINT32 PowerLimitNotificationEnable:1;\r
- UINT32 Reserved3:7;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;\r
-\r
-\r
-/**\r
- Trace/Profile Resource Control (R/W). Introduced at Display Family / Display\r
- Model 06_0EH.\r
-\r
- @param ECX MSR_IA32_DEBUGCTL (0x000001D9)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_DEBUGCTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);\r
- AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.\r
-**/\r
-#define MSR_IA32_DEBUGCTL 0x000001D9\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_DEBUGCTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a\r
- /// running trace of the most recent branches taken by the processor in\r
- /// the LBR stack. Introduced at Display Family / Display Model 06_01H.\r
- ///\r
- UINT32 LBR:1;\r
- ///\r
- /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat\r
- /// EFLAGS.TF as single-step on branches instead of single-step on\r
- /// instructions. Introduced at Display Family / Display Model 06_01H.\r
- ///\r
- UINT32 BTF:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be\r
- /// sent. Introduced at Display Family / Display Model 06_0EH.\r
- ///\r
- UINT32 TR:1;\r
- ///\r
- /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to\r
- /// be logged in a BTS buffer. Introduced at Display Family / Display\r
- /// Model 06_0EH.\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular\r
- /// fashion. When this bit is set, an interrupt is generated by the BTS\r
- /// facility when the BTS buffer is full. Introduced at Display Family /\r
- /// Display Model 06_0EH.\r
- ///\r
- UINT32 BTINT:1;\r
- ///\r
- /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.\r
- /// Introduced at Display Family / Display Model 06_0FH.\r
- ///\r
- UINT32 BTS_OFF_OS:1;\r
- ///\r
- /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.\r
- /// Introduced at Display Family / Display Model 06_0FH.\r
- ///\r
- UINT32 BTS_OFF_USR:1;\r
- ///\r
- /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a\r
- /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r
- ///\r
- UINT32 FREEZE_LBRS_ON_PMI:1;\r
- ///\r
- /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the\r
- /// global counter control MSR are frozen (address 38FH) on a PMI request.\r
- /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r
- ///\r
- UINT32 FREEZE_PERFMON_ON_PMI:1;\r
- ///\r
- /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to\r
- /// receive and generate PMI on behalf of the uncore. Introduced at\r
- /// Display Family / Display Model 06_1AH.\r
- ///\r
- UINT32 ENABLE_UNCORE_PMI:1;\r
- ///\r
- /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace\r
- /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.\r
- ///\r
- UINT32 FREEZE_WHILE_SMM:1;\r
- ///\r
- /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If\r
- /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).\r
- ///\r
- UINT32 RTM_DEBUG:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_DEBUGCTL_REGISTER;\r
-\r
-\r
-/**\r
- SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.\r
- If IA32_MTRRCAP.SMRR[11] = 1.\r
-\r
- @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);\r
- AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.\r
-**/\r
-#define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Type. Specifies memory type of the range.\r
- ///\r
- UINT32 Type:8;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r
- ///\r
- UINT32 PhysBase:20;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_SMRR_PHYSBASE_REGISTER;\r
-\r
-\r
-/**\r
- SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If\r
- IA32_MTRRCAP[SMRR] = 1.\r
-\r
- @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);\r
- AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.\r
-**/\r
-#define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:11;\r
- ///\r
- /// [Bit 11] Valid Enable range mask.\r
- ///\r
- UINT32 Valid:1;\r
- ///\r
- /// [Bits 31:12] PhysMask SMRR address range mask.\r
- ///\r
- UINT32 PhysMask:20;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_SMRR_PHYSMASK_REGISTER;\r
-\r
-\r
-/**\r
- DCA Capability (R). If CPUID.01H: ECX[18] = 1.\r
-\r
- @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);\r
- @endcode\r
- @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.\r
-**/\r
-#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r
-\r
-\r
-/**\r
- If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.\r
-\r
- @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);\r
- AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);\r
- @endcode\r
- @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.\r
-**/\r
-#define MSR_IA32_CPU_DCA_CAP 0x000001F9\r
-\r
-\r
-/**\r
- DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.\r
-\r
- @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_DCA_0_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);\r
- AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.\r
-**/\r
-#define MSR_IA32_DCA_0_CAP 0x000001FA\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_DCA_0_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no\r
- /// defeatures are set.\r
- ///\r
- UINT32 DCA_ACTIVE:1;\r
- ///\r
- /// [Bits 2:1] TRANSACTION.\r
- ///\r
- UINT32 TRANSACTION:2;\r
- ///\r
- /// [Bits 6:3] DCA_TYPE.\r
- ///\r
- UINT32 DCA_TYPE:4;\r
- ///\r
- /// [Bits 10:7] DCA_QUEUE_SIZE.\r
- ///\r
- UINT32 DCA_QUEUE_SIZE:4;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW\r
- /// side-effect.\r
- ///\r
- UINT32 DCA_DELAY:4;\r
- UINT32 Reserved2:7;\r
- ///\r
- /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.\r
- ///\r
- UINT32 SW_BLOCK:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).\r
- ///\r
- UINT32 HW_BLOCK:1;\r
- UINT32 Reserved4:5;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_DCA_0_CAP_REGISTER;\r
-\r
-\r
-/**\r
- MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".\r
- If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r
-\r
- @param ECX MSR_IA32_MTRR_PHYSBASEn\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.\r
- MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.\r
- MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.\r
- MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.\r
- MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.\r
- MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.\r
- MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.\r
- MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.\r
- MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.\r
- MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r
-#define MSR_IA32_MTRR_PHYSBASE1 0x00000202\r
-#define MSR_IA32_MTRR_PHYSBASE2 0x00000204\r
-#define MSR_IA32_MTRR_PHYSBASE3 0x00000206\r
-#define MSR_IA32_MTRR_PHYSBASE4 0x00000208\r
-#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A\r
-#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C\r
-#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E\r
-#define MSR_IA32_MTRR_PHYSBASE8 0x00000210\r
-#define MSR_IA32_MTRR_PHYSBASE9 0x00000212\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to\r
- #MSR_IA32_MTRR_PHYSBASE9\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Type. Specifies memory type of the range.\r
- ///\r
- UINT32 Type:8;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 31:12] PhysBase. MTRR physical Base Address.\r
- ///\r
- UINT32 PhysBase:20;\r
- ///\r
- /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.\r
- /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r
- /// maximum physical address range supported by the processor. It is\r
- /// reported by CPUID leaf function 80000008H. If CPUID does not support\r
- /// leaf 80000008H, the processor supports 36-bit physical address size,\r
- /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r
- ///\r
- UINT32 PhysBaseHi:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_MTRR_PHYSBASE_REGISTER;\r
-\r
-\r
-/**\r
- MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".\r
- If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r
-\r
- @param ECX MSR_IA32_MTRR_PHYSMASKn\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.\r
- MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.\r
- MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.\r
- MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.\r
- MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.\r
- MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.\r
- MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.\r
- MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.\r
- MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.\r
- MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r
-#define MSR_IA32_MTRR_PHYSMASK1 0x00000203\r
-#define MSR_IA32_MTRR_PHYSMASK2 0x00000205\r
-#define MSR_IA32_MTRR_PHYSMASK3 0x00000207\r
-#define MSR_IA32_MTRR_PHYSMASK4 0x00000209\r
-#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B\r
-#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D\r
-#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F\r
-#define MSR_IA32_MTRR_PHYSMASK8 0x00000211\r
-#define MSR_IA32_MTRR_PHYSMASK9 0x00000213\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to\r
- #MSR_IA32_MTRR_PHYSMASK9\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:11;\r
- ///\r
- /// [Bit 11] Valid Enable range mask.\r
- ///\r
- UINT32 V:1;\r
- ///\r
- /// [Bits 31:12] PhysMask. MTRR address range mask.\r
- ///\r
- UINT32 PhysMask:20;\r
- ///\r
- /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.\r
- /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r
- /// maximum physical address range supported by the processor. It is\r
- /// reported by CPUID leaf function 80000008H. If CPUID does not support\r
- /// leaf 80000008H, the processor supports 36-bit physical address size,\r
- /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r
- ///\r
- UINT32 PhysMaskHi:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_MTRR_PHYSMASK_REGISTER;\r
-\r
-\r
-/**\r
- MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r
-\r
-\r
-/**\r
- MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r
-\r
-\r
-/**\r
- MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r
-\r
-\r
-/**\r
- See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r
-\r
-\r
-/**\r
- MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r
-\r
-\r
-/**\r
- MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r
-\r
-\r
-/**\r
- MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r
-\r
-\r
-/**\r
- MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r
-\r
-\r
-/**\r
- MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r
-\r
-\r
-/**\r
- MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r
-\r
-\r
-/**\r
- MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);\r
- @endcode\r
- @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r
-\r
-\r
-/**\r
- IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.\r
-\r
- @param ECX MSR_IA32_PAT (0x00000277)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PAT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PAT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PAT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);\r
- AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PAT is defined as IA32_PAT in SDM.\r
-**/\r
-#define MSR_IA32_PAT 0x00000277\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PAT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] PA0.\r
- ///\r
- UINT32 PA0:3;\r
- UINT32 Reserved1:5;\r
- ///\r
- /// [Bits 10:8] PA1.\r
- ///\r
- UINT32 PA1:3;\r
- UINT32 Reserved2:5;\r
- ///\r
- /// [Bits 18:16] PA2.\r
- ///\r
- UINT32 PA2:3;\r
- UINT32 Reserved3:5;\r
- ///\r
- /// [Bits 26:24] PA3.\r
- ///\r
- UINT32 PA3:3;\r
- UINT32 Reserved4:5;\r
- ///\r
- /// [Bits 34:32] PA4.\r
- ///\r
- UINT32 PA4:3;\r
- UINT32 Reserved5:5;\r
- ///\r
- /// [Bits 42:40] PA5.\r
- ///\r
- UINT32 PA5:3;\r
- UINT32 Reserved6:5;\r
- ///\r
- /// [Bits 50:48] PA6.\r
- ///\r
- UINT32 PA6:3;\r
- UINT32 Reserved7:5;\r
- ///\r
- /// [Bits 58:56] PA7.\r
- ///\r
- UINT32 PA7:3;\r
- UINT32 Reserved8:5;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PAT_REGISTER;\r
-\r
-\r
-/**\r
- Provides the programming interface to use corrected MC error signaling\r
- capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.\r
-\r
- @param ECX MSR_IA32_MCn_CTL2\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_MC_CTL2_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_MC_CTL2_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_MC_CTL2_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);\r
- AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.\r
- MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.\r
- MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.\r
- MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.\r
- MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r
- MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.\r
- MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.\r
- MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.\r
- MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.\r
- MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.\r
- MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.\r
- MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.\r
- MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.\r
- MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.\r
- MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.\r
- MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.\r
- MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.\r
- MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.\r
- MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.\r
- MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.\r
- MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.\r
- MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.\r
- MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.\r
- MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.\r
- MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.\r
- MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.\r
- MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.\r
- MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.\r
- MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.\r
- MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.\r
- MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.\r
- MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_MC0_CTL2 0x00000280\r
-#define MSR_IA32_MC1_CTL2 0x00000281\r
-#define MSR_IA32_MC2_CTL2 0x00000282\r
-#define MSR_IA32_MC3_CTL2 0x00000283\r
-#define MSR_IA32_MC4_CTL2 0x00000284\r
-#define MSR_IA32_MC5_CTL2 0x00000285\r
-#define MSR_IA32_MC6_CTL2 0x00000286\r
-#define MSR_IA32_MC7_CTL2 0x00000287\r
-#define MSR_IA32_MC8_CTL2 0x00000288\r
-#define MSR_IA32_MC9_CTL2 0x00000289\r
-#define MSR_IA32_MC10_CTL2 0x0000028A\r
-#define MSR_IA32_MC11_CTL2 0x0000028B\r
-#define MSR_IA32_MC12_CTL2 0x0000028C\r
-#define MSR_IA32_MC13_CTL2 0x0000028D\r
-#define MSR_IA32_MC14_CTL2 0x0000028E\r
-#define MSR_IA32_MC15_CTL2 0x0000028F\r
-#define MSR_IA32_MC16_CTL2 0x00000290\r
-#define MSR_IA32_MC17_CTL2 0x00000291\r
-#define MSR_IA32_MC18_CTL2 0x00000292\r
-#define MSR_IA32_MC19_CTL2 0x00000293\r
-#define MSR_IA32_MC20_CTL2 0x00000294\r
-#define MSR_IA32_MC21_CTL2 0x00000295\r
-#define MSR_IA32_MC22_CTL2 0x00000296\r
-#define MSR_IA32_MC23_CTL2 0x00000297\r
-#define MSR_IA32_MC24_CTL2 0x00000298\r
-#define MSR_IA32_MC25_CTL2 0x00000299\r
-#define MSR_IA32_MC26_CTL2 0x0000029A\r
-#define MSR_IA32_MC27_CTL2 0x0000029B\r
-#define MSR_IA32_MC28_CTL2 0x0000029C\r
-#define MSR_IA32_MC29_CTL2 0x0000029D\r
-#define MSR_IA32_MC30_CTL2 0x0000029E\r
-#define MSR_IA32_MC31_CTL2 0x0000029F\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2\r
- to #MSR_IA32_MC31_CTL2\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] Corrected error count threshold.\r
- ///\r
- UINT32 CorrectedErrorCountThreshold:15;\r
- UINT32 Reserved1:15;\r
- ///\r
- /// [Bit 30] CMCI_EN.\r
- ///\r
- UINT32 CMCI_EN:1;\r
- UINT32 Reserved2:1;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_MC_CTL2_REGISTER;\r
-\r
-\r
-/**\r
- MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.\r
-\r
- @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
- AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.\r
-**/\r
-#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Default Memory Type.\r
- ///\r
- UINT32 Type:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 10] Fixed Range MTRR Enable.\r
- ///\r
- UINT32 FE:1;\r
- ///\r
- /// [Bit 11] MTRR Enable.\r
- ///\r
- UINT32 E:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_MTRR_DEF_TYPE_REGISTER;\r
-\r
-\r
-/**\r
- Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If\r
- CPUID.0AH: EDX[4:0] > 0.\r
-\r
- @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);\r
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);\r
- @endcode\r
- @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.\r
-**/\r
-#define MSR_IA32_FIXED_CTR0 0x00000309\r
-\r
-\r
-/**\r
- Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r
- CPUID.0AH: EDX[4:0] > 1.\r
-\r
- @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);\r
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);\r
- @endcode\r
- @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.\r
-**/\r
-#define MSR_IA32_FIXED_CTR1 0x0000030A\r
-\r
-\r
-/**\r
- Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r
- CPUID.0AH: EDX[4:0] > 2.\r
-\r
- @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);\r
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);\r
- @endcode\r
- @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.\r
-**/\r
-#define MSR_IA32_FIXED_CTR2 0x0000030B\r
-\r
-\r
-/**\r
- RO. If CPUID.01H: ECX[15] = 1.\r
-\r
- @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);\r
- AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.\r
-**/\r
-#define MSR_IA32_PERF_CAPABILITIES 0x00000345\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 5:0] LBR format.\r
- ///\r
- UINT32 LBR_FMT:6;\r
- ///\r
- /// [Bit 6] PEBS Trap.\r
- ///\r
- UINT32 PEBS_TRAP:1;\r
- ///\r
- /// [Bit 7] PEBSSaveArchRegs.\r
- ///\r
- UINT32 PEBS_ARCH_REG:1;\r
- ///\r
- /// [Bits 11:8] PEBS Record Format.\r
- ///\r
- UINT32 PEBS_REC_FMT:4;\r
- ///\r
- /// [Bit 12] 1: Freeze while SMM is supported.\r
- ///\r
- UINT32 SMM_FREEZE:1;\r
- ///\r
- /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.\r
- ///\r
- UINT32 FW_WRITE:1;\r
- UINT32 Reserved1:18;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PERF_CAPABILITIES_REGISTER;\r
-\r
-\r
-/**\r
- Fixed-Function Performance Counter Control (R/W) Counter increments while\r
- the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with\r
- the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]\r
- > 1.\r
-\r
- @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);\r
- AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.\r
-**/\r
-#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.\r
- ///\r
- UINT32 EN0_OS:1;\r
- ///\r
- /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.\r
- ///\r
- UINT32 EN0_Usr:1;\r
- ///\r
- /// [Bit 2] AnyThread: When set to 1, it enables counting the associated\r
- /// event conditions occurring across all logical processors sharing a\r
- /// processor core. When set to 0, the counter only increments the\r
- /// associated event conditions occurring in the logical processor which\r
- /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
- ///\r
- UINT32 AnyThread0:1;\r
- ///\r
- /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.\r
- ///\r
- UINT32 EN0_PMI:1;\r
- ///\r
- /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.\r
- ///\r
- UINT32 EN1_OS:1;\r
- ///\r
- /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.\r
- ///\r
- UINT32 EN1_Usr:1;\r
- ///\r
- /// [Bit 6] AnyThread: When set to 1, it enables counting the associated\r
- /// event conditions occurring across all logical processors sharing a\r
- /// processor core. When set to 0, the counter only increments the\r
- /// associated event conditions occurring in the logical processor which\r
- /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
- ///\r
- UINT32 AnyThread1:1;\r
- ///\r
- /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.\r
- ///\r
- UINT32 EN1_PMI:1;\r
- ///\r
- /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.\r
- ///\r
- UINT32 EN2_OS:1;\r
- ///\r
- /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.\r
- ///\r
- UINT32 EN2_Usr:1;\r
- ///\r
- /// [Bit 10] AnyThread: When set to 1, it enables counting the associated\r
- /// event conditions occurring across all logical processors sharing a\r
- /// processor core. When set to 0, the counter only increments the\r
- /// associated event conditions occurring in the logical processor which\r
- /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
- ///\r
- UINT32 AnyThread2:1;\r
- ///\r
- /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.\r
- ///\r
- UINT32 EN2_PMI:1;\r
- UINT32 Reserved1:20;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_FIXED_CTR_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.\r
-\r
- @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);\r
- @endcode\r
- @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:\r
- /// EAX[15:8] > 0.\r
- ///\r
- UINT32 Ovf_PMC0:1;\r
- ///\r
- /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:\r
- /// EAX[15:8] > 1.\r
- ///\r
- UINT32 Ovf_PMC1:1;\r
- ///\r
- /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:\r
- /// EAX[15:8] > 2.\r
- ///\r
- UINT32 Ovf_PMC2:1;\r
- ///\r
- /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:\r
- /// EAX[15:8] > 3.\r
- ///\r
- UINT32 Ovf_PMC3:1;\r
- UINT32 Reserved1:28;\r
- ///\r
- /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If\r
- /// CPUID.0AH: EAX[7:0] > 1.\r
- ///\r
- UINT32 Ovf_FixedCtr0:1;\r
- ///\r
- /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If\r
- /// CPUID.0AH: EAX[7:0] > 1.\r
- ///\r
- UINT32 Ovf_FixedCtr1:1;\r
- ///\r
- /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If\r
- /// CPUID.0AH: EAX[7:0] > 1.\r
- ///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
- ///\r
- /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory\r
- /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r
- /// && IA32_RTIT_CTL.ToPA = 1.\r
- ///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 58] LBR_Frz: LBRs are frozen due to -\r
- /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If\r
- /// CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 LBR_Frz:1;\r
- ///\r
- /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due\r
- /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU\r
- /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 CTR_Frz:1;\r
- ///\r
- /// [Bit 60] ASCI: Data in the performance counters in the core PMU may\r
- /// include contributions from the direct or indirect operation intel SGX\r
- /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.\r
- ///\r
- UINT32 ASCI:1;\r
- ///\r
- /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:\r
- /// EAX[7:0] > 2.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:\r
- /// EAX[7:0] > 0.\r
- ///\r
- UINT32 OvfBuf:1;\r
- ///\r
- /// [Bit 63] CondChgd: status bits of this register has changed. If\r
- /// CPUID.0AH: EAX[7:0] > 0.\r
- ///\r
- UINT32 CondChgd:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Global Performance Counter Control (R/W) Counter increments while the result\r
- of ANDing respective enable bit in this MSR with the corresponding OS or USR\r
- bits in the general-purpose or fixed counter control MSR is true. If\r
- CPUID.0AH: EAX[7:0] > 0.\r
-\r
- @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);\r
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
-**/\r
-#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
-///\r
- struct {\r
- ///\r
- /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.\r
- /// Enable bitmask. Only the first n-1 bits are valid.\r
- /// Bits n..31 are reserved.\r
- ///\r
- UINT32 EN_PMCn:32;\r
- ///\r
- /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.\r
- /// Enable bitmask. Only the first n-1 bits are valid.\r
- /// Bits 31:n are reserved.\r
- ///\r
- UINT32 EN_FIXED_CTRn:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >\r
- 0 && CPUID.0AH: EAX[7:0] <= 3.\r
-\r
- @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r
- /// Clear bitmask. Only the first n-1 bits are valid.\r
- /// Bits 31:n are reserved.\r
- ///\r
- UINT32 Ovf_PMCn:32;\r
- ///\r
- /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r
- /// If CPUID.0AH: EDX[4:0] > n.\r
- /// Clear bitmask. Only the first n-1 bits are valid.\r
- /// Bits 22:n are reserved.\r
- ///\r
- UINT32 Ovf_FIXED_CTRn:23;\r
- ///\r
- /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r
- /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.\r
- ///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved2:5;\r
- ///\r
- /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r
- /// Display Model 06_2EH.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r
- ///\r
- UINT32 OvfBuf:1;\r
- ///\r
- /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r
- ///\r
- UINT32 CondChgd:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:\r
- EAX[7:0] > 3.\r
-\r
- @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);\r
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
-**/\r
-#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r
- /// Clear bitmask. Only the first n-1 bits are valid.\r
- /// Bits 31:n are reserved.\r
- ///\r
- UINT32 Ovf_PMCn:32;\r
- ///\r
- /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r
- /// If CPUID.0AH: EDX[4:0] > n.\r
- /// Clear bitmask. Only the first n-1 bits are valid.\r
- /// Bits 22:n are reserved.\r
- ///\r
- UINT32 Ovf_FIXED_CTRn:23;\r
- ///\r
- /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r
- /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.\r
- ///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved2:2;\r
- ///\r
- /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 LBR_Frz:1;\r
- ///\r
- /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 CTR_Frz:1;\r
- ///\r
- /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 ASCI:1;\r
- ///\r
- /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r
- /// Display Model 06_2EH.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r
- ///\r
- UINT32 OvfBuf:1;\r
- ///\r
- /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r
- ///\r
- UINT32 CondChgd:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
-\r
-\r
-/**\r
- Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:\r
- EAX[7:0] > 3.\r
-\r
- @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);\r
- AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
-**/\r
-#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.\r
- /// Set bitmask. Only the first n-1 bits are valid.\r
- /// Bits 31:n are reserved.\r
- ///\r
- UINT32 Ovf_PMCn:32;\r
- ///\r
- /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.\r
- /// If CPUID.0AH: EAX[7:0] > n.\r
- /// Set bitmask. Only the first n-1 bits are valid.\r
- /// Bits 22:n are reserved.\r
- ///\r
- UINT32 Ovf_FIXED_CTRn:23;\r
- ///\r
- /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved2:2;\r
- ///\r
- /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 LBR_Frz:1;\r
- ///\r
- /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 CTR_Frz:1;\r
- ///\r
- /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 ASCI:1;\r
- ///\r
- /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.\r
- ///\r
- UINT32 OvfBuf:1;\r
- UINT32 Reserved3:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
-\r
-\r
-/**\r
- Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >\r
- 3.\r
-\r
- @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);\r
- @endcode\r
- @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.\r
-**/\r
-#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.\r
- /// Status bitmask. Only the first n-1 bits are valid.\r
- /// Bits 31:n are reserved.\r
- ///\r
- UINT32 IA32_PERFEVTSELn:32;\r
- ///\r
- /// [Bits 62:32] IA32_FIXED_CTRn in use.\r
- /// If CPUID.0AH: EAX[7:0] > n.\r
- /// Status bitmask. Only the first n-1 bits are valid.\r
- /// Bits 30:n are reserved.\r
- ///\r
- UINT32 IA32_FIXED_CTRn:31;\r
- ///\r
- /// [Bit 63] PMI in use.\r
- ///\r
- UINT32 PMI:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;\r
-\r
-\r
-/**\r
- PEBS Control (R/W).\r
-\r
- @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PEBS_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.\r
-**/\r
-#define MSR_IA32_PEBS_ENABLE 0x000003F1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /\r
- /// Display Model 06_0FH.\r
- ///\r
- UINT32 Enable:1;\r
- ///\r
- /// [Bits 3:1] Reserved or Model specific.\r
- ///\r
- UINT32 Reserved1:3;\r
- UINT32 Reserved2:28;\r
- ///\r
- /// [Bits 35:32] Reserved or Model specific.\r
- ///\r
- UINT32 Reserved3:4;\r
- UINT32 Reserved4:28;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PEBS_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- MCn_CTL. If IA32_MCG_CAP.CNT > n.\r
-\r
- @param ECX MSR_IA32_MCn_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);\r
- AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);\r
- @endcode\r
- @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.\r
- MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.\r
- MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.\r
- MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.\r
- MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r
- MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.\r
- MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.\r
- MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.\r
- MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.\r
- MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.\r
- MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.\r
- MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.\r
- MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.\r
- MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.\r
- MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.\r
- MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.\r
- MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.\r
- MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.\r
- MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.\r
- MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.\r
- MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.\r
- MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.\r
- MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.\r
- MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.\r
- MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.\r
- MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.\r
- MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.\r
- MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.\r
- MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_MC0_CTL 0x00000400\r
-#define MSR_IA32_MC1_CTL 0x00000404\r
-#define MSR_IA32_MC2_CTL 0x00000408\r
-#define MSR_IA32_MC3_CTL 0x0000040C\r
-#define MSR_IA32_MC4_CTL 0x00000410\r
-#define MSR_IA32_MC5_CTL 0x00000414\r
-#define MSR_IA32_MC6_CTL 0x00000418\r
-#define MSR_IA32_MC7_CTL 0x0000041C\r
-#define MSR_IA32_MC8_CTL 0x00000420\r
-#define MSR_IA32_MC9_CTL 0x00000424\r
-#define MSR_IA32_MC10_CTL 0x00000428\r
-#define MSR_IA32_MC11_CTL 0x0000042C\r
-#define MSR_IA32_MC12_CTL 0x00000430\r
-#define MSR_IA32_MC13_CTL 0x00000434\r
-#define MSR_IA32_MC14_CTL 0x00000438\r
-#define MSR_IA32_MC15_CTL 0x0000043C\r
-#define MSR_IA32_MC16_CTL 0x00000440\r
-#define MSR_IA32_MC17_CTL 0x00000444\r
-#define MSR_IA32_MC18_CTL 0x00000448\r
-#define MSR_IA32_MC19_CTL 0x0000044C\r
-#define MSR_IA32_MC20_CTL 0x00000450\r
-#define MSR_IA32_MC21_CTL 0x00000454\r
-#define MSR_IA32_MC22_CTL 0x00000458\r
-#define MSR_IA32_MC23_CTL 0x0000045C\r
-#define MSR_IA32_MC24_CTL 0x00000460\r
-#define MSR_IA32_MC25_CTL 0x00000464\r
-#define MSR_IA32_MC26_CTL 0x00000468\r
-#define MSR_IA32_MC27_CTL 0x0000046C\r
-#define MSR_IA32_MC28_CTL 0x00000470\r
-/// @}\r
-\r
-\r
-/**\r
- MCn_STATUS. If IA32_MCG_CAP.CNT > n.\r
-\r
- @param ECX MSR_IA32_MCn_STATUS\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);\r
- AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);\r
- @endcode\r
- @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.\r
- MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.\r
- MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.\r
- MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.\r
- MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.\r
- MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.\r
- MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.\r
- MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.\r
- MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.\r
- MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.\r
- MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.\r
- MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.\r
- MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.\r
- MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.\r
- MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.\r
- MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.\r
- MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.\r
- MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.\r
- MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.\r
- MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.\r
- MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.\r
- MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.\r
- MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.\r
- MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.\r
- MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.\r
- MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.\r
- MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.\r
- MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.\r
- MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_MC0_STATUS 0x00000401\r
-#define MSR_IA32_MC1_STATUS 0x00000405\r
-#define MSR_IA32_MC2_STATUS 0x00000409\r
-#define MSR_IA32_MC3_STATUS 0x0000040D\r
-#define MSR_IA32_MC4_STATUS 0x00000411\r
-#define MSR_IA32_MC5_STATUS 0x00000415\r
-#define MSR_IA32_MC6_STATUS 0x00000419\r
-#define MSR_IA32_MC7_STATUS 0x0000041D\r
-#define MSR_IA32_MC8_STATUS 0x00000421\r
-#define MSR_IA32_MC9_STATUS 0x00000425\r
-#define MSR_IA32_MC10_STATUS 0x00000429\r
-#define MSR_IA32_MC11_STATUS 0x0000042D\r
-#define MSR_IA32_MC12_STATUS 0x00000431\r
-#define MSR_IA32_MC13_STATUS 0x00000435\r
-#define MSR_IA32_MC14_STATUS 0x00000439\r
-#define MSR_IA32_MC15_STATUS 0x0000043D\r
-#define MSR_IA32_MC16_STATUS 0x00000441\r
-#define MSR_IA32_MC17_STATUS 0x00000445\r
-#define MSR_IA32_MC18_STATUS 0x00000449\r
-#define MSR_IA32_MC19_STATUS 0x0000044D\r
-#define MSR_IA32_MC20_STATUS 0x00000451\r
-#define MSR_IA32_MC21_STATUS 0x00000455\r
-#define MSR_IA32_MC22_STATUS 0x00000459\r
-#define MSR_IA32_MC23_STATUS 0x0000045D\r
-#define MSR_IA32_MC24_STATUS 0x00000461\r
-#define MSR_IA32_MC25_STATUS 0x00000465\r
-#define MSR_IA32_MC26_STATUS 0x00000469\r
-#define MSR_IA32_MC27_STATUS 0x0000046D\r
-#define MSR_IA32_MC28_STATUS 0x00000471\r
-/// @}\r
-\r
-\r
-/**\r
- MCn_ADDR. If IA32_MCG_CAP.CNT > n.\r
-\r
- @param ECX MSR_IA32_MCn_ADDR\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);\r
- AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);\r
- @endcode\r
- @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.\r
- MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.\r
- MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.\r
- MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.\r
- MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.\r
- MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.\r
- MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.\r
- MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.\r
- MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.\r
- MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.\r
- MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.\r
- MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.\r
- MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.\r
- MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.\r
- MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.\r
- MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.\r
- MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.\r
- MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.\r
- MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.\r
- MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.\r
- MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.\r
- MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.\r
- MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.\r
- MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.\r
- MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.\r
- MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.\r
- MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.\r
- MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.\r
- MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_MC0_ADDR 0x00000402\r
-#define MSR_IA32_MC1_ADDR 0x00000406\r
-#define MSR_IA32_MC2_ADDR 0x0000040A\r
-#define MSR_IA32_MC3_ADDR 0x0000040E\r
-#define MSR_IA32_MC4_ADDR 0x00000412\r
-#define MSR_IA32_MC5_ADDR 0x00000416\r
-#define MSR_IA32_MC6_ADDR 0x0000041A\r
-#define MSR_IA32_MC7_ADDR 0x0000041E\r
-#define MSR_IA32_MC8_ADDR 0x00000422\r
-#define MSR_IA32_MC9_ADDR 0x00000426\r
-#define MSR_IA32_MC10_ADDR 0x0000042A\r
-#define MSR_IA32_MC11_ADDR 0x0000042E\r
-#define MSR_IA32_MC12_ADDR 0x00000432\r
-#define MSR_IA32_MC13_ADDR 0x00000436\r
-#define MSR_IA32_MC14_ADDR 0x0000043A\r
-#define MSR_IA32_MC15_ADDR 0x0000043E\r
-#define MSR_IA32_MC16_ADDR 0x00000442\r
-#define MSR_IA32_MC17_ADDR 0x00000446\r
-#define MSR_IA32_MC18_ADDR 0x0000044A\r
-#define MSR_IA32_MC19_ADDR 0x0000044E\r
-#define MSR_IA32_MC20_ADDR 0x00000452\r
-#define MSR_IA32_MC21_ADDR 0x00000456\r
-#define MSR_IA32_MC22_ADDR 0x0000045A\r
-#define MSR_IA32_MC23_ADDR 0x0000045E\r
-#define MSR_IA32_MC24_ADDR 0x00000462\r
-#define MSR_IA32_MC25_ADDR 0x00000466\r
-#define MSR_IA32_MC26_ADDR 0x0000046A\r
-#define MSR_IA32_MC27_ADDR 0x0000046E\r
-#define MSR_IA32_MC28_ADDR 0x00000472\r
-/// @}\r
-\r
-\r
-/**\r
- MCn_MISC. If IA32_MCG_CAP.CNT > n.\r
-\r
- @param ECX MSR_IA32_MCn_MISC\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);\r
- AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);\r
- @endcode\r
- @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.\r
- MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.\r
- MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.\r
- MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.\r
- MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.\r
- MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.\r
- MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
- MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.\r
- MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.\r
- MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.\r
- MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.\r
- MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.\r
- MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.\r
- MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.\r
- MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.\r
- MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.\r
- MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.\r
- MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.\r
- MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.\r
- MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.\r
- MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.\r
- MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.\r
- MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.\r
- MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.\r
- MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.\r
- MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.\r
- MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.\r
- MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.\r
- MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_MC0_MISC 0x00000403\r
-#define MSR_IA32_MC1_MISC 0x00000407\r
-#define MSR_IA32_MC2_MISC 0x0000040B\r
-#define MSR_IA32_MC3_MISC 0x0000040F\r
-#define MSR_IA32_MC4_MISC 0x00000413\r
-#define MSR_IA32_MC5_MISC 0x00000417\r
-#define MSR_IA32_MC6_MISC 0x0000041B\r
-#define MSR_IA32_MC7_MISC 0x0000041F\r
-#define MSR_IA32_MC8_MISC 0x00000423\r
-#define MSR_IA32_MC9_MISC 0x00000427\r
-#define MSR_IA32_MC10_MISC 0x0000042B\r
-#define MSR_IA32_MC11_MISC 0x0000042F\r
-#define MSR_IA32_MC12_MISC 0x00000433\r
-#define MSR_IA32_MC13_MISC 0x00000437\r
-#define MSR_IA32_MC14_MISC 0x0000043B\r
-#define MSR_IA32_MC15_MISC 0x0000043F\r
-#define MSR_IA32_MC16_MISC 0x00000443\r
-#define MSR_IA32_MC17_MISC 0x00000447\r
-#define MSR_IA32_MC18_MISC 0x0000044B\r
-#define MSR_IA32_MC19_MISC 0x0000044F\r
-#define MSR_IA32_MC20_MISC 0x00000453\r
-#define MSR_IA32_MC21_MISC 0x00000457\r
-#define MSR_IA32_MC22_MISC 0x0000045B\r
-#define MSR_IA32_MC23_MISC 0x0000045F\r
-#define MSR_IA32_MC24_MISC 0x00000463\r
-#define MSR_IA32_MC25_MISC 0x00000467\r
-#define MSR_IA32_MC26_MISC 0x0000046B\r
-#define MSR_IA32_MC27_MISC 0x0000046F\r
-#define MSR_IA32_MC28_MISC 0x00000473\r
-/// @}\r
-\r
-\r
-/**\r
- Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic\r
- VMX Information.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_BASIC (0x00000480)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_VMX_BASIC_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r
- @endcode\r
- @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r
-**/\r
-#define MSR_IA32_VMX_BASIC 0x00000480\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 30:0] VMCS revision identifier used by the processor. Processors\r
- /// that use the same VMCS revision identifier use the same size for VMCS\r
- /// regions (see subsequent item on bits 44:32).\r
- ///\r
- /// @note Earlier versions of this manual specified that the VMCS revision\r
- /// identifier was a 32-bit field in bits 31:0 of this MSR. For all\r
- /// processors produced prior to this change, bit 31 of this MSR was read\r
- /// as 0.\r
- ///\r
- UINT32 VmcsRevisonId:31;\r
- UINT32 MustBeZero:1;\r
- ///\r
- /// [Bit 44:32] Reports the number of bytes that software should allocate\r
- /// for the VMXON region and any VMCS region. It is a value greater than\r
- /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r
- ///\r
- UINT32 VmcsSize:13;\r
- UINT32 Reserved1:3;\r
- ///\r
- /// [Bit 48] Indicates the width of the physical addresses that may be used\r
- /// for the VMXON region, each VMCS, and data structures referenced by\r
- /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX\r
- /// transitions). If the bit is 0, these addresses are limited to the\r
- /// processor's physical-address width. If the bit is 1, these addresses\r
- /// are limited to 32 bits. This bit is always 0 for processors that\r
- /// support Intel 64 architecture.\r
- ///\r
- /// @note On processors that support Intel 64 architecture, the pointer\r
- /// must not set bits beyond the processor's physical address width.\r
- ///\r
- UINT32 VmcsAddressWidth:1;\r
- ///\r
- /// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r
- /// dual-monitor treatment of system-management interrupts and\r
- /// system-management mode. See Section 34.15 for details of this treatment.\r
- ///\r
- UINT32 DualMonitor:1;\r
- ///\r
- /// [Bit 53:50] report the memory type that should be used for the VMCS,\r
- /// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r
- /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG\r
- /// header. If software needs to access these data structures (e.g., to\r
- /// modify the contents of the MSR bitmaps), it can configure the paging\r
- /// structures to map them into the linear-address space. If it does so,\r
- /// it should establish mappings that use the memory type reported bits\r
- /// 53:50 in this MSR.\r
- ///\r
- /// As of this writing, all processors that support VMX operation indicate\r
- /// the write-back type.\r
- ///\r
- /// If software needs to access these data structures (e.g., to modify\r
- /// the contents of the MSR bitmaps), it can configure the paging\r
- /// structures to map them into the linear-address space. If it does so,\r
- /// it should establish mappings that use the memory type reported in this\r
- /// MSR.\r
- ///\r
- /// @note Alternatively, software may map any of these regions or\r
- /// structures with the UC memory type. (This may be necessary for the MSEG\r
- /// header.) Doing so is discouraged unless necessary as it will cause the\r
- /// performance of software accesses to those structures to suffer.\r
- ///\r
- ///\r
- UINT32 MemoryType:4;\r
- ///\r
- /// [Bit 54] If bit 54 is read as 1, the processor reports information in\r
- /// the VM-exit instruction-information field on VM exitsdue to execution\r
- /// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r
- /// is done only if this bit is read as 1.\r
- ///\r
- UINT32 InsOutsReporting:1;\r
- ///\r
- /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r
- /// be cleared to 0. See Appendix A.2 for details. It also reports support\r
- /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,\r
- /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and\r
- /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r
- /// Appendix A.4, and Appendix A.5 for details.\r
- ///\r
- UINT32 VmxControls:1;\r
- UINT32 Reserved2:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_VMX_BASIC_REGISTER;\r
-\r
-///\r
-/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType\r
-///\r
-#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00\r
-#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06\r
-///\r
-/// @}\r
-///\r
-\r
-\r
-/**\r
- Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r
- Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);\r
- @endcode\r
- @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.\r
-**/\r
-#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r
-\r
-\r
-/**\r
- Capability Reporting Register of Primary Processor-based VM-execution\r
- Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r
- Controls.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);\r
- @endcode\r
- @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.\r
-**/\r
-#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r
-\r
-\r
-/**\r
- Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,\r
- "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);\r
- @endcode\r
- @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.\r
-**/\r
-#define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r
-\r
-\r
-/**\r
- Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,\r
- "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);\r
- @endcode\r
- @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.\r
-**/\r
-#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r
-\r
-\r
-/**\r
- Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,\r
- "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_MISC (0x00000485)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- IA32_VMX_MISC_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
- @endcode\r
- @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r
-**/\r
-#define MSR_IA32_VMX_MISC 0x00000485\r
-\r
-/**\r
- MSR information returned for MSR index #IA32_VMX_MISC\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 4:0] Reports a value X that specifies the relationship between the\r
- /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).\r
- /// Specifically, the VMX-preemption timer (if it is active) counts down by\r
- /// 1 every time bit X in the TSC changes due to a TSC increment.\r
- ///\r
- UINT32 VmxTimerRatio:5;\r
- ///\r
- /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r
- /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r
- /// details. This bit is read as 1 on any logical processor that supports\r
- /// the 1-setting of the "unrestricted guest" VM-execution control.\r
- ///\r
- UINT32 VmExitEferLma:1;\r
- ///\r
- /// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r
- ///\r
- UINT32 HltActivityStateSupported:1;\r
- ///\r
- /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r
- ///\r
- UINT32 ShutdownActivityStateSupported:1;\r
- ///\r
- /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r
- ///\r
- UINT32 WaitForSipiActivityStateSupported:1;\r
- UINT32 Reserved1:5;\r
- ///\r
- /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r
- /// in VMX operation. If the processor supports Intel PT but does not allow\r
- /// it to be used in VMX operation, execution of VMXON clears\r
- /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);\r
- /// any attempt to set that bit while in VMX operation (including VMX root\r
- /// operation) using the WRMSR instruction causes a general-protection\r
- /// exception.\r
- ///\r
- UINT32 ProcessorTraceSupported:1;\r
- ///\r
- /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r
- /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r
- /// See Section 34.15.6.3.\r
- ///\r
- UINT32 SmBaseMsrSupported:1;\r
- ///\r
- /// [Bits 24:16] Indicate the number of CR3-target values supported by the\r
- /// processor. This number is a value between 0 and 256, inclusive (bit 24\r
- /// is set if and only if bits 23:16 are clear).\r
- ///\r
- UINT32 NumberOfCr3TargetValues:9;\r
- ///\r
- /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum\r
- /// number of MSRs that should appear in the VM-exit MSR-store list, the\r
- /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if\r
- /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the\r
- /// recommended maximum number of MSRs to be included in each list. If the\r
- /// limit is exceeded, undefined processor behavior may result (including a\r
- /// machine check during the VMX transition).\r
- ///\r
- UINT32 MsrStoreListMaximum:3;\r
- ///\r
- /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set\r
- /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1\r
- /// (see Section 34.14.4).\r
- ///\r
- UINT32 BlockSmiSupported:1;\r
- ///\r
- /// [Bit 29] read as 1, software can use VMWRITE to write to any supported\r
- /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit\r
- /// information fields.\r
- ///\r
- UINT32 VmWriteSupported:1;\r
- ///\r
- /// [Bit 30] If read as 1, VM entry allows injection of a software\r
- /// interrupt, software exception, or privileged software exception with an\r
- /// instruction length of 0.\r
- ///\r
- UINT32 VmInjectSupported:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r
- /// processor.\r
- ///\r
- UINT32 MsegRevisionIdentifier:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} IA32_VMX_MISC_REGISTER;\r
-\r
-\r
-/**\r
- Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r
- "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);\r
- @endcode\r
- @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.\r
-**/\r
-#define MSR_IA32_VMX_CR0_FIXED0 0x00000486\r
-\r
-\r
-/**\r
- Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,\r
- "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);\r
- @endcode\r
- @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.\r
-**/\r
-#define MSR_IA32_VMX_CR0_FIXED1 0x00000487\r
-\r
-\r
-/**\r
- Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,\r
- "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);\r
- @endcode\r
- @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.\r
-**/\r
-#define MSR_IA32_VMX_CR4_FIXED0 0x00000488\r
-\r
-\r
-/**\r
- Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,\r
- "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);\r
- @endcode\r
- @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.\r
-**/\r
-#define MSR_IA32_VMX_CR4_FIXED1 0x00000489\r
-\r
-\r
-/**\r
- Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix\r
- A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.\r
-\r
- @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);\r
- @endcode\r
- @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.\r
-**/\r
-#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A\r
-\r
-\r
-/**\r
- Capability Reporting Register of Secondary Processor-based VM-execution\r
- Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution\r
- Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).\r
-\r
- @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);\r
- @endcode\r
- @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.\r
-**/\r
-#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B\r
-\r
-\r
-/**\r
- Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,\r
- "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C\r
- TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).\r
-\r
- @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);\r
- @endcode\r
- @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.\r
-**/\r
-#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C\r
-\r
-\r
-/**\r
- Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)\r
- See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (\r
- CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
-\r
- @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);\r
- @endcode\r
- @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.\r
-**/\r
-#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D\r
-\r
-\r
-/**\r
- Capability Reporting Register of Primary Processor-based VM-execution Flex\r
- Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r
- Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
-\r
- @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);\r
- @endcode\r
- @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.\r
-**/\r
-#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E\r
-\r
-\r
-/**\r
- Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix\r
- A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
-\r
- @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);\r
- @endcode\r
- @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.\r
-**/\r
-#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F\r
-\r
-\r
-/**\r
- Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix\r
- A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
-\r
- @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);\r
- @endcode\r
- @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.\r
-**/\r
-#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490\r
-\r
-\r
-/**\r
- Capability Reporting Register of VMfunction Controls (R/O). If(\r
- CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
-\r
- @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);\r
- @endcode\r
- @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.\r
-**/\r
-#define MSR_IA32_VMX_VMFUNC 0x00000491\r
-\r
-\r
-/**\r
- Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&\r
- IA32_PERF_CAPABILITIES[ 13] = 1.\r
-\r
- @param ECX MSR_IA32_A_PMCn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);\r
- AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);\r
- @endcode\r
- @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.\r
- MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.\r
- MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.\r
- MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.\r
- MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.\r
- MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.\r
- MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.\r
- MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_A_PMC0 0x000004C1\r
-#define MSR_IA32_A_PMC1 0x000004C2\r
-#define MSR_IA32_A_PMC2 0x000004C3\r
-#define MSR_IA32_A_PMC3 0x000004C4\r
-#define MSR_IA32_A_PMC4 0x000004C5\r
-#define MSR_IA32_A_PMC5 0x000004C6\r
-#define MSR_IA32_A_PMC6 0x000004C7\r
-#define MSR_IA32_A_PMC7 0x000004C8\r
-/// @}\r
-\r
-\r
-/**\r
- (R/W). If IA32_MCG_CAP.LMCE_P =1.\r
-\r
- @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_MCG_EXT_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);\r
- AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.\r
-**/\r
-#define MSR_IA32_MCG_EXT_CTL 0x000004D0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] LMCE_EN.\r
- ///\r
- UINT32 LMCE_EN:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_MCG_EXT_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,\r
- ECX=0H): EBX[2] = 1.\r
-\r
- @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);\r
- @endcode\r
- @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.\r
-**/\r
-#define MSR_IA32_SGX_SVN_STATUS 0x00000500\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated\r
- /// Code Modules (ACMs)".\r
- ///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:15;\r
- ///\r
- /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with\r
- /// Authenticated Code Modules (ACMs)".\r
- ///\r
- UINT32 SGX_SVN_SINIT:8;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_SGX_SVN_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r
- && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)\r
- ) ).\r
-\r
- @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r
- AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.\r
-**/\r
-#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved:7;\r
- ///\r
- /// [Bits 31:7] Base physical address.\r
- ///\r
- UINT32 Base:25;\r
- ///\r
- /// [Bits 63:32] Base physical address.\r
- ///\r
- UINT32 BaseHi:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;\r
-\r
-\r
-/**\r
- Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,\r
- ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)\r
- (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).\r
-\r
- @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r
- AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.\r
-**/\r
-#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved:7;\r
- ///\r
- /// [Bits 31:7] MaskOrTableOffset.\r
- ///\r
- UINT32 MaskOrTableOffset:25;\r
- ///\r
- /// [Bits 63:32] Output Offset.\r
- ///\r
- UINT32 OutputOffset:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r
-\r
-/**\r
- Format of ToPA table entries.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
- ///\r
- UINT32 END:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
- ///\r
- UINT32 INT:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
- ///\r
- UINT32 STOP:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 6:9] Indicates the size of the associated output region. See Section\r
- /// 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
- ///\r
- UINT32 Size:4;\r
- UINT32 Reserved4:2;\r
- ///\r
- /// [Bit 12:31] Output Region Base Physical Address low part.\r
- /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.\r
- /// ATTENTION: The size of the address field is determined by the processor's\r
- /// physical-address width (MAXPHYADDR) in bits, as reported in\r
- /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r
- /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
- /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
- ///\r
- UINT32 Base:20;\r
- ///\r
- /// [Bit 32:63] Output Region Base Physical Address high part.\r
- /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.\r
- /// ATTENTION: The size of the address field is determined by the processor's\r
- /// physical-address width (MAXPHYADDR) in bits, as reported in\r
- /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r
- /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
- /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
- ///\r
- UINT32 BaseHi:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} RTIT_TOPA_TABLE_ENTRY;\r
-\r
-///\r
-/// The size of the associated output region usd by Topa.\r
-///\r
-typedef enum {\r
- RtitTopaMemorySize4K = 0,\r
- RtitTopaMemorySize8K,\r
- RtitTopaMemorySize16K,\r
- RtitTopaMemorySize32K,\r
- RtitTopaMemorySize64K,\r
- RtitTopaMemorySize128K,\r
- RtitTopaMemorySize256K,\r
- RtitTopaMemorySize512K,\r
- RtitTopaMemorySize1M,\r
- RtitTopaMemorySize2M,\r
- RtitTopaMemorySize4M,\r
- RtitTopaMemorySize8M,\r
- RtitTopaMemorySize16M,\r
- RtitTopaMemorySize32M,\r
- RtitTopaMemorySize64M,\r
- RtitTopaMemorySize128M\r
-} RTIT_TOPA_MEMORY_SIZE;\r
-\r
-/**\r
- Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
-\r
- @param ECX MSR_IA32_RTIT_CTL (0x00000570)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_RTIT_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
- AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r
-**/\r
-#define MSR_IA32_RTIT_CTL 0x00000570\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] TraceEn.\r
- ///\r
- UINT32 TraceEn:1;\r
- ///\r
- /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
- ///\r
- UINT32 CYCEn:1;\r
- ///\r
- /// [Bit 2] OS.\r
- ///\r
- UINT32 OS:1;\r
- ///\r
- /// [Bit 3] User.\r
- ///\r
- UINT32 User:1;\r
- ///\r
- /// [Bit 4] PwrEvtEn.\r
- ///\r
- UINT32 PwrEvtEn:1;\r
- ///\r
- /// [Bit 5] FUPonPTW.\r
- ///\r
- UINT32 FUPonPTW:1;\r
- ///\r
- /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r
- ///\r
- UINT32 FabricEn:1;\r
- ///\r
- /// [Bit 7] CR3 filter.\r
- ///\r
- UINT32 CR3:1;\r
- ///\r
- /// [Bit 8] ToPA.\r
- ///\r
- UINT32 ToPA:1;\r
- ///\r
- /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r
- ///\r
- UINT32 MTCEn:1;\r
- ///\r
- /// [Bit 10] TSCEn.\r
- ///\r
- UINT32 TSCEn:1;\r
- ///\r
- /// [Bit 11] DisRETC.\r
- ///\r
- UINT32 DisRETC:1;\r
- ///\r
- /// [Bit 12] PTWEn.\r
- ///\r
- UINT32 PTWEn:1;\r
- ///\r
- /// [Bit 13] BranchEn.\r
- ///\r
- UINT32 BranchEn:1;\r
- ///\r
- /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r
- ///\r
- UINT32 MTCFreq:4;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
- ///\r
- UINT32 CYCThresh:4;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
- ///\r
- UINT32 PSBFreq:4;\r
- UINT32 Reserved5:4;\r
- ///\r
- /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).\r
- ///\r
- UINT32 ADDR0_CFG:4;\r
- ///\r
- /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).\r
- ///\r
- UINT32 ADDR1_CFG:4;\r
- ///\r
- /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).\r
- ///\r
- UINT32 ADDR2_CFG:4;\r
- ///\r
- /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).\r
- ///\r
- UINT32 ADDR3_CFG:4;\r
- UINT32 Reserved6:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_RTIT_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
-\r
- @param ECX MSR_IA32_RTIT_STATUS (0x00000571)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_RTIT_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);\r
- AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.\r
-**/\r
-#define MSR_IA32_RTIT_STATUS 0x00000571\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_RTIT_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] FilterEn, (writes ignored).\r
- /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).\r
- ///\r
- UINT32 FilterEn:1;\r
- ///\r
- /// [Bit 1] ContexEn, (writes ignored).\r
- ///\r
- UINT32 ContexEn:1;\r
- ///\r
- /// [Bit 2] TriggerEn, (writes ignored).\r
- ///\r
- UINT32 TriggerEn:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 4] Error.\r
- ///\r
- UINT32 Error:1;\r
- ///\r
- /// [Bit 5] Stopped.\r
- ///\r
- UINT32 Stopped:1;\r
- UINT32 Reserved2:26;\r
- ///\r
- /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).\r
- ///\r
- UINT32 PacketByteCnt:17;\r
- UINT32 Reserved3:15;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_RTIT_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Trace Filter CR3 Match Register (R/W).\r
- If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
-\r
- @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);\r
- AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.\r
-**/\r
-#define MSR_IA32_RTIT_CR3_MATCH 0x00000572\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved:5;\r
- ///\r
- /// [Bits 31:5] CR3[63:5] value to match.\r
- ///\r
- UINT32 Cr3:27;\r
- ///\r
- /// [Bits 63:32] CR3[63:5] value to match.\r
- ///\r
- UINT32 Cr3Hi:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_RTIT_CR3_MATCH_REGISTER;\r
-\r
-\r
-/**\r
- Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r
-\r
- @param ECX MSR_IA32_RTIT_ADDRn_A\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_RTIT_ADDR_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);\r
- AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.\r
- MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.\r
- MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.\r
- MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_RTIT_ADDR0_A 0x00000580\r
-#define MSR_IA32_RTIT_ADDR1_A 0x00000582\r
-#define MSR_IA32_RTIT_ADDR2_A 0x00000584\r
-#define MSR_IA32_RTIT_ADDR3_A 0x00000586\r
-/// @}\r
-\r
-\r
-/**\r
- Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r
-\r
- @param ECX MSR_IA32_RTIT_ADDRn_B\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_RTIT_ADDR_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);\r
- AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.\r
- MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.\r
- MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.\r
- MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_RTIT_ADDR0_B 0x00000581\r
-#define MSR_IA32_RTIT_ADDR1_B 0x00000583\r
-#define MSR_IA32_RTIT_ADDR2_B 0x00000585\r
-#define MSR_IA32_RTIT_ADDR3_B 0x00000587\r
-/// @}\r
-\r
-\r
-/**\r
- MSR information returned for MSR indexes\r
- #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and\r
- #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Virtual Address.\r
- ///\r
- UINT32 VirtualAddress:32;\r
- ///\r
- /// [Bits 47:32] Virtual Address.\r
- ///\r
- UINT32 VirtualAddressHi:16;\r
- ///\r
- /// [Bits 63:48] SignExt_VA.\r
- ///\r
- UINT32 SignExt_VA:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_RTIT_ADDR_REGISTER;\r
-\r
-\r
-/**\r
- DS Save Area (R/W) Points to the linear address of the first byte of the DS\r
- buffer management area, which is used to manage the BTS and PEBS buffers.\r
- See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(\r
- CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS\r
- buffer management area, if IA-32e mode is active.\r
-\r
- @param ECX MSR_IA32_DS_AREA (0x00000600)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_DS_AREA_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_DS_AREA_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);\r
- AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);\r
- @endcode\r
- @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.\r
-**/\r
-#define MSR_IA32_DS_AREA 0x00000600\r
-\r
-\r
-/**\r
- TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =\r
- 1.\r
-\r
- @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);\r
- AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);\r
- @endcode\r
- @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.\r
-**/\r
-#define MSR_IA32_TSC_DEADLINE 0x000006E0\r
-\r
-\r
-/**\r
- Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.\r
-\r
- @param ECX MSR_IA32_PM_ENABLE (0x00000770)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PM_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);\r
- AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.\r
-**/\r
-#define MSR_IA32_PM_ENABLE 0x00000770\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PM_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If\r
- /// CPUID.06H:EAX.[7] = 1.\r
- ///\r
- UINT32 HWP_ENABLE:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PM_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.\r
-\r
- @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);\r
- @endcode\r
- @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.\r
-**/\r
-#define MSR_IA32_HWP_CAPABILITIES 0x00000771\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance\r
- /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
- ///\r
- UINT32 Highest_Performance:8;\r
- ///\r
- /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP\r
- /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
- ///\r
- UINT32 Guaranteed_Performance:8;\r
- ///\r
- /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP\r
- /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
- ///\r
- UINT32 Most_Efficient_Performance:8;\r
- ///\r
- /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance\r
- /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
- ///\r
- UINT32 Lowest_Performance:8;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_HWP_CAPABILITIES_REGISTER;\r
-\r
-\r
-/**\r
- Power Management Control Hints for All Logical Processors in a Package\r
- (R/W). If CPUID.06H:EAX.[11] = 1.\r
-\r
- @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);\r
- AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.\r
-**/\r
-#define MSR_IA32_HWP_REQUEST_PKG 0x00000772\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r
- /// CPUID.06H:EAX.[11] = 1.\r
- ///\r
- UINT32 Minimum_Performance:8;\r
- ///\r
- /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r
- /// CPUID.06H:EAX.[11] = 1.\r
- ///\r
- UINT32 Maximum_Performance:8;\r
- ///\r
- /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r
- /// If CPUID.06H:EAX.[11] = 1.\r
- ///\r
- UINT32 Desired_Performance:8;\r
- ///\r
- /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r
- /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.\r
- ///\r
- UINT32 Energy_Performance_Preference:8;\r
- ///\r
- /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r
- /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.\r
- ///\r
- UINT32 Activity_Window:10;\r
- UINT32 Reserved:22;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_HWP_REQUEST_PKG_REGISTER;\r
-\r
-\r
-/**\r
- Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.\r
-\r
- @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_HWP_INTERRUPT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);\r
- AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.\r
-**/\r
-#define MSR_IA32_HWP_INTERRUPT 0x00000773\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP\r
- /// Notifications". If CPUID.06H:EAX.[8] = 1.\r
- ///\r
- UINT32 EN_Guaranteed_Performance_Change:1;\r
- ///\r
- /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".\r
- /// If CPUID.06H:EAX.[8] = 1.\r
- ///\r
- UINT32 EN_Excursion_Minimum:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_HWP_INTERRUPT_REGISTER;\r
-\r
-\r
-/**\r
- Power Management Control Hints to a Logical Processor (R/W). If\r
- CPUID.06H:EAX.[7] = 1.\r
-\r
- @param ECX MSR_IA32_HWP_REQUEST (0x00000774)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_HWP_REQUEST_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);\r
- AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.\r
-**/\r
-#define MSR_IA32_HWP_REQUEST 0x00000774\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_HWP_REQUEST\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r
- /// CPUID.06H:EAX.[7] = 1.\r
- ///\r
- UINT32 Minimum_Performance:8;\r
- ///\r
- /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r
- /// CPUID.06H:EAX.[7] = 1.\r
- ///\r
- UINT32 Maximum_Performance:8;\r
- ///\r
- /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r
- /// If CPUID.06H:EAX.[7] = 1.\r
- ///\r
- UINT32 Desired_Performance:8;\r
- ///\r
- /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r
- /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.\r
- ///\r
- UINT32 Energy_Performance_Preference:8;\r
- ///\r
- /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r
- /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.\r
- ///\r
- UINT32 Activity_Window:10;\r
- ///\r
- /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If\r
- /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.\r
- ///\r
- UINT32 Package_Control:1;\r
- UINT32 Reserved:21;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_HWP_REQUEST_REGISTER;\r
-\r
-\r
-/**\r
- Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If\r
- CPUID.06H:EAX.[7] = 1.\r
-\r
- @param ECX MSR_IA32_HWP_STATUS (0x00000777)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_HWP_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);\r
- AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.\r
-**/\r
-#define MSR_IA32_HWP_STATUS 0x00000777\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_HWP_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,\r
- /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.\r
- ///\r
- UINT32 Guaranteed_Performance_Change:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP\r
- /// Feedback". If CPUID.06H:EAX.[7] = 1.\r
- ///\r
- UINT32 Excursion_To_Minimum:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_HWP_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1\r
- && IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_APICID (0x00000802)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);\r
- @endcode\r
- @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_APICID 0x00000802\r
-\r
-\r
-/**\r
- x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);\r
- @endcode\r
- @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_VERSION 0x00000803\r
-\r
-\r
-/**\r
- x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_TPR (0x00000808)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_TPR 0x00000808\r
-\r
-\r
-/**\r
- x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);\r
- @endcode\r
- @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_PPR 0x0000080A\r
-\r
-\r
-/**\r
- x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]\r
- = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = 0;\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_EOI 0x0000080B\r
-\r
-\r
-/**\r
- x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);\r
- @endcode\r
- @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_LDR 0x0000080D\r
-\r
-\r
-/**\r
- x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1\r
- && IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_SIVR 0x0000080F\r
-\r
-\r
-/**\r
- x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).\r
- If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_ISRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);\r
- @endcode\r
- @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.\r
- MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.\r
- MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.\r
- MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.\r
- MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.\r
- MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.\r
- MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.\r
- MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_X2APIC_ISR0 0x00000810\r
-#define MSR_IA32_X2APIC_ISR1 0x00000811\r
-#define MSR_IA32_X2APIC_ISR2 0x00000812\r
-#define MSR_IA32_X2APIC_ISR3 0x00000813\r
-#define MSR_IA32_X2APIC_ISR4 0x00000814\r
-#define MSR_IA32_X2APIC_ISR5 0x00000815\r
-#define MSR_IA32_X2APIC_ISR6 0x00000816\r
-#define MSR_IA32_X2APIC_ISR7 0x00000817\r
-/// @}\r
-\r
-\r
-/**\r
- x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).\r
- If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_TMRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);\r
- @endcode\r
- @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.\r
- MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.\r
- MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.\r
- MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.\r
- MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.\r
- MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.\r
- MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.\r
- MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_X2APIC_TMR0 0x00000818\r
-#define MSR_IA32_X2APIC_TMR1 0x00000819\r
-#define MSR_IA32_X2APIC_TMR2 0x0000081A\r
-#define MSR_IA32_X2APIC_TMR3 0x0000081B\r
-#define MSR_IA32_X2APIC_TMR4 0x0000081C\r
-#define MSR_IA32_X2APIC_TMR5 0x0000081D\r
-#define MSR_IA32_X2APIC_TMR6 0x0000081E\r
-#define MSR_IA32_X2APIC_TMR7 0x0000081F\r
-/// @}\r
-\r
-\r
-/**\r
- x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).\r
- If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_IRRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);\r
- @endcode\r
- @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.\r
- MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.\r
- MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.\r
- MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.\r
- MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.\r
- MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.\r
- MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.\r
- MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.\r
- @{\r
-**/\r
-#define MSR_IA32_X2APIC_IRR0 0x00000820\r
-#define MSR_IA32_X2APIC_IRR1 0x00000821\r
-#define MSR_IA32_X2APIC_IRR2 0x00000822\r
-#define MSR_IA32_X2APIC_IRR3 0x00000823\r
-#define MSR_IA32_X2APIC_IRR4 0x00000824\r
-#define MSR_IA32_X2APIC_IRR5 0x00000825\r
-#define MSR_IA32_X2APIC_IRR6 0x00000826\r
-#define MSR_IA32_X2APIC_IRR7 0x00000827\r
-/// @}\r
-\r
-\r
-/**\r
- x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_ESR (0x00000828)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_ESR 0x00000828\r
-\r
-\r
-/**\r
- x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If\r
- CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F\r
-\r
-\r
-/**\r
- x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_ICR (0x00000830)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_ICR 0x00000830\r
-\r
-\r
-/**\r
- x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832\r
-\r
-\r
-/**\r
- x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =\r
- 1 && IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833\r
-\r
-\r
-/**\r
- x2APIC LVT Performance Monitor Interrupt Register (R/W). If\r
- CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_LVT_PMI 0x00000834\r
-\r
-\r
-/**\r
- x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835\r
-\r
-\r
-/**\r
- x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836\r
-\r
-\r
-/**\r
- x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837\r
-\r
-\r
-/**\r
- x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838\r
-\r
-\r
-/**\r
- x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);\r
- @endcode\r
- @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839\r
-\r
-\r
-/**\r
- x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E\r
-\r
-\r
-/**\r
- x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&\r
- IA32_APIC_BASE.[10] = 1.\r
-\r
- @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = 0;\r
- AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);\r
- @endcode\r
- @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.\r
-**/\r
-#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F\r
-\r
-\r
-/**\r
- Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.\r
-\r
- @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);\r
- AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.\r
-**/\r
-#define MSR_IA32_DEBUG_INTERFACE 0x00000C80\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.\r
- /// Default is 0. If CPUID.01H:ECX.[11] = 1.\r
- ///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:29;\r
- ///\r
- /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The\r
- /// lock bit is set automatically on the first SMI assertion even if not\r
- /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.\r
- ///\r
- UINT32 Lock:1;\r
- ///\r
- /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to\r
- /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.\r
- ///\r
- UINT32 DebugOccurred:1;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_DEBUG_INTERFACE_REGISTER;\r
-\r
-\r
-/**\r
- L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).\r
-\r
- @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_L3_QOS_CFG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);\r
- AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
-**/\r
-#define MSR_IA32_L3_QOS_CFG 0x00000C81\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate\r
- /// in Code and Data Prioritization (CDP) mode.\r
- ///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_L3_QOS_CFG_REGISTER;\r
-\r
-/**\r
- L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).\r
-\r
- @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_L2_QOS_CFG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);\r
- AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.\r
-**/\r
-#define MSR_IA32_L2_QOS_CFG 0x00000C82\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate\r
- /// in Code and Data Prioritization (CDP) mode.\r
- ///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_L2_QOS_CFG_REGISTER;\r
-\r
-/**\r
- Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]\r
- = 1 ).\r
-\r
- @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_QM_EVTSEL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);\r
- AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
-**/\r
-#define MSR_IA32_QM_EVTSEL 0x00000C8D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_QM_EVTSEL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via\r
- /// IA32_QM_CTR.\r
- ///\r
- UINT32 EventID:8;\r
- UINT32 Reserved:24;\r
- ///\r
- /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to\r
- /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (\r
- /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r
- ///\r
- UINT32 ResourceMonitoringID:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_QM_EVTSEL_REGISTER;\r
-\r
-\r
-/**\r
- Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1\r
- ).\r
-\r
- @param ECX MSR_IA32_QM_CTR (0x00000C8E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_QM_CTR_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_QM_CTR_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_QM_CTR_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);\r
- @endcode\r
- @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.\r
-**/\r
-#define MSR_IA32_QM_CTR 0x00000C8E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_QM_CTR\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Resource Monitored Data.\r
- ///\r
- UINT32 ResourceMonitoredData:32;\r
- ///\r
- /// [Bits 61:32] Resource Monitored Data.\r
- ///\r
- UINT32 ResourceMonitoredDataHi:30;\r
- ///\r
- /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not\r
- /// available or not monitored for this resource or RMID.\r
- ///\r
- UINT32 Unavailable:1;\r
- ///\r
- /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was\r
- /// written to IA32_PQR_QM_EVTSEL.\r
- ///\r
- UINT32 Error:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_QM_CTR_REGISTER;\r
-\r
-\r
-/**\r
- Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]\r
- =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).\r
-\r
- @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PQR_ASSOC_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);\r
- AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
-**/\r
-#define MSR_IA32_PQR_ASSOC 0x00000C8F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PQR_ASSOC\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware\r
- /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`\r
- /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r
- ///\r
- UINT32 ResourceMonitoringID:32;\r
- ///\r
- /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on\r
- /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,\r
- /// ECX=0):EBX.[15] = 1 ).\r
- ///\r
- UINT32 COS:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PQR_ASSOC_REGISTER;\r
-\r
-\r
-/**\r
- Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,\r
- ECX=0H):EBX[14] = 1).\r
-\r
- @param ECX MSR_IA32_BNDCFGS (0x00000D90)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_BNDCFGS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_BNDCFGS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_BNDCFGS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);\r
- AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.\r
-**/\r
-#define MSR_IA32_BNDCFGS 0x00000D90\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_BNDCFGS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] EN: Enable Intel MPX in supervisor mode.\r
- ///\r
- UINT32 EN:1;\r
- ///\r
- /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch\r
- /// instructions in the absence of the BND prefix.\r
- ///\r
- UINT32 BNDPRESERVE:1;\r
- UINT32 Reserved:10;\r
- ///\r
- /// [Bits 31:12] Base Address of Bound Directory.\r
- ///\r
- UINT32 Base:20;\r
- ///\r
- /// [Bits 63:32] Base Address of Bound Directory.\r
- ///\r
- UINT32 BaseHi:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_BNDCFGS_REGISTER;\r
-\r
-\r
-/**\r
- Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.\r
-\r
- @param ECX MSR_IA32_XSS (0x00000DA0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_XSS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_XSS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_XSS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);\r
- AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_XSS is defined as IA32_XSS in SDM.\r
-**/\r
-#define MSR_IA32_XSS 0x00000DA0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_XSS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bit 8] Trace Packet Configuration State (R/W).\r
- ///\r
- UINT32 TracePacketConfigurationState:1;\r
- UINT32 Reserved2:23;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_XSS_REGISTER;\r
-\r
-\r
-/**\r
- Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.\r
-\r
- @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PKG_HDC_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);\r
- AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.\r
-**/\r
-#define MSR_IA32_PKG_HDC_CTL 0x00000DB0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled\r
- /// logical processors in the package. See Section 14.5.2, "Package level\r
- /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.\r
- ///\r
- UINT32 HDC_Pkg_Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PKG_HDC_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.\r
-\r
- @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_PM_CTL1_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_PM_CTL1_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_PM_CTL1_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);\r
- AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.\r
-**/\r
-#define MSR_IA32_PM_CTL1 0x00000DB1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_PM_CTL1\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for\r
- /// package level HDC control. See Section 14.5.3.\r
- /// If CPUID.06H:EAX.[13] = 1.\r
- ///\r
- UINT32 HDC_Allow_Block:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_PM_CTL1_REGISTER;\r
-\r
-\r
-/**\r
- Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.\r
- Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical\r
- processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.\r
-\r
- @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);\r
- @endcode\r
- @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.\r
-**/\r
-#define MSR_IA32_THREAD_STALL 0x00000DB2\r
-\r
-\r
-/**\r
- Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]\r
- CPUID.80000001H:EDX.[2 9]).\r
-\r
- @param ECX MSR_IA32_EFER (0xC0000080)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_EFER_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_EFER_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_EFER_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r
- AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_EFER is defined as IA32_EFER in SDM.\r
-**/\r
-#define MSR_IA32_EFER 0xC0000080\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_EFER\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET\r
- /// instructions in 64-bit mode.\r
- ///\r
- UINT32 SCE:1;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode\r
- /// operation.\r
- ///\r
- UINT32 LME:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode\r
- /// is active when set.\r
- ///\r
- UINT32 LMA:1;\r
- ///\r
- /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).\r
- ///\r
- UINT32 NXE:1;\r
- UINT32 Reserved3:20;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_EFER_REGISTER;\r
-\r
-\r
-/**\r
- System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r
-\r
- @param ECX MSR_IA32_STAR (0xC0000081)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_STAR);\r
- AsmWriteMsr64 (MSR_IA32_STAR, Msr);\r
- @endcode\r
- @note MSR_IA32_STAR is defined as IA32_STAR in SDM.\r
-**/\r
-#define MSR_IA32_STAR 0xC0000081\r
-\r
-\r
-/**\r
- IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r
-\r
- @param ECX MSR_IA32_LSTAR (0xC0000082)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_LSTAR);\r
- AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);\r
- @endcode\r
- @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.\r
-**/\r
-#define MSR_IA32_LSTAR 0xC0000082\r
-\r
-/**\r
- IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL\r
- instruction is not recognized in compatibility mode. If\r
- CPUID.80000001:EDX.[29] = 1.\r
-\r
- @param ECX MSR_IA32_CSTAR (0xC0000083)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_CSTAR);\r
- AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);\r
- @endcode\r
- @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.\r
-**/\r
-#define MSR_IA32_CSTAR 0xC0000083\r
-\r
-/**\r
- System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r
-\r
- @param ECX MSR_IA32_FMASK (0xC0000084)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_FMASK);\r
- AsmWriteMsr64 (MSR_IA32_FMASK, Msr);\r
- @endcode\r
- @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.\r
-**/\r
-#define MSR_IA32_FMASK 0xC0000084\r
-\r
-\r
-/**\r
- Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
-\r
- @param ECX MSR_IA32_FS_BASE (0xC0000100)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);\r
- AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);\r
- @endcode\r
- @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.\r
-**/\r
-#define MSR_IA32_FS_BASE 0xC0000100\r
-\r
-\r
-/**\r
- Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
-\r
- @param ECX MSR_IA32_GS_BASE (0xC0000101)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);\r
- AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);\r
- @endcode\r
- @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.\r
-**/\r
-#define MSR_IA32_GS_BASE 0xC0000101\r
-\r
-\r
-/**\r
- Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
-\r
- @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);\r
- AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);\r
- @endcode\r
- @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.\r
-**/\r
-#define MSR_IA32_KERNEL_GS_BASE 0xC0000102\r
-\r
-\r
-/**\r
- Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.\r
-\r
- @param ECX MSR_IA32_TSC_AUX (0xC0000103)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IA32_TSC_AUX_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IA32_TSC_AUX_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IA32_TSC_AUX_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);\r
- AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);\r
- @endcode\r
- @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.\r
-**/\r
-#define MSR_IA32_TSC_AUX 0xC0000103\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_TSC_AUX\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] AUX: Auxiliary signature of TSC.\r
- ///\r
- UINT32 AUX:32;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IA32_TSC_AUX_REGISTER;\r
+#include <Register/Intel/ArchitecturalMsr.h>\r
\r
#endif\r
\r
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,\r
- November 2018, CPUID instruction.\r
-\r
**/\r
\r
#ifndef __CPUID_H__\r
/** @file\r
- IA32 Local APIC Definitions.\r
+ Wrapper header file to include <Register/Intel/LocalApic.h> in MdePkg.\r
\r
- Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
**/\r
\r
#ifndef __LOCAL_APIC_H__\r
#define __LOCAL_APIC_H__\r
\r
-//\r
-// Definition for Local APIC registers and related values\r
-//\r
-#define XAPIC_ID_OFFSET 0x20\r
-#define XAPIC_VERSION_OFFSET 0x30\r
-#define XAPIC_EOI_OFFSET 0x0b0\r
-#define XAPIC_ICR_DFR_OFFSET 0x0e0\r
-#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r
-#define XAPIC_ICR_LOW_OFFSET 0x300\r
-#define XAPIC_ICR_HIGH_OFFSET 0x310\r
-#define XAPIC_LVT_TIMER_OFFSET 0x320\r
-#define XAPIC_LVT_LINT0_OFFSET 0x350\r
-#define XAPIC_LVT_LINT1_OFFSET 0x360\r
-#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r
-#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r
-#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
-\r
-#define X2APIC_MSR_BASE_ADDRESS 0x800\r
-#define X2APIC_MSR_ICR_ADDRESS 0x830\r
-\r
-#define LOCAL_APIC_DELIVERY_MODE_FIXED 0\r
-#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r
-#define LOCAL_APIC_DELIVERY_MODE_SMI 2\r
-#define LOCAL_APIC_DELIVERY_MODE_NMI 4\r
-#define LOCAL_APIC_DELIVERY_MODE_INIT 5\r
-#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6\r
-#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7\r
-\r
-#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0\r
-#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1\r
-#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
-#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
-\r
-//\r
-// Local APIC Version Register.\r
-//\r
-typedef union {\r
- struct {\r
- UINT32 Version:8; ///< The version numbers of the local APIC.\r
- UINT32 Reserved0:8; ///< Reserved.\r
- UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.\r
- UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.\r
- UINT32 Reserved1:7; ///< Reserved.\r
- } Bits;\r
- UINT32 Uint32;\r
-} LOCAL_APIC_VERSION;\r
-\r
-//\r
-// Low half of Interrupt Command Register (ICR).\r
-//\r
-typedef union {\r
- struct {\r
- UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
- UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.\r
- UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.\r
- UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r
- UINT32 Reserved0:1; ///< Reserved.\r
- UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r
- UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r
- UINT32 Reserved1:2; ///< Reserved.\r
- UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.\r
- UINT32 Reserved2:12; ///< Reserved.\r
- } Bits;\r
- UINT32 Uint32;\r
-} LOCAL_APIC_ICR_LOW;\r
-\r
-//\r
-// High half of Interrupt Command Register (ICR)\r
-//\r
-typedef union {\r
- struct {\r
- UINT32 Reserved0:24; ///< Reserved.\r
- UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.\r
- } Bits;\r
- UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.\r
-} LOCAL_APIC_ICR_HIGH;\r
-\r
-//\r
-// Spurious-Interrupt Vector Register (SVR)\r
-//\r
-typedef union {\r
- struct {\r
- UINT32 SpuriousVector:8; ///< Spurious Vector.\r
- UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.\r
- UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.\r
- UINT32 Reserved0:2; ///< Reserved.\r
- UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.\r
- UINT32 Reserved1:19; ///< Reserved.\r
- } Bits;\r
- UINT32 Uint32;\r
-} LOCAL_APIC_SVR;\r
-\r
-//\r
-// Divide Configuration Register (DCR)\r
-//\r
-typedef union {\r
- struct {\r
- UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.\r
- UINT32 Reserved0:1; ///< Always 0.\r
- UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.\r
- UINT32 Reserved1:28; ///< Reserved.\r
- } Bits;\r
- UINT32 Uint32;\r
-} LOCAL_APIC_DCR;\r
-\r
-//\r
-// LVT Timer Register\r
-//\r
-typedef union {\r
- struct {\r
- UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
- UINT32 Reserved0:4; ///< Reserved.\r
- UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
- UINT32 Reserved1:3; ///< Reserved.\r
- UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
- UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.\r
- UINT32 Reserved2:14; ///< Reserved.\r
- } Bits;\r
- UINT32 Uint32;\r
-} LOCAL_APIC_LVT_TIMER;\r
-\r
-//\r
-// LVT LINT0/LINT1 Register\r
-//\r
-typedef union {\r
- struct {\r
- UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
- UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
- UINT32 Reserved0:1; ///< Reserved.\r
- UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
- UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.\r
- UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r
- UINT32 TriggerMode:1; ///< 0:edge, 1:level.\r
- UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
- UINT32 Reserved1:15; ///< Reserved.\r
- } Bits;\r
- UINT32 Uint32;\r
-} LOCAL_APIC_LVT_LINT;\r
-\r
-//\r
-// MSI Address Register\r
-//\r
-typedef union {\r
- struct {\r
- UINT32 Reserved0:2; ///< Reserved\r
- UINT32 DestinationMode:1; ///< Specifies the Destination Mode.\r
- UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.\r
- UINT32 Reserved1:8; ///< Reserved.\r
- UINT32 DestinationId:8; ///< Specifies the Destination ID.\r
- UINT32 BaseAddress:12; ///< Must be 0FEEH\r
- } Bits;\r
- UINT32 Uint32;\r
-} LOCAL_APIC_MSI_ADDRESS;\r
-\r
-//\r
-// MSI Address Register\r
-//\r
-typedef union {\r
- struct {\r
- UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH\r
- UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
- UINT32 Reserved0:3; ///< Reserved.\r
- UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.\r
- UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.\r
- UINT32 Reserved1:16; ///< Reserved.\r
- UINT32 Reserved2:32; ///< Reserved.\r
- } Bits;\r
- UINT64 Uint64;\r
-} LOCAL_APIC_MSI_DATA;\r
+#include <Register/Intel/LocalApic.h>\r
\r
#endif\r
\r
/** @file\r
- Microcode Definitions.\r
+ Wrapper header file to include <Register/Intel/Microcode.h> in MdePkg.\r
\r
- Microcode Definitions based on contents of the\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- Volume 3A, Section 9.11 Microcode Definitions\r
-\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A,\r
- June 2016, Chapter 9 Processor Management and Initialization, Section 9-11.\r
-\r
**/\r
\r
#ifndef __MICROCODE_H__\r
#define __MICROCODE_H__\r
\r
-///\r
-/// CPU Microcode Date in BCD format\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 Year:16;\r
- UINT32 Day:8;\r
- UINT32 Month:8;\r
- } Bits;\r
- UINT32 Uint32;\r
-} CPU_MICROCODE_DATE;\r
-\r
-///\r
-/// CPU Microcode Processor Signature format\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 Stepping:4;\r
- UINT32 Model:4;\r
- UINT32 Family:4;\r
- UINT32 Type:2;\r
- UINT32 Reserved1:2;\r
- UINT32 ExtendedModel:4;\r
- UINT32 ExtendedFamily:8;\r
- UINT32 Reserved2:4;\r
- } Bits;\r
- UINT32 Uint32;\r
-} CPU_MICROCODE_PROCESSOR_SIGNATURE;\r
-\r
-#pragma pack (1)\r
-\r
-///\r
-/// Microcode Update Format definition\r
-///\r
-typedef struct {\r
- ///\r
- /// Version number of the update header\r
- ///\r
- UINT32 HeaderVersion;\r
- ///\r
- /// Unique version number for the update, the basis for the update\r
- /// signature provided by the processor to indicate the current update\r
- /// functioning within the processor. Used by the BIOS to authenticate\r
- /// the update and verify that the processor loads successfully. The\r
- /// value in this field cannot be used for processor stepping identification\r
- /// alone. This is a signed 32-bit number.\r
- ///\r
- UINT32 UpdateRevision;\r
- ///\r
- /// Date of the update creation in binary format: mmddyyyy (e.g.\r
- /// 07/18/98 is 07181998H).\r
- ///\r
- CPU_MICROCODE_DATE Date;\r
- ///\r
- /// Extended family, extended model, type, family, model, and stepping\r
- /// of processor that requires this particular update revision (e.g.,\r
- /// 00000650H). Each microcode update is designed specifically for a\r
- /// given extended family, extended model, type, family, model, and\r
- /// stepping of the processor.\r
- /// The BIOS uses the processor signature field in conjunction with the\r
- /// CPUID instruction to determine whether or not an update is\r
- /// appropriate to load on a processor. The information encoded within\r
- /// this field exactly corresponds to the bit representations returned by\r
- /// the CPUID instruction.\r
- ///\r
- CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;\r
- ///\r
- /// Checksum of Update Data and Header. Used to verify the integrity of\r
- /// the update header and data. Checksum is correct when the\r
- /// summation of all the DWORDs (including the extended Processor\r
- /// Signature Table) that comprise the microcode update result in\r
- /// 00000000H.\r
- ///\r
- UINT32 Checksum;\r
- ///\r
- /// Version number of the loader program needed to correctly load this\r
- /// update. The initial version is 00000001H\r
- ///\r
- UINT32 LoaderRevision;\r
- ///\r
- /// Platform type information is encoded in the lower 8 bits of this 4-\r
- /// byte field. Each bit represents a particular platform type for a given\r
- /// CPUID. The BIOS uses the processor flags field in conjunction with\r
- /// the platform Id bits in MSR (17H) to determine whether or not an\r
- /// update is appropriate to load on a processor. Multiple bits may be set\r
- /// representing support for multiple platform IDs.\r
- ///\r
- UINT32 ProcessorFlags;\r
- ///\r
- /// Specifies the size of the encrypted data in bytes, and must be a\r
- /// multiple of DWORDs. If this value is 00000000H, then the microcode\r
- /// update encrypted data is 2000 bytes (or 500 DWORDs).\r
- ///\r
- UINT32 DataSize;\r
- ///\r
- /// Specifies the total size of the microcode update in bytes. It is the\r
- /// summation of the header size, the encrypted data size and the size of\r
- /// the optional extended signature table. This value is always a multiple\r
- /// of 1024.\r
- ///\r
- UINT32 TotalSize;\r
- ///\r
- /// Reserved fields for future expansion.\r
- ///\r
- UINT8 Reserved[12];\r
-} CPU_MICROCODE_HEADER;\r
-\r
-///\r
-/// Extended Signature Table Header Field Definitions\r
-///\r
-typedef struct {\r
- ///\r
- /// Specifies the number of extended signature structures (Processor\r
- /// Signature[n], processor flags[n] and checksum[n]) that exist in this\r
- /// microcode update\r
- ///\r
- UINT32 ExtendedSignatureCount;\r
- ///\r
- /// Checksum of update extended processor signature table. Used to\r
- /// verify the integrity of the extended processor signature table.\r
- /// Checksum is correct when the summation of the DWORDs that\r
- /// comprise the extended processor signature table results in\r
- /// 00000000H.\r
- ///\r
- UINT32 ExtendedChecksum;\r
- ///\r
- /// Reserved fields.\r
- ///\r
- UINT8 Reserved[12];\r
-} CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
-\r
-///\r
-/// Extended Signature Table Field Definitions\r
-///\r
-typedef struct {\r
- ///\r
- /// Extended family, extended model, type, family, model, and stepping\r
- /// of processor that requires this particular update revision (e.g.,\r
- /// 00000650H). Each microcode update is designed specifically for a\r
- /// given extended family, extended model, type, family, model, and\r
- /// stepping of the processor.\r
- /// The BIOS uses the processor signature field in conjunction with the\r
- /// CPUID instruction to determine whether or not an update is\r
- /// appropriate to load on a processor. The information encoded within\r
- /// this field exactly corresponds to the bit representations returned by\r
- /// the CPUID instruction.\r
- ///\r
- CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;\r
- ///\r
- /// Platform type information is encoded in the lower 8 bits of this 4-\r
- /// byte field. Each bit represents a particular platform type for a given\r
- /// CPUID. The BIOS uses the processor flags field in conjunction with\r
- /// the platform Id bits in MSR (17H) to determine whether or not an\r
- /// update is appropriate to load on a processor. Multiple bits may be set\r
- /// representing support for multiple platform IDs.\r
- ///\r
- UINT32 ProcessorFlag;\r
- ///\r
- /// Used by utility software to decompose a microcode update into\r
- /// multiple microcode updates where each of the new updates is\r
- /// constructed without the optional Extended Processor Signature\r
- /// Table.\r
- /// To calculate the Checksum, substitute the Primary Processor\r
- /// Signature entry and the Processor Flags entry with the\r
- /// corresponding Extended Patch entry. Delete the Extended Processor\r
- /// Signature Table entries. The Checksum is correct when the\r
- /// summation of all DWORDs that comprise the created Extended\r
- /// Processor Patch results in 00000000H.\r
- ///\r
- UINT32 Checksum;\r
-} CPU_MICROCODE_EXTENDED_TABLE;\r
-\r
-#pragma pack ()\r
+#include <Register/Intel/Microcode.h>\r
\r
#endif\r
/** @file\r
- MSR Definitions.\r
+ Wrapper header file to include <Register/Intel/Msr.h> in MdePkg.\r
\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 ~ 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
**/\r
\r
#ifndef __MSR_H__\r
#define __MSR_H__\r
\r
-#include <Register/ArchitecturalMsr.h>\r
-#include <Register/Msr/Core2Msr.h>\r
-#include <Register/Msr/AtomMsr.h>\r
-#include <Register/Msr/SilvermontMsr.h>\r
-#include <Register/Msr/GoldmontMsr.h>\r
-#include <Register/Msr/GoldmontPlusMsr.h>\r
-#include <Register/Msr/NehalemMsr.h>\r
-#include <Register/Msr/Xeon5600Msr.h>\r
-#include <Register/Msr/XeonE7Msr.h>\r
-#include <Register/Msr/SandyBridgeMsr.h>\r
-#include <Register/Msr/IvyBridgeMsr.h>\r
-#include <Register/Msr/HaswellMsr.h>\r
-#include <Register/Msr/HaswellEMsr.h>\r
-#include <Register/Msr/BroadwellMsr.h>\r
-#include <Register/Msr/XeonDMsr.h>\r
-#include <Register/Msr/SkylakeMsr.h>\r
-#include <Register/Msr/XeonPhiMsr.h>\r
-#include <Register/Msr/Pentium4Msr.h>\r
-#include <Register/Msr/CoreMsr.h>\r
-#include <Register/Msr/PentiumMMsr.h>\r
-#include <Register/Msr/P6Msr.h>\r
-#include <Register/Msr/PentiumMsr.h>\r
+#include <Register/Intel/Msr.h>\r
\r
#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for the Intel(R) Atom(TM) Processor Family.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __ATOM_MSR_H__\r
-#define __ATOM_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel(R) Atom(TM) Processor Family?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x1C || \\r
- DisplayModel == 0x26 || \\r
- DisplayModel == 0x27 || \\r
- DisplayModel == 0x35 || \\r
- DisplayModel == 0x36 \\r
- ) \\r
- )\r
-\r
-/**\r
- Shared. Model Specific Platform ID (R).\r
-\r
- @param ECX MSR_ATOM_PLATFORM_ID (0x00000017)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_ATOM_PLATFORM_ID_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);\r
- @endcode\r
- @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
-**/\r
-#define MSR_ATOM_PLATFORM_ID 0x00000017\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
- ///\r
- UINT32 MaximumQualifiedRatio:5;\r
- UINT32 Reserved2:19;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_ATOM_PLATFORM_ID_REGISTER;\r
-\r
-\r
-/**\r
- Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
- processor features; (R) indicates current processor configuration.\r
-\r
- @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);\r
- AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);\r
- @endcode\r
- @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
-**/\r
-#define MSR_ATOM_EBL_CR_POWERON 0x0000002A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
- /// Always 0.\r
- ///\r
- UINT32 DataErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
- /// Always 0.\r
- ///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
- ///\r
- UINT32 AERR_DriveEnable:1;\r
- ///\r
- /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =\r
- /// Disabled Always 0.\r
- ///\r
- UINT32 BERR_Enable:1;\r
- UINT32 Reserved2:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
- ///\r
- UINT32 BINIT_DriverEnable:1;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 ExecuteBIST:1;\r
- ///\r
- /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
- /// Always 0.\r
- ///\r
- UINT32 AERR_ObservationEnabled:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
- /// Always 0.\r
- ///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
- ///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved7:1;\r
- ///\r
- /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.\r
- ///\r
- UINT32 APICClusterID:2;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.\r
- ///\r
- UINT32 SymmetricArbitrationID:2;\r
- ///\r
- /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
- ///\r
- UINT32 IntegerBusFrequencyRatio:5;\r
- UINT32 Reserved9:5;\r
- UINT32 Reserved10:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_ATOM_EBL_CR_POWERON_REGISTER;\r
-\r
-\r
-/**\r
- Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
- record registers on the last branch record stack. The From_IP part of the\r
- stack contains pointers to the source instruction . See also: - Last Branch\r
- Record Stack TOS at 1C9H - Section 17.5.\r
-\r
- @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);\r
- AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);\r
- @endcode\r
- @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040\r
-#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041\r
-#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042\r
-#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043\r
-#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044\r
-#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045\r
-#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046\r
-#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047\r
-/// @}\r
-\r
-\r
-/**\r
- Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
- record registers on the last branch record stack. The To_IP part of the\r
- stack contains pointers to the destination instruction.\r
-\r
- @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);\r
- AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);\r
- @endcode\r
- @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
- MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060\r
-#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061\r
-#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062\r
-#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063\r
-#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064\r
-#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065\r
-#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066\r
-#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067\r
-/// @}\r
-\r
-\r
-/**\r
- Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
- bus clock speed for processors based on Intel Atom microarchitecture:.\r
-\r
- @param ECX MSR_ATOM_FSB_FREQ (0x000000CD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_ATOM_FSB_FREQ_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_ATOM_FSB_FREQ_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_ATOM_FSB_FREQ_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);\r
- @endcode\r
- @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
-**/\r
-#define MSR_ATOM_FSB_FREQ 0x000000CD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_ATOM_FSB_FREQ\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] - Scalable Bus Speed\r
- ///\r
- /// Atom Processor Family\r
- /// ---------------------\r
- /// 111B: 083 MHz (FSB 333)\r
- /// 101B: 100 MHz (FSB 400)\r
- /// 001B: 133 MHz (FSB 533)\r
- /// 011B: 167 MHz (FSB 667)\r
- ///\r
- /// 133.33 MHz should be utilized if performing calculation with\r
- /// System Bus Speed when encoding is 001B.\r
- /// 166.67 MHz should be utilized if performing calculation with\r
- /// System Bus Speed when\r
- /// encoding is 011B.\r
- ///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_ATOM_FSB_FREQ_REGISTER;\r
-\r
-\r
-/**\r
- Shared.\r
-\r
- @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);\r
- AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);\r
- @endcode\r
- @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
-**/\r
-#define MSR_ATOM_BBL_CR_CTL3 0x0000011E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
- /// Indicates if the L2 is hardware-disabled.\r
- ///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r
- /// Disabled (default) Until this bit is set the processor will not\r
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
- ///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved2:14;\r
- ///\r
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
- ///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved3:8;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_ATOM_BBL_CR_CTL3_REGISTER;\r
-\r
-\r
-/**\r
- Shared.\r
-\r
- @param ECX MSR_ATOM_PERF_STATUS (0x00000198)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_ATOM_PERF_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_ATOM_PERF_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_ATOM_PERF_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);\r
- AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_ATOM_PERF_STATUS 0x00000198\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_ATOM_PERF_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] Current Performance State Value.\r
- ///\r
- UINT32 CurrentPerformanceStateValue:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:8;\r
- ///\r
- /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r
- /// configured for the processor.\r
- ///\r
- UINT32 MaximumBusRatio:5;\r
- UINT32 Reserved3:19;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_ATOM_PERF_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Shared.\r
-\r
- @param ECX MSR_ATOM_THERM2_CTL (0x0000019D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_ATOM_THERM2_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_ATOM_THERM2_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_ATOM_THERM2_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);\r
- AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
-**/\r
-#define MSR_ATOM_THERM2_CTL 0x0000019D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_ATOM_THERM2_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
- /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
- /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
- /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
- /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r
- ///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_ATOM_THERM2_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Fast-Strings Enable See Table 2-2.\r
- ///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 2-2. Default value is 0.\r
- ///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:1;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
- /// the processor to indicate a pending break event within the processor 0\r
- /// = Indicates compatible FERR# signaling behavior This bit must be set\r
- /// to 1 to support XAPIC interrupt model usage.\r
- ///\r
- UINT32 FERR:1;\r
- ///\r
- /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 PEBS:1;\r
- ///\r
- /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
- /// thermal sensor indicates that the die temperature is at the\r
- /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r
- /// TM2 will reduce the bus to core ratio and voltage according to the\r
- /// value last written to MSR_THERM2_CTL bits 15:0.\r
- /// When this bit is clear (0, default), the processor does not change\r
- /// the VID signals or the bus to core ratio when the processor enters a\r
- /// thermally managed state. The BIOS must enable this feature if the\r
- /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is\r
- /// not set, this feature is not supported and BIOS must not alter the\r
- /// contents of the TM2 bit location. The processor is operating out of\r
- /// specification if both this bit and the TM1 bit are set to 0.\r
- ///\r
- UINT32 TM2:1;\r
- UINT32 Reserved5:2;\r
- ///\r
- /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
- ///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved7:1;\r
- ///\r
- /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r
- /// (R/WO) When set, this bit causes the following bits to become\r
- /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this\r
- /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must\r
- /// be set before an Enhanced Intel SpeedStep Technology transition is\r
- /// requested. This bit is cleared on reset.\r
- ///\r
- UINT32 EISTLock:1;\r
- UINT32 Reserved8:1;\r
- ///\r
- /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.\r
- ///\r
- UINT32 LimitCpuidMaxval:1;\r
- ///\r
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved9:8;\r
- UINT32 Reserved10:2;\r
- ///\r
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 XD:1;\r
- UINT32 Reserved11:29;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)\r
- that points to the MSR containing the most recent branch record. See\r
- MSR_LASTBRANCH_0_FROM_IP (at 40H).\r
-\r
- @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
- last branch instruction that the processor executed prior to the last\r
- exception that was generated or the last interrupt that was handled.\r
-\r
- @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);\r
- @endcode\r
- @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
-**/\r
-#define MSR_ATOM_LER_FROM_LIP 0x000001DD\r
-\r
-\r
-/**\r
- Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
- to the target of the last branch instruction that the processor executed\r
- prior to the last exception that was generated or the last interrupt that\r
- was handled.\r
-\r
- @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);\r
- @endcode\r
- @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
-**/\r
-#define MSR_ATOM_LER_TO_LIP 0x000001DE\r
-\r
-\r
-/**\r
- Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
- (PEBS).".\r
-\r
- @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_ATOM_PEBS_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
-**/\r
-#define MSR_ATOM_PEBS_ENABLE 0x000003F1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
- ///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_ATOM_PEBS_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Package. Package C2 Residency Note: C-state values are processor specific\r
- C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
- C-States. Package. Package C2 Residency Counter. (R/O) Time that this\r
- package is in processor-specific C2 states since last reset. Counts at 1 Mhz\r
- frequency.\r
-\r
- @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);\r
- AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
-**/\r
-#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8\r
-\r
-\r
-/**\r
- Package. Package C4 Residency Note: C-state values are processor specific\r
- C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
- C-States. Package. Package C4 Residency Counter. (R/O) Time that this\r
- package is in processor-specific C4 states since last reset. Counts at 1 Mhz\r
- frequency.\r
-\r
- @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);\r
- AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.\r
-**/\r
-#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9\r
-\r
-\r
-/**\r
- Package. Package C6 Residency Note: C-state values are processor specific\r
- C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
- C-States. Package. Package C6 Residency Counter. (R/O) Time that this\r
- package is in processor-specific C6 states since last reset. Counts at 1 Mhz\r
- frequency.\r
-\r
- @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __BROADWELL_MSR_H__\r
-#define __BROADWELL_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel processors based on the Broadwell microarchitecture?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x3D || \\r
- DisplayModel == 0x47 || \\r
- DisplayModel == 0x4F || \\r
- DisplayModel == 0x56 \\r
- ) \\r
- )\r
-\r
-/**\r
- Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
- Facilities.".\r
-\r
- @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Ovf_PMC0.\r
- ///\r
- UINT32 Ovf_PMC0:1;\r
- ///\r
- /// [Bit 1] Ovf_PMC1.\r
- ///\r
- UINT32 Ovf_PMC1:1;\r
- ///\r
- /// [Bit 2] Ovf_PMC2.\r
- ///\r
- UINT32 Ovf_PMC2:1;\r
- ///\r
- /// [Bit 3] Ovf_PMC3.\r
- ///\r
- UINT32 Ovf_PMC3:1;\r
- UINT32 Reserved1:28;\r
- ///\r
- /// [Bit 32] Ovf_FixedCtr0.\r
- ///\r
- UINT32 Ovf_FixedCtr0:1;\r
- ///\r
- /// [Bit 33] Ovf_FixedCtr1.\r
- ///\r
- UINT32 Ovf_FixedCtr1:1;\r
- ///\r
- /// [Bit 34] Ovf_FixedCtr2.\r
- ///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
- ///\r
- /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
- /// Addresses (ToPA).".\r
- ///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:5;\r
- ///\r
- /// [Bit 61] Ovf_Uncore.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Ovf_BufDSSAVE.\r
- ///\r
- UINT32 OvfBuf:1;\r
- ///\r
- /// [Bit 63] CondChgd.\r
- ///\r
- UINT32 CondChgd:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
- specific C-state code names, unrelated to MWAIT extension C-state parameters\r
- or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
-\r
- @param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
-**/\r
-#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
- /// processor-specific C-state code name (consuming the least power) for\r
- /// the package. The default is set as factory-configured package C-state\r
- /// limit. The following C-state code name encodings are supported: 0000b:\r
- /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
- /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r
- ///\r
- UINT32 Limit:4;\r
- UINT32 Reserved1:6;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
- ///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO).\r
- ///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
- ///\r
- /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
- ///\r
- UINT32 C3AutoDemotion:1;\r
- ///\r
- /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
- ///\r
- UINT32 C1AutoDemotion:1;\r
- ///\r
- /// [Bit 27] Enable C3 Undemotion (R/W).\r
- ///\r
- UINT32 C3Undemotion:1;\r
- ///\r
- /// [Bit 28] Enable C1 Undemotion (R/W).\r
- ///\r
- UINT32 C1Undemotion:1;\r
- ///\r
- /// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r
- ///\r
- UINT32 CStateAutoDemotion:1;\r
- ///\r
- /// [Bit 30] Enable Package C-State Undemotion (R/W).\r
- ///\r
- UINT32 CStateUndemotion:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r
- @endcode\r
- @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
- /// limit of 1 core active.\r
- ///\r
- UINT32 Maximum1C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
- /// limit of 2 core active.\r
- ///\r
- UINT32 Maximum2C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
- /// limit of 3 core active.\r
- ///\r
- UINT32 Maximum3C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
- /// limit of 4 core active.\r
- ///\r
- UINT32 Maximum4C:8;\r
- ///\r
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
- /// limit of 5core active.\r
- ///\r
- UINT32 Maximum5C:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
- /// limit of 6core active.\r
- ///\r
- UINT32 Maximum6C:8;\r
- UINT32 Reserved:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
- fields represent the widest possible range of uncore frequencies. Writing to\r
- these fields allows software to control the minimum and the maximum\r
- frequency that hardware will select.\r
-\r
- @param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);\r
- AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
- /// LLC/Ring.\r
- ///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
- /// possible ratio of the LLC/Ring.\r
- ///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved3:17;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
-\r
-/**\r
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __CORE2_MSR_H__\r
-#define __CORE2_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel(R) Core(TM) 2 Processor Family?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x0F || \\r
- DisplayModel == 0x17 \\r
- ) \\r
- )\r
-\r
-/**\r
- Shared. Model Specific Platform ID (R).\r
-\r
- @param ECX MSR_CORE2_PLATFORM_ID (0x00000017)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_PLATFORM_ID_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);\r
- @endcode\r
- @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
-**/\r
-#define MSR_CORE2_PLATFORM_ID 0x00000017\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
- ///\r
- UINT32 MaximumQualifiedRatio:5;\r
- UINT32 Reserved2:19;\r
- UINT32 Reserved3:18;\r
- ///\r
- /// [Bits 52:50] See Table 2-2.\r
- ///\r
- UINT32 PlatformId:3;\r
- UINT32 Reserved4:11;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_PLATFORM_ID_REGISTER;\r
-\r
-\r
-/**\r
- Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
- processor features; (R) indicates current processor configuration.\r
-\r
- @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_EBL_CR_POWERON_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);\r
- AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
-**/\r
-#define MSR_CORE2_EBL_CR_POWERON 0x0000002A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
- /// Note: Not all processor implements R/W.\r
- ///\r
- UINT32 DataErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
- /// Note: Not all processor implements R/W.\r
- ///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
- /// all processor implements R/W.\r
- ///\r
- UINT32 MCERR_DriveEnable:1;\r
- ///\r
- /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r
- /// Not all processor implements R/W.\r
- ///\r
- UINT32 AddressParityEnable:1;\r
- UINT32 Reserved2:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
- /// all processor implements R/W.\r
- ///\r
- UINT32 BINIT_DriverEnable:1;\r
- ///\r
- /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 OutputTriStateEnable:1;\r
- ///\r
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 ExecuteBIST:1;\r
- ///\r
- /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 MCERR_ObservationEnabled:1;\r
- ///\r
- /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.\r
- ///\r
- UINT32 IntelTXTCapableChipset:1;\r
- ///\r
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
- ///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bits 17:16] APIC Cluster ID (R/O).\r
- ///\r
- UINT32 APICClusterID:2;\r
- ///\r
- /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =\r
- /// Non-integer ratio.\r
- ///\r
- UINT32 NonIntegerBusRatio:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bits 21:20] Symmetric Arbitration ID (R/O).\r
- ///\r
- UINT32 SymmetricArbitrationID:2;\r
- ///\r
- /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
- ///\r
- UINT32 IntegerBusFrequencyRatio:5;\r
- UINT32 Reserved7:5;\r
- UINT32 Reserved8:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_EBL_CR_POWERON_REGISTER;\r
-\r
-\r
-/**\r
- Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.\r
-\r
- @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_CORE2_FEATURE_CONTROL 0x0000003A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:3;\r
- ///\r
- /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock\r
- /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read\r
- /// visible and writeable while in SMM.\r
- ///\r
- UINT32 SMRREnable:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch\r
- record registers on the last branch record stack. The From_IP part of the\r
- stack contains pointers to the source instruction. See also: - Last Branch\r
- Record Stack TOS at 1C9H - Section 17.5.\r
-\r
- @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);\r
- AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);\r
- @endcode\r
- @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
- MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
- MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
- MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040\r
-#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041\r
-#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042\r
-#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043\r
-/// @}\r
-\r
-\r
-/**\r
- Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch\r
- record registers on the last branch record stack. This To_IP part of the\r
- stack contains pointers to the destination instruction.\r
-\r
- @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);\r
- AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);\r
- @endcode\r
- @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
- MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
- MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
- MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060\r
-#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061\r
-#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062\r
-#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063\r
-/// @}\r
-\r
-\r
-/**\r
- Unique. System Management Mode Base Address register (WO in SMM)\r
- Model-specific implementation of SMRR-like interface, read visible and write\r
- only in SMM.\r
-\r
- @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = 0;\r
- AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.\r
-**/\r
-#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:12;\r
- ///\r
- /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r
- ///\r
- UINT32 PhysBase:20;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_SMRR_PHYSBASE_REGISTER;\r
-\r
-\r
-/**\r
- Unique. System Management Mode Physical Address Mask register (WO in SMM)\r
- Model-specific implementation of SMRR-like interface, read visible and write\r
- only in SMM.\r
-\r
- @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr;\r
-\r
- Msr.Uint64 = 0;\r
- AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.\r
-**/\r
-#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:11;\r
- ///\r
- /// [Bit 11] Valid. Physical address base and range mask are valid.\r
- ///\r
- UINT32 Valid:1;\r
- ///\r
- /// [Bits 31:12] PhysMask. SMRR physical address range mask.\r
- ///\r
- UINT32 PhysMask:20;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_SMRR_PHYSMASK_REGISTER;\r
-\r
-\r
-/**\r
- Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
- bus clock speed for processors based on Intel Core microarchitecture:.\r
-\r
- @param ECX MSR_CORE2_FSB_FREQ (0x000000CD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_FSB_FREQ_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_FSB_FREQ_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_FSB_FREQ_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);\r
- @endcode\r
- @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
-**/\r
-#define MSR_CORE2_FSB_FREQ 0x000000CD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_FSB_FREQ\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] - Scalable Bus Speed\r
- /// 101B: 100 MHz (FSB 400)\r
- /// 001B: 133 MHz (FSB 533)\r
- /// 011B: 167 MHz (FSB 667)\r
- /// 010B: 200 MHz (FSB 800)\r
- /// 000B: 267 MHz (FSB 1067)\r
- /// 100B: 333 MHz (FSB 1333)\r
- ///\r
- /// 133.33 MHz should be utilized if performing calculation with System\r
- /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if\r
- /// performing calculation with System Bus Speed when encoding is 011B.\r
- /// 266.67 MHz should be utilized if performing calculation with System\r
- /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if\r
- /// performing calculation with System Bus Speed when encoding is 100B.\r
- ///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_FSB_FREQ_REGISTER;\r
-\r
-/**\r
- Shared.\r
-\r
- @param ECX MSR_CORE2_PERF_STATUS (0x00000198)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_PERF_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_PERF_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_PERF_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_CORE2_PERF_STATUS 0x00000198\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_PERF_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] Current Performance State Value.\r
- ///\r
- UINT32 CurrentPerformanceStateValue:16;\r
- UINT32 Reserved1:15;\r
- ///\r
- /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default\r
- /// is cleared.\r
- ///\r
- UINT32 XEOperation:1;\r
- UINT32 Reserved2:8;\r
- ///\r
- /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r
- /// configured for the processor.\r
- ///\r
- UINT32 MaximumBusRatio:5;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio\r
- /// is enabled. Applies processors based on Enhanced Intel Core\r
- /// microarchitecture.\r
- ///\r
- UINT32 NonIntegerBusRatio:1;\r
- UINT32 Reserved4:17;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_PERF_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_THERM2_CTL (0x0000019D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_THERM2_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_THERM2_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_THERM2_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
-**/\r
-#define MSR_CORE2_THERM2_CTL 0x0000019D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_THERM2_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
- /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
- /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
- /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
- /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r
- ///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_THERM2_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Enable Misc. Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Fast-Strings Enable See Table 2-2.\r
- ///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the\r
- /// hardware prefetcher operation on streams of data. When clear\r
- /// (default), enables the prefetch queue. Disabling of the hardware\r
- /// prefetcher may impact processor performance.\r
- ///\r
- UINT32 HardwarePrefetcherDisable:1;\r
- ///\r
- /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
- /// the processor to indicate a pending break event within the processor 0\r
- /// = Indicates compatible FERR# signaling behavior This bit must be set\r
- /// to 1 to support XAPIC interrupt model usage.\r
- ///\r
- UINT32 FERR:1;\r
- ///\r
- /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 PEBS:1;\r
- ///\r
- /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
- /// thermal sensor indicates that the die temperature is at the\r
- /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r
- /// TM2 will reduce the bus to core ratio and voltage according to the\r
- /// value last written to MSR_THERM2_CTL bits 15:0.\r
- /// When this bit is clear (0, default), the processor does not change\r
- /// the VID signals or the bus to core ratio when the processor enters a\r
- /// thermally managed state. The BIOS must enable this feature if the\r
- /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is\r
- /// not set, this feature is not supported and BIOS must not alter the\r
- /// contents of the TM2 bit location. The processor is operating out of\r
- /// specification if both this bit and the TM1 bit are set to 0.\r
- ///\r
- UINT32 TM2:1;\r
- UINT32 Reserved4:2;\r
- ///\r
- /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
- ///\r
- UINT32 MONITOR:1;\r
- ///\r
- /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set\r
- /// to 1, the processor fetches the cache line that contains data\r
- /// currently required by the processor. When set to 0, the processor\r
- /// fetches cache lines that comprise a cache line pair (128 bytes).\r
- /// Single processor platforms should not set this bit. Server platforms\r
- /// should set or clear this bit based on platform performance observed in\r
- /// validation and testing. BIOS may contain a setup option that controls\r
- /// the setting of this bit.\r
- ///\r
- UINT32 AdjacentCacheLinePrefetchDisable:1;\r
- ///\r
- /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r
- /// (R/WO) When set, this bit causes the following bits to become\r
- /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this\r
- /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must\r
- /// be set before an Enhanced Intel SpeedStep Technology transition is\r
- /// requested. This bit is cleared on reset.\r
- ///\r
- UINT32 EISTLock:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.\r
- ///\r
- UINT32 LimitCpuidMaxval:1;\r
- ///\r
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:2;\r
- ///\r
- /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU\r
- /// L1 data cache prefetcher is disabled. The default value after reset is\r
- /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is\r
- /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple\r
- /// loads from the same line done within a time limit, the DCU prefetcher\r
- /// assumes the next line will be required. The next line is prefetched in\r
- /// to the L1 data cache from memory or L2.\r
- ///\r
- UINT32 DCUPrefetcherDisable:1;\r
- ///\r
- /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that\r
- /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled\r
- /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).\r
- /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]\r
- /// reports the processor's support of IDA is enabled. Note: the power-on\r
- /// default value is used by BIOS to detect hardware support of IDA. If\r
- /// power-on default value is 1, IDA is available in the processor. If\r
- /// power-on default value is 0, IDA is not available.\r
- ///\r
- UINT32 IDADisable:1;\r
- ///\r
- /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP\r
- /// prefetcher is disabled. The default value after reset is 0. BIOS may\r
- /// write '1' to disable this feature. The IP prefetcher is an L1 data\r
- /// cache prefetcher. The IP prefetcher looks for sequential load history\r
- /// to determine whether to prefetch the next expected data into the L1\r
- /// cache from memory or L2.\r
- ///\r
- UINT32 IPPrefetcherDisable:1;\r
- UINT32 Reserved10:24;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
- that points to the MSR containing the most recent branch record. See\r
- MSR_LASTBRANCH_0_FROM_IP (at 40H).\r
-\r
- @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
- last branch instruction that the processor executed prior to the last\r
- exception that was generated or the last interrupt that was handled.\r
-\r
- @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);\r
- @endcode\r
- @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
-**/\r
-#define MSR_CORE2_LER_FROM_LIP 0x000001DD\r
-\r
-\r
-/**\r
- Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
- to the target of the last branch instruction that the processor executed\r
- prior to the last exception that was generated or the last interrupt that\r
- was handled.\r
-\r
- @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);\r
- @endcode\r
- @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
-**/\r
-#define MSR_CORE2_LER_TO_LIP 0x000001DE\r
-\r
-\r
-/**\r
- Unique. Fixed-Function Performance Counter Register n (R/W).\r
-\r
- @param ECX MSR_CORE2_PERF_FIXED_CTRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);\r
- AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);\r
- @endcode\r
- @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.\r
- MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.\r
- MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.\r
- @{\r
-**/\r
-#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309\r
-#define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A\r
-#define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B\r
-/// @}\r
-\r
-\r
-/**\r
- Unique. RO. This applies to processors that do not support architectural\r
- perfmon version 2.\r
-\r
- @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);\r
- AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.\r
-**/\r
-#define MSR_CORE2_PERF_CAPABILITIES 0x00000345\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 5:0] LBR Format. See Table 2-2.\r
- ///\r
- UINT32 LBR_FMT:6;\r
- ///\r
- /// [Bit 6] PEBS Record Format.\r
- ///\r
- UINT32 PEBS_FMT:1;\r
- ///\r
- /// [Bit 7] PEBSSaveArchRegs. See Table 2-2.\r
- ///\r
- UINT32 PEBS_ARCH_REG:1;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_PERF_CAPABILITIES_REGISTER;\r
-\r
-\r
-/**\r
- Unique. Fixed-Function-Counter Control Register (R/W).\r
-\r
- @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);\r
- AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);\r
- @endcode\r
- @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.\r
-**/\r
-#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D\r
-\r
-\r
-/**\r
- Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
-\r
- @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E\r
-\r
-\r
-/**\r
- Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
-\r
- @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);\r
- AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);\r
- @endcode\r
- @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.\r
-**/\r
-#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F\r
-\r
-\r
-/**\r
- Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
-\r
- @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390\r
-\r
-\r
-/**\r
- Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
- (PEBS).".\r
-\r
- @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE2_PEBS_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
-**/\r
-#define MSR_CORE2_PEBS_ENABLE 0x000003F1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
- ///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE2_PEBS_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon\r
- processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
-\r
- @param ECX MSR_CORE2_EMON_L3_CTR_CTLn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);\r
- AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);\r
- @endcode\r
- @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.\r
- MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.\r
- MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.\r
- MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.\r
- MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.\r
- MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.\r
- MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.\r
- MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r
- @{\r
-**/\r
-#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC\r
-#define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD\r
-#define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE\r
-#define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF\r
-#define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0\r
-#define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1\r
-#define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2\r
-#define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3\r
-/// @}\r
-\r
-\r
-/**\r
- Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor\r
- 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
-\r
- @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);\r
- @endcode\r
- @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.\r
-**/\r
-#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel Core Solo and Intel Core Duo Processors.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __CORE_MSR_H__\r
-#define __CORE_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel Core Solo and Intel Core Duo Processors?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x0E \\r
- ) \\r
- )\r
-\r
-/**\r
- Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.\r
-\r
- @param ECX MSR_CORE_P5_MC_ADDR (0x00000000)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);\r
- AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);\r
- @endcode\r
- @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
-**/\r
-#define MSR_CORE_P5_MC_ADDR 0x00000000\r
-\r
-\r
-/**\r
- Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.\r
-\r
- @param ECX MSR_CORE_P5_MC_TYPE (0x00000001)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);\r
- AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);\r
- @endcode\r
- @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
-**/\r
-#define MSR_CORE_P5_MC_TYPE 0x00000001\r
-\r
-\r
-/**\r
- Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
- processor features; (R) indicates current processor configuration.\r
-\r
- @param ECX MSR_CORE_EBL_CR_POWERON (0x0000002A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE_EBL_CR_POWERON_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);\r
- AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
-**/\r
-#define MSR_CORE_EBL_CR_POWERON 0x0000002A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
- /// Note: Not all processor implements R/W.\r
- ///\r
- UINT32 DataErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
- /// Note: Not all processor implements R/W.\r
- ///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
- /// all processor implements R/W.\r
- ///\r
- UINT32 MCERR_DriveEnable:1;\r
- ///\r
- /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r
- /// Not all processor implements R/W.\r
- ///\r
- UINT32 AddressParityEnable:1;\r
- UINT32 Reserved2:2;\r
- ///\r
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
- /// all processor implements R/W.\r
- ///\r
- UINT32 BINIT_DriverEnable:1;\r
- ///\r
- /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 OutputTriStateEnable:1;\r
- ///\r
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 ExecuteBIST:1;\r
- ///\r
- /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 MCERR_ObservationEnabled:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
- ///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bits 17:16] APIC Cluster ID (R/O).\r
- ///\r
- UINT32 APICClusterID:2;\r
- ///\r
- /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.\r
- ///\r
- UINT32 SystemBusFrequency:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bits 21:20] Symmetric Arbitration ID (R/O).\r
- ///\r
- UINT32 SymmetricArbitrationID:2;\r
- ///\r
- /// [Bits 26:22] Clock Frequency Ratio (R/O).\r
- ///\r
- UINT32 ClockFrequencyRatio:5;\r
- UINT32 Reserved7:5;\r
- UINT32 Reserved8:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE_EBL_CR_POWERON_REGISTER;\r
-\r
-\r
-/**\r
- Unique. Last Branch Record n (R/W) One of 8 last branch record registers on\r
- the last branch record stack: bits 31-0 hold the 'from' address and bits\r
- 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at\r
- 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording\r
- (Pentium M Processors).".\r
-\r
- @param ECX MSR_CORE_LASTBRANCH_n\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);\r
- AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);\r
- @endcode\r
- @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
- MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
- MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
- MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
- MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
- MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
- MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
- MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
- @{\r
-**/\r
-#define MSR_CORE_LASTBRANCH_0 0x00000040\r
-#define MSR_CORE_LASTBRANCH_1 0x00000041\r
-#define MSR_CORE_LASTBRANCH_2 0x00000042\r
-#define MSR_CORE_LASTBRANCH_3 0x00000043\r
-#define MSR_CORE_LASTBRANCH_4 0x00000044\r
-#define MSR_CORE_LASTBRANCH_5 0x00000045\r
-#define MSR_CORE_LASTBRANCH_6 0x00000046\r
-#define MSR_CORE_LASTBRANCH_7 0x00000047\r
-/// @}\r
-\r
-\r
-/**\r
- Shared. Scalable Bus Speed (RO) This field indicates the scalable bus\r
- clock speed:.\r
-\r
- @param ECX MSR_CORE_FSB_FREQ (0x000000CD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE_FSB_FREQ_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE_FSB_FREQ_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE_FSB_FREQ_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);\r
- @endcode\r
- @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
-**/\r
-#define MSR_CORE_FSB_FREQ 0x000000CD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE_FSB_FREQ\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] - Scalable Bus Speed\r
- /// 101B: 100 MHz (FSB 400)\r
- /// 001B: 133 MHz (FSB 533)\r
- /// 011B: 167 MHz (FSB 667)\r
- ///\r
- /// 133.33 MHz should be utilized if performing calculation with System Bus\r
- /// Speed when encoding is 101B. 166.67 MHz should be utilized if\r
- /// performing calculation with System Bus Speed when encoding is 001B.\r
- ///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE_FSB_FREQ_REGISTER;\r
-\r
-\r
-/**\r
- Shared.\r
-\r
- @param ECX MSR_CORE_BBL_CR_CTL3 (0x0000011E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE_BBL_CR_CTL3_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);\r
- AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
-**/\r
-#define MSR_CORE_BBL_CR_CTL3 0x0000011E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
- /// Indicates if the L2 is hardware-disabled.\r
- ///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
- /// Disabled (default) Until this bit is set the processor will not\r
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
- ///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved2:14;\r
- ///\r
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
- ///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved3:8;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE_BBL_CR_CTL3_REGISTER;\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_THERM2_CTL (0x0000019D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE_THERM2_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE_THERM2_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE_THERM2_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);\r
- AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
-**/\r
-#define MSR_CORE_THERM2_CTL 0x0000019D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE_THERM2_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
- /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
- /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
- /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
- /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
- ///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE_THERM2_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_CORE_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:3;\r
- ///\r
- /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
- /// the processor to indicate a pending break event within the processor 0\r
- /// = Indicates compatible FERR# signaling behavior This bit must be set\r
- /// to 1 to support XAPIC interrupt model usage.\r
- ///\r
- UINT32 FERR:1;\r
- ///\r
- /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
- ///\r
- UINT32 BTS:1;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
- /// thermal sensor indicates that the die temperature is at the\r
- /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r
- /// TM2 will reduce the bus to core ratio and voltage according to the\r
- /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear\r
- /// (0, default), the processor does not change the VID signals or the bus\r
- /// to core ratio when the processor enters a thermal managed state. If\r
- /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID\r
- /// with EAX = 1, then this feature is not supported and BIOS must not\r
- /// alter the contents of this bit location. The processor is operating\r
- /// out of spec if both this bit and the TM1 bit are set to disabled\r
- /// states.\r
- ///\r
- UINT32 TM2:1;\r
- UINT32 Reserved5:2;\r
- ///\r
- /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
- /// Enhanced Intel SpeedStep Technology enabled.\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
- ///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved7:1;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this\r
- /// bit may cause behavior in software that depends on the availability of\r
- /// CPUID leaves greater than 2.\r
- ///\r
- UINT32 LimitCpuidMaxval:1;\r
- UINT32 Reserved9:9;\r
- UINT32 Reserved10:2;\r
- ///\r
- /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 XD:1;\r
- UINT32 Reserved11:29;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
- that points to the MSR containing the most recent branch record. See\r
- MSR_LASTBRANCH_0_FROM_IP (at 40H).\r
-\r
- @param ECX MSR_CORE_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_CORE_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
- last branch instruction that the processor executed prior to the last\r
- exception that was generated or the last interrupt that was handled.\r
-\r
- @param ECX MSR_CORE_LER_FROM_LIP (0x000001DD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);\r
- @endcode\r
- @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
-**/\r
-#define MSR_CORE_LER_FROM_LIP 0x000001DD\r
-\r
-\r
-/**\r
- Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
- to the target of the last branch instruction that the processor executed\r
- prior to the last exception that was generated or the last interrupt that\r
- was handled.\r
-\r
- @param ECX MSR_CORE_LER_TO_LIP (0x000001DE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);\r
- @endcode\r
- @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
-**/\r
-#define MSR_CORE_LER_TO_LIP 0x000001DE\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRPHYSBASEn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);\r
- AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.\r
- MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.\r
- MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.\r
- MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.\r
- MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.\r
- MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.\r
- MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.\r
- MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r
- @{\r
-**/\r
-#define MSR_CORE_MTRRPHYSBASE0 0x00000200\r
-#define MSR_CORE_MTRRPHYSBASE1 0x00000202\r
-#define MSR_CORE_MTRRPHYSBASE2 0x00000204\r
-#define MSR_CORE_MTRRPHYSBASE3 0x00000206\r
-#define MSR_CORE_MTRRPHYSBASE4 0x00000208\r
-#define MSR_CORE_MTRRPHYSBASE5 0x0000020A\r
-#define MSR_CORE_MTRRPHYSMASK6 0x0000020D\r
-#define MSR_CORE_MTRRPHYSMASK7 0x0000020F\r
-/// @}\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRPHYSMASKn (0x00000201)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);\r
- AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.\r
- MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.\r
- MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.\r
- MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.\r
- MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.\r
- MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.\r
- MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.\r
- MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r
- @{\r
-**/\r
-#define MSR_CORE_MTRRPHYSMASK0 0x00000201\r
-#define MSR_CORE_MTRRPHYSMASK1 0x00000203\r
-#define MSR_CORE_MTRRPHYSMASK2 0x00000205\r
-#define MSR_CORE_MTRRPHYSMASK3 0x00000207\r
-#define MSR_CORE_MTRRPHYSMASK4 0x00000209\r
-#define MSR_CORE_MTRRPHYSMASK5 0x0000020B\r
-#define MSR_CORE_MTRRPHYSBASE6 0x0000020C\r
-#define MSR_CORE_MTRRPHYSBASE7 0x0000020E\r
-/// @}\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX64K_00000 (0x00000250)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX64K_00000 0x00000250\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX16K_80000 (0x00000258)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX16K_80000 0x00000258\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX16K_A0000 (0x00000259)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX16K_A0000 0x00000259\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX4K_C0000 (0x00000268)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX4K_C0000 0x00000268\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX4K_C8000 (0x00000269)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX4K_C8000 0x00000269\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);\r
- AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);\r
- @endcode\r
- @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r
-**/\r
-#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_CORE_MC4_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);\r
- AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);\r
- @endcode\r
- @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
-**/\r
-#define MSR_CORE_MC4_CTL 0x0000040C\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_CORE_MC4_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
-**/\r
-#define MSR_CORE_MC4_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC4_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_CORE_MC4_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);\r
- @endcode\r
- @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
-**/\r
-#define MSR_CORE_MC4_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC3_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_CORE_MC3_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
-**/\r
-#define MSR_CORE_MC3_ADDR 0x00000412\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MC3_MISC (0x00000413)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);\r
- AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);\r
- @endcode\r
- @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.\r
-**/\r
-#define MSR_CORE_MC3_MISC 0x00000413\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MC5_CTL (0x00000414)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);\r
- AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);\r
- @endcode\r
- @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
-**/\r
-#define MSR_CORE_MC5_CTL 0x00000414\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MC5_STATUS (0x00000415)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);\r
- AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);\r
- @endcode\r
- @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
-**/\r
-#define MSR_CORE_MC5_STATUS 0x00000415\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MC5_ADDR (0x00000416)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);\r
- AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);\r
- @endcode\r
- @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
-**/\r
-#define MSR_CORE_MC5_ADDR 0x00000416\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE_MC5_MISC (0x00000417)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);\r
- AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);\r
- @endcode\r
- @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
-**/\r
-#define MSR_CORE_MC5_MISC 0x00000417\r
-\r
-\r
-/**\r
- Unique. See Table 2-2.\r
-\r
- @param ECX MSR_CORE_IA32_EFER (0xC0000080)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_CORE_IA32_EFER_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_CORE_IA32_EFER_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_CORE_IA32_EFER_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);\r
- AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);\r
- @endcode\r
- @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.\r
-**/\r
-#define MSR_CORE_IA32_EFER 0xC0000080\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_CORE_IA32_EFER\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:11;\r
- ///\r
- /// [Bit 11] Execute Disable Bit Enable.\r
- ///\r
- UINT32 NXE:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_CORE_IA32_EFER_REGISTER;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __GOLDMONT_MSR_H__\r
-#define __GOLDMONT_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel Atom processors based on the Goldmont microarchitecture?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x5C \\r
- ) \\r
- )\r
-\r
-/**\r
- Core. Control Features in Intel 64Processor (R/W).\r
-\r
- @param ECX MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Lock bit (R/WL)\r
- ///\r
- UINT32 Lock:1;\r
- ///\r
- /// [Bit 1] Enable VMX inside SMX operation (R/WL)\r
- ///\r
- UINT32 EnableVmxInsideSmx:1;\r
- ///\r
- /// [Bit 2] Enable VMX outside SMX operation (R/WL)\r
- ///\r
- UINT32 EnableVmxOutsideSmx:1;\r
- UINT32 Reserved1:5;\r
- ///\r
- /// [Bits 14:8] SENTER local function enables (R/WL)\r
- ///\r
- UINT32 SenterLocalFunctionEnables:7;\r
- ///\r
- /// [Bit 15] SENTER global functions enable (R/WL)\r
- ///\r
- UINT32 SenterGlobalEnable:1;\r
- UINT32 Reserved2:2;\r
- ///\r
- /// [Bit 18] SGX global functions enable (R/WL)\r
- ///\r
- UINT32 SgxEnable:1;\r
- UINT32 Reserved3:13;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package. See http://biosbits.org.\r
-\r
- @param ECX MSR_GOLDMONT_PLATFORM_INFO (0x000000CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_PLATFORM_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
- /// MHz.\r
- ///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
- ///\r
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
- /// Turbo mode is disabled.\r
- ///\r
- UINT32 RatioLimit:1;\r
- ///\r
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
- /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
- /// programmable.\r
- ///\r
- UINT32 TDPLimit:1;\r
- ///\r
- /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r
- /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r
- /// specify an temperature offset.\r
- ///\r
- UINT32 TJOFFSET:1;\r
- UINT32 Reserved3:1;\r
- UINT32 Reserved4:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
- /// minimum ratio (maximum efficiency) that the processor can operates, in\r
- /// units of 100MHz.\r
- ///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_PLATFORM_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Core. C-State Configuration Control (R/W) Note: C-state values are\r
- processor specific C-state code names, unrelated to MWAIT extension C-state\r
- parameters or ACPI CStates. See http://biosbits.org.\r
-\r
- @param ECX MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type\r
- MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type\r
- MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
- /// processor-specific C-state code name (consuming the least power). for\r
- /// the package. The default is set as factory-configured package C-state\r
- /// limit. The following C-state code name encodings are supported: 0000b:\r
- /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8\r
- /// 0111b: C9 1000b: C10.\r
- ///\r
- UINT32 Limit:4;\r
- UINT32 Reserved1:6;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
- /// IO_read instructions sent to IO register specified by\r
- /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
- ///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
- /// until next reset.\r
- ///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:16;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.\r
- Accessible only while in SMM.\r
-\r
- @param ECX MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_SMM_MCA_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP);\r
- AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
-**/\r
-#define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
- ///\r
- /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
- /// SMM code access restriction is supported and the\r
- /// MSR_SMM_FEATURE_CONTROL is supported.\r
- ///\r
- UINT32 SMM_Code_Access_Chk:1;\r
- ///\r
- /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
- /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r
- /// supported.\r
- ///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;\r
-\r
-\r
-/**\r
- Enable Misc. Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r
- ///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 2-2. Default value is 1.\r
- ///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
- ///\r
- /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
- ///\r
- /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
- ///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
- ///\r
- /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r
- ///\r
- UINT32 LimitCpuidMaxval:1;\r
- ///\r
- /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
- ///\r
- /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
- /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
- /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
- /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
- /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
- /// the power-on default value is used by BIOS to detect hardware support\r
- /// of turbo mode. If power-on default value is 1, turbo mode is available\r
- /// in the processor. If power-on default value is 0, turbo mode is not\r
- /// available.\r
- ///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Miscellaneous Feature Control (R/W).\r
-\r
- @param ECX MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
- /// L2 hardware prefetcher, which fetches additional lines of code or data\r
- /// into the L2 cache.\r
- ///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
- /// the L1 data cache prefetcher, which fetches the next cache line into\r
- /// L1 data cache.\r
- ///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package. See http://biosbits.org.\r
-\r
- @param ECX MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT);\r
- AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
-**/\r
-#define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables\r
- /// hardware coordination of Enhanced Intel Speedstep Technology request\r
- /// from processor cores; When 1, disables hardware coordination of\r
- /// Enhanced Intel Speedstep Technology requests.\r
- ///\r
- UINT32 EISTHardwareCoordinationDisable:1;\r
- UINT32 Reserved1:21;\r
- ///\r
- /// [Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then\r
- /// thermal interrupt on one core is routed to all cores.\r
- ///\r
- UINT32 ThermalInterruptCoordinationEnable:1;\r
- UINT32 Reserved2:9;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies\r
- Maximum Ratio Limit for each Core Group. Max ratio for groups with more\r
- cores must decrease monotonically. For groups with less than 4 cores, the\r
- max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must\r
- be 22 or less. For groups with more than 5 cores, the max ratio must be 16\r
- or less..\r
-\r
- @param ECX MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT);\r
- AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0\r
- /// Maximum turbo ratio limit when number of active cores is less or equal\r
- /// to Group 0 threshold.\r
- ///\r
- UINT32 MaxRatioLimitGroup0:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1\r
- /// Maximum turbo ratio limit when number of active cores is less or equal\r
- /// to Group 1 threshold and greater than Group 0 threshold.\r
- ///\r
- UINT32 MaxRatioLimitGroup1:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2\r
- /// Maximum turbo ratio limit when number of active cores is less or equal\r
- /// to Group 2 threshold and greater than Group 1 threshold.\r
- ///\r
- UINT32 MaxRatioLimitGroup2:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3\r
- /// Maximum turbo ratio limit when number of active cores is less or equal\r
- /// to Group 3 threshold and greater than Group 2 threshold.\r
- ///\r
- UINT32 MaxRatioLimitGroup3:8;\r
- ///\r
- /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4\r
- /// Maximum turbo ratio limit when number of active cores is less or equal\r
- /// to Group 4 threshold and greater than Group 3 threshold.\r
- ///\r
- UINT32 MaxRatioLimitGroup4:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5\r
- /// Maximum turbo ratio limit when number of active cores is less or equal\r
- /// to Group 5 threshold and greater than Group 4 threshold.\r
- ///\r
- UINT32 MaxRatioLimitGroup5:8;\r
- ///\r
- /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6\r
- /// Maximum turbo ratio limit when number of active cores is less or equal\r
- /// to Group 6 threshold and greater than Group 5 threshold.\r
- ///\r
- UINT32 MaxRatioLimitGroup6:8;\r
- ///\r
- /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7\r
- /// Maximum turbo ratio limit when number of active cores is less or equal\r
- /// to Group 7 threshold and greater than Group 6 threshold.\r
- ///\r
- UINT32 MaxRatioLimitGroup7:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of\r
- 0 threshold is ignored.\r
-\r
- @param ECX MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT);\r
- AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.\r
-**/\r
-#define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of\r
- /// active cores to operate under Group 0 Max Turbo Ratio limit.\r
- ///\r
- UINT32 CoreCountThresholdGroup0:8;\r
- ///\r
- /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of\r
- /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be\r
- /// greater than Group 0 Core Count.\r
- ///\r
- UINT32 CoreCountThresholdGroup1:8;\r
- ///\r
- /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of\r
- /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be\r
- /// greater than Group 1 Core Count.\r
- ///\r
- UINT32 CoreCountThresholdGroup2:8;\r
- ///\r
- /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of\r
- /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be\r
- /// greater than Group 2 Core Count.\r
- ///\r
- UINT32 CoreCountThresholdGroup3:8;\r
- ///\r
- /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of\r
- /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be\r
- /// greater than Group 3 Core Count.\r
- ///\r
- UINT32 CoreCountThresholdGroup4:8;\r
- ///\r
- /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of\r
- /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be\r
- /// greater than Group 4 Core Count.\r
- ///\r
- UINT32 CoreCountThresholdGroup5:8;\r
- ///\r
- /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of\r
- /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be\r
- /// greater than Group 5 Core Count.\r
- ///\r
- UINT32 CoreCountThresholdGroup6:8;\r
- ///\r
- /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of\r
- /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be\r
- /// greater than Group 6 Core Count and not less than the total number of\r
- /// processor cores in the package. E.g. specify 255.\r
- ///\r
- UINT32 CoreCountThresholdGroup7:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;\r
-\r
-\r
-/**\r
- Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
- "Filtering of Last Branch Records.".\r
-\r
- @param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_LBR_SELECT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT);\r
- AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
-**/\r
-#define MSR_GOLDMONT_LBR_SELECT 0x000001C8\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] CPL_EQ_0.\r
- ///\r
- UINT32 CPL_EQ_0:1;\r
- ///\r
- /// [Bit 1] CPL_NEQ_0.\r
- ///\r
- UINT32 CPL_NEQ_0:1;\r
- ///\r
- /// [Bit 2] JCC.\r
- ///\r
- UINT32 JCC:1;\r
- ///\r
- /// [Bit 3] NEAR_REL_CALL.\r
- ///\r
- UINT32 NEAR_REL_CALL:1;\r
- ///\r
- /// [Bit 4] NEAR_IND_CALL.\r
- ///\r
- UINT32 NEAR_IND_CALL:1;\r
- ///\r
- /// [Bit 5] NEAR_RET.\r
- ///\r
- UINT32 NEAR_RET:1;\r
- ///\r
- /// [Bit 6] NEAR_IND_JMP.\r
- ///\r
- UINT32 NEAR_IND_JMP:1;\r
- ///\r
- /// [Bit 7] NEAR_REL_JMP.\r
- ///\r
- UINT32 NEAR_REL_JMP:1;\r
- ///\r
- /// [Bit 8] FAR_BRANCH.\r
- ///\r
- UINT32 FAR_BRANCH:1;\r
- ///\r
- /// [Bit 9] EN_CALL_STACK.\r
- ///\r
- UINT32 EN_CALL_STACK:1;\r
- UINT32 Reserved1:22;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_LBR_SELECT_REGISTER;\r
-\r
-\r
-/**\r
- Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that\r
- points to the MSR containing the most recent branch record. See\r
- MSR_LASTBRANCH_0_FROM_IP.\r
-\r
- @param ECX MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Core. Power Control Register. See http://biosbits.org.\r
-\r
- @param ECX MSR_GOLDMONT_POWER_CTL (0x000001FC)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_POWER_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL);\r
- AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
-**/\r
-#define MSR_GOLDMONT_POWER_CTL 0x000001FC\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r
- /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r
- /// operating point when all execution cores enter MWAIT (C1).\r
- ///\r
- UINT32 C1EEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_POWER_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
- CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
- the package. Lower 64 bits of an 128-bit external entropy value for key\r
- derivation of an enclave.\r
-\r
- @param ECX MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);\r
- @endcode\r
- @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.\r
-**/\r
-#define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300\r
-\r
-\r
-//\r
-// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.\r
-//\r
-#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0\r
-\r
-\r
-/**\r
- Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of\r
- an 128-bit external entropy value for key derivation of an enclave.\r
-\r
- @param ECX MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);\r
- @endcode\r
- @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.\r
-**/\r
-#define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301\r
-\r
-\r
-//\r
-// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.\r
-//\r
-#define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1\r
-\r
-\r
-/**\r
- Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r
- Monitoring Version 4.".\r
-\r
- @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET);\r
- AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
-**/\r
-#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Set 1 to clear Ovf_PMC0.\r
- ///\r
- UINT32 Ovf_PMC0:1;\r
- ///\r
- /// [Bit 1] Set 1 to clear Ovf_PMC1.\r
- ///\r
- UINT32 Ovf_PMC1:1;\r
- ///\r
- /// [Bit 2] Set 1 to clear Ovf_PMC2.\r
- ///\r
- UINT32 Ovf_PMC2:1;\r
- ///\r
- /// [Bit 3] Set 1 to clear Ovf_PMC3.\r
- ///\r
- UINT32 Ovf_PMC3:1;\r
- UINT32 Reserved1:28;\r
- ///\r
- /// [Bit 32] Set 1 to clear Ovf_FixedCtr0.\r
- ///\r
- UINT32 Ovf_FixedCtr0:1;\r
- ///\r
- /// [Bit 33] Set 1 to clear Ovf_FixedCtr1.\r
- ///\r
- UINT32 Ovf_FixedCtr1:1;\r
- ///\r
- /// [Bit 34] Set 1 to clear Ovf_FixedCtr2.\r
- ///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
- ///\r
- /// [Bit 55] Set 1 to clear Trace_ToPA_PMI.\r
- ///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 58] Set 1 to clear LBR_Frz.\r
- ///\r
- UINT32 LBR_Frz:1;\r
- ///\r
- /// [Bit 59] Set 1 to clear CTR_Frz.\r
- ///\r
- UINT32 CTR_Frz:1;\r
- ///\r
- /// [Bit 60] Set 1 to clear ASCI.\r
- ///\r
- UINT32 ASCI:1;\r
- ///\r
- /// [Bit 61] Set 1 to clear Ovf_Uncore.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.\r
- ///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- ///\r
- /// [Bit 63] Set 1 to clear CondChgd.\r
- ///\r
- UINT32 CondChgd:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
-\r
-\r
-/**\r
- Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r
- Monitoring Version 4.".\r
-\r
- @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET);\r
- AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
-**/\r
-#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.\r
- ///\r
- UINT32 Ovf_PMC0:1;\r
- ///\r
- /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.\r
- ///\r
- UINT32 Ovf_PMC1:1;\r
- ///\r
- /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.\r
- ///\r
- UINT32 Ovf_PMC2:1;\r
- ///\r
- /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.\r
- ///\r
- UINT32 Ovf_PMC3:1;\r
- UINT32 Reserved1:28;\r
- ///\r
- /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.\r
- ///\r
- UINT32 Ovf_FixedCtr0:1;\r
- ///\r
- /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.\r
- ///\r
- UINT32 Ovf_FixedCtr1:1;\r
- ///\r
- /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.\r
- ///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
- ///\r
- /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.\r
- ///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 58] Set 1 to cause LBR_Frz = 1.\r
- ///\r
- UINT32 LBR_Frz:1;\r
- ///\r
- /// [Bit 59] Set 1 to cause CTR_Frz = 1.\r
- ///\r
- UINT32 CTR_Frz:1;\r
- ///\r
- /// [Bit 60] Set 1 to cause ASCI = 1.\r
- ///\r
- UINT32 ASCI:1;\r
- ///\r
- /// [Bit 61] Set 1 to cause Ovf_Uncore.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.\r
- ///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- UINT32 Reserved4:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
-\r
-\r
-/**\r
- Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
- (PEBS).".\r
-\r
- @param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_PEBS_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable PEBS trigger and recording for the programmed event\r
- /// (precise or otherwise) on IA32_PMC0. (R/W).\r
- ///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_PEBS_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C3 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C6 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9\r
-\r
-\r
-/**\r
- Core. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
- Residency Counter. (R/O) Value since last reset that this core is in\r
- processor-specific C3 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY);\r
- AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
-**/\r
-#define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC\r
-\r
-\r
-/**\r
- Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r
- Enhancement. Accessible only while in SMM.\r
-\r
- @param ECX MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r
- /// further changes.\r
- ///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r
- /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r
- /// logical processors are prevented from executing SMM code outside the\r
- /// ranges defined by the SMRR. When set to '1' any logical processor in\r
- /// the package that attempts to execute SMM code not within the ranges\r
- /// defined by the SMRR will assert an unrecoverable MCE.\r
- ///\r
- UINT32 SMM_Code_Chk_En:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r
- processors in the package. Available only while in SMM and\r
- MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.\r
-\r
- @param ECX MSR_GOLDMONT_SMM_DELAYED (0x000004E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_SMM_DELAYED_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED);\r
- AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r
-**/\r
-#define MSR_GOLDMONT_SMM_DELAYED 0x000004E2\r
-\r
-\r
-/**\r
- Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r
- processors in the package. Available only while in SMM.\r
-\r
- @param ECX MSR_GOLDMONT_SMM_BLOCKED (0x000004E3)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_SMM_BLOCKED_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED);\r
- AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r
-**/\r
-#define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3\r
-\r
-\r
-/**\r
- Core. Trace Control Register (R/W).\r
-\r
- @param ECX MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL);\r
- AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r
-**/\r
-#define MSR_IA32_RTIT_CTL 0x00000570\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] TraceEn.\r
- ///\r
- UINT32 TraceEn:1;\r
- ///\r
- /// [Bit 1] CYCEn.\r
- ///\r
- UINT32 CYCEn:1;\r
- ///\r
- /// [Bit 2] OS.\r
- ///\r
- UINT32 OS:1;\r
- ///\r
- /// [Bit 3] User.\r
- ///\r
- UINT32 User:1;\r
- UINT32 Reserved1:3;\r
- ///\r
- /// [Bit 7] CR3 filter.\r
- ///\r
- UINT32 CR3:1;\r
- ///\r
- /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.\r
- ///\r
- UINT32 ToPA:1;\r
- ///\r
- /// [Bit 9] MTCEn.\r
- ///\r
- UINT32 MTCEn:1;\r
- ///\r
- /// [Bit 10] TSCEn.\r
- ///\r
- UINT32 TSCEn:1;\r
- ///\r
- /// [Bit 11] DisRETC.\r
- ///\r
- UINT32 DisRETC:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 13] BranchEn.\r
- ///\r
- UINT32 BranchEn:1;\r
- ///\r
- /// [Bits 17:14] MTCFreq.\r
- ///\r
- UINT32 MTCFreq:4;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bits 22:19] CYCThresh.\r
- ///\r
- UINT32 CYCThresh:4;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bits 27:24] PSBFreq.\r
- ///\r
- UINT32 PSBFreq:4;\r
- UINT32 Reserved5:4;\r
- ///\r
- /// [Bits 35:32] ADDR0_CFG.\r
- ///\r
- UINT32 ADDR0_CFG:4;\r
- ///\r
- /// [Bits 39:36] ADDR1_CFG.\r
- ///\r
- UINT32 ADDR1_CFG:4;\r
- UINT32 Reserved6:24;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
- "RAPL Interfaces.".\r
-\r
- @param ECX MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT);\r
- @endcode\r
- @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
-**/\r
-#define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Power Units. Power related information (in Watts) is in\r
- /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits\r
- /// 3:0. Default value is 1000b, indicating power unit is in 3.9\r
- /// milliWatts increment.\r
- ///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 12:8] Energy Status Units. Energy related information (in\r
- /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned\r
- /// integer represented by bits 12:8. Default value is 01110b, indicating\r
- /// energy unit is in 61 microJoules.\r
- ///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bits 19:16] Time Unit. Time related information (in seconds) is in\r
- /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits\r
- /// 19:16. Default value is 1010b, indicating power unit is in 0.977\r
- /// millisecond.\r
- ///\r
- UINT32 TimeUnit:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r
- processor specific C-state code names, unrelated to MWAIT extension C-state\r
- parameters or ACPI CStates.\r
-\r
- @param ECX MSR_GOLDMONT_PKGC3_IRTL (0x0000060A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_PKGC3_IRTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
- /// that should be used to decide if the package should be put into a\r
- /// package C3 state.\r
- ///\r
- UINT32 InterruptResponseTimeLimit:10;\r
- ///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
- /// of the interrupt response time limit. See Table 2-19 for supported\r
- /// time unit encodings.\r
- ///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
- /// valid and can be used by the processor for package C-sate management.\r
- ///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_PKGC3_IRTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines\r
- the interrupt response time limit used by the processor to manage transition\r
- to package C6 or C7S state. Note: C-state values are processor specific\r
- C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
- CStates.\r
-\r
- @param ECX MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_PKGC_IRTL1_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
- /// that should be used to decide if the package should be put into a\r
- /// package C6 or C7S state.\r
- ///\r
- UINT32 InterruptResponseTimeLimit:10;\r
- ///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
- /// of the interrupt response time limit. See Table 2-19 for supported\r
- /// time unit encodings.\r
- ///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
- /// valid and can be used by the processor for package C-sate management.\r
- ///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_PKGC_IRTL1_REGISTER;\r
-\r
-\r
-/**\r
- Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the\r
- interrupt response time limit used by the processor to manage transition to\r
- package C7 state. Note: C-state values are processor specific C-state code\r
- names, unrelated to MWAIT extension C-state parameters or ACPI CStates.\r
-\r
- @param ECX MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_PKGC_IRTL2_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
- /// that should be used to decide if the package should be put into a\r
- /// package C7 state.\r
- ///\r
- UINT32 InterruptResponseTimeLimit:10;\r
- ///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
- /// of the interrupt response time limit. See Table 2-19 for supported\r
- /// time unit encodings.\r
- ///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
- /// valid and can be used by the processor for package C-sate management.\r
- ///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_PKGC_IRTL2_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C2 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D\r
-\r
-\r
-/**\r
- Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610\r
-\r
-\r
-/**\r
- Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
-\r
- @param ECX MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611\r
-\r
-\r
-/**\r
- Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
-\r
- @param ECX MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS);\r
- @endcode\r
- @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613\r
-\r
-\r
-/**\r
- Package. PKG RAPL Parameters (R/W).\r
-\r
- @param ECX MSR_GOLDMONT_PKG_POWER_INFO (0x00000614)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_PKG_POWER_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package\r
- /// RAPL Domain.".\r
- ///\r
- UINT32 ThermalSpecPower:15;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL\r
- /// Domain.".\r
- ///\r
- UINT32 MinimumPower:15;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL\r
- /// Domain.".\r
- ///\r
- UINT32 MaximumPower:15;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 +\r
- /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value\r
- /// represented. by bits 52:48, "Z" is an unsigned integer represented by\r
- /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of\r
- /// MSR_RAPL_POWER_UNIT.\r
- ///\r
- UINT32 MaximumTimeWindow:7;\r
- UINT32 Reserved4:9;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
- Domain.".\r
-\r
- @param ECX MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618\r
-\r
-\r
-/**\r
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619\r
-\r
-\r
-/**\r
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS);\r
- @endcode\r
- @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO);\r
- AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr);\r
- @endcode\r
- @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
-**/\r
-#define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,.\r
- Package C10 Residency Counter. (R/O) Value since last reset that the entire\r
- SOC is in an S0i3 state. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632\r
-\r
-\r
-/**\r
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639\r
-\r
-\r
-/**\r
- Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641\r
-\r
-\r
-/**\r
- Package. ConfigTDP Control (R/W).\r
-\r
- @param ECX MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO);\r
- AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
-**/\r
-#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
- /// field.\r
- ///\r
- UINT32 MAX_NON_TURBO_RATIO:8;\r
- UINT32 Reserved1:23;\r
- ///\r
- /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
- /// content of this register is locked until a reset.\r
- ///\r
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;\r
-\r
-\r
-/**\r
- Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
- refers to processor core frequency).\r
-\r
- @param ECX MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS);\r
- AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
-**/\r
-#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
- /// reduced below the operating system request due to assertion of\r
- /// external PROCHOT.\r
- ///\r
- UINT32 PROCHOTStatus:1;\r
- ///\r
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to a thermal event.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- ///\r
- /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,\r
- /// frequency is reduced below the operating system request due to\r
- /// package-level power limiting PL1.\r
- ///\r
- UINT32 PL1Status:1;\r
- ///\r
- /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,\r
- /// frequency is reduced below the operating system request due to\r
- /// package-level power limiting PL2.\r
- ///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved1:5;\r
- ///\r
- /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to domain-level power limiting.\r
- ///\r
- UINT32 PowerLimitingStatus:1;\r
- ///\r
- /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to a thermal alert from the\r
- /// Voltage Regulator.\r
- ///\r
- UINT32 VRThermAlertStatus:1;\r
- ///\r
- /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to multi-core turbo limits.\r
- ///\r
- UINT32 MaxTurboLimitStatus:1;\r
- ///\r
- /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to electrical design\r
- /// point constraints (e.g. maximum electrical current consumption).\r
- ///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- ///\r
- /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
- /// is reduced below the operating system request due to Turbo transition\r
- /// attenuation. This prevents performance degradation due to frequent\r
- /// operating ratio changes.\r
- ///\r
- UINT32 TurboTransitionAttenuationStatus:1;\r
- ///\r
- /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency\r
- /// is reduced below the maximum efficiency frequency.\r
- ///\r
- UINT32 MaximumEfficiencyFrequencyStatus:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PROCHOT:1;\r
- ///\r
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ThermalLog:1;\r
- ///\r
- /// [Bit 18] Package-Level PL1 Power Limiting Log When set, indicates\r
- /// that the Package Level PL1 Power Limiting Status bit has asserted\r
- /// since the log bit was last cleared. This log bit will remain set until\r
- /// cleared by software writing 0.\r
- ///\r
- UINT32 PL1Log:1;\r
- ///\r
- /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that\r
- /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
- /// log bit was last cleared. This log bit will remain set until cleared\r
- /// by software writing 0.\r
- ///\r
- UINT32 PL2Log:1;\r
- UINT32 Reserved3:5;\r
- ///\r
- /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
- /// Power Limiting Status bit has asserted since the log bit was last\r
- /// cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 CorePowerLimitingLog:1;\r
- ///\r
- /// [Bit 26] VR Therm Alert Log When set, indicates that the VR Therm\r
- /// Alert Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 VRThermAlertLog:1;\r
- ///\r
- /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo\r
- /// Limit Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 MaxTurboLimitLog:1;\r
- ///\r
- /// [Bit 28] Electrical Design Point Log When set, indicates that the EDP\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ElectricalDesignPointLog:1;\r
- ///\r
- /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
- /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
- /// was last cleared. This log bit will remain set until cleared by\r
- /// software writing 0.\r
- ///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- ///\r
- /// [Bit 30] Maximum Efficiency Frequency Log When set, indicates that\r
- /// the Maximum Efficiency Frequency Status bit has asserted since the log\r
- /// bit was last cleared. This log bit will remain set until cleared by\r
- /// software writing 0.\r
- ///\r
- UINT32 MaximumEfficiencyFrequencyLog:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;\r
-\r
-\r
-/**\r
- Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch\r
- record registers on the last branch record stack. The From_IP part of the\r
- stack contains pointers to the source instruction . See also: - Last Branch\r
- Record Stack TOS at 1C9H - Section 17.6 and record format in Section\r
- 17.4.8.1.\r
-\r
- @param ECX MSR_GOLDMONT_LASTBRANCH_n_FROM_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP);\r
- AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F\r
-#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690\r
-#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691\r
-#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692\r
-#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693\r
-#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694\r
-#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695\r
-#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696\r
-#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697\r
-#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698\r
-#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699\r
-#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A\r
-#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B\r
-#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C\r
-#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D\r
-#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E\r
-#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP\r
- to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 31:0] From Linear Address (R/W).\r
- ///\r
- UINT32 FromLinearAddress:32;\r
- ///\r
- /// [Bit 47:32] From Linear Address (R/W).\r
- ///\r
- UINT32 FromLinearAddressHi:16;\r
- ///\r
- /// [Bits 62:48] Signed extension of bits 47:0.\r
- ///\r
- UINT32 SignedExtension:15;\r
- ///\r
- /// [Bit 63] Mispred.\r
- ///\r
- UINT32 Mispred:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;\r
-\r
-\r
-/**\r
- Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record\r
- registers on the last branch record stack. The To_IP part of the stack\r
- contains pointers to the Destination instruction and elapsed cycles from\r
- last LBR update. See also: - Section 17.6.\r
-\r
- @param ECX MSR_GOLDMONT_LASTBRANCH_n_TO_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP);\r
- AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.\r
- MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF\r
-#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0\r
-#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1\r
-#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2\r
-#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3\r
-#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4\r
-#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5\r
-#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6\r
-#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7\r
-#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8\r
-#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9\r
-#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA\r
-#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB\r
-#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC\r
-#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD\r
-#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE\r
-#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to\r
- #MSR_GOLDMONT_LASTBRANCH_31_TO_IP.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 31:0] Target Linear Address (R/W).\r
- ///\r
- UINT32 TargetLinearAddress:32;\r
- ///\r
- /// [Bit 47:32] Target Linear Address (R/W).\r
- ///\r
- UINT32 TargetLinearAddressHi:16;\r
- ///\r
- /// [Bits 63:48] Elapsed cycles from last update to the LBR.\r
- ///\r
- UINT32 ElapsedCycles:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;\r
-\r
-\r
-/**\r
- Core. Resource Association Register (R/W).\r
-\r
- @param ECX MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC);\r
- AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
-**/\r
-#define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- ///\r
- /// [Bits 33:32] COS (R/W).\r
- ///\r
- UINT32 COS:2;\r
- UINT32 Reserved2:30;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;\r
-\r
-\r
-/**\r
- Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
- ECX=1):EDX.COS_MAX[15:0] >=n.\r
-\r
- @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_n\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n);\r
- AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM.\r
- MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM.\r
- MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.\r
- @{\r
-**/\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to\r
- #MSR_GOLDMONT_IA32_L2_QOS_MASK_2.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r
- ///\r
- UINT32 CBM:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;\r
-\r
-\r
-/**\r
- Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,\r
- ECX=1):EDX.COS_MAX[15:0] >=3.\r
-\r
- @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_3\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3);\r
- AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64);\r
- @endcode\r
- @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.\r
-**/\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r
- ///\r
- UINT32 CBM:20;\r
- UINT32 Reserved1:12;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;\r
-\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __GOLDMONT_PLUS_MSR_H__\r
-#define __GOLDMONT_PLUS_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel Atom processors based on the Goldmont plus microarchitecture?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x7A \\r
- ) \\r
- )\r
-\r
-/**\r
- Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based\r
- Sampling (PEBS).".\r
-\r
- @param ECX MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_GOLDMONT_PLUS_PEBS_ENABLE 0x000003F1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable PEBS trigger and recording for the programmed event\r
- /// (precise or otherwise) on IA32_PMC0.\r
- ///\r
- UINT32 Fix_Me_1:1;\r
- ///\r
- /// [Bit 1] Enable PEBS trigger and recording for the programmed event\r
- /// (precise or otherwise) on IA32_PMC1.\r
- ///\r
- UINT32 Fix_Me_2:1;\r
- ///\r
- /// [Bit 2] Enable PEBS trigger and recording for the programmed event\r
- /// (precise or otherwise) on IA32_PMC2.\r
- ///\r
- UINT32 Fix_Me_3:1;\r
- ///\r
- /// [Bit 3] Enable PEBS trigger and recording for the programmed event\r
- /// (precise or otherwise) on IA32_PMC3.\r
- ///\r
- UINT32 Fix_Me_4:1;\r
- UINT32 Reserved1:28;\r
- ///\r
- /// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.\r
- ///\r
- UINT32 Fix_Me_5:1;\r
- ///\r
- /// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.\r
- ///\r
- UINT32 Fix_Me_6:1;\r
- ///\r
- /// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.\r
- ///\r
- UINT32 Fix_Me_7:1;\r
- UINT32 Reserved2:29;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up\r
- the first entry of the 32-entry LBR stack. The From_IP part of the stack\r
- contains pointers to the source instruction. See also: - Last Branch Record\r
- Stack TOS at 1C9H. - Section 17.7, "Last Branch, Call Stack, Interrupt, and\r
- .. Exception Recording for Processors based on Goldmont Plus\r
- Microarchitecture.".\r
-\r
- @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);\r
- @endcode\r
-**/\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP 0x0000068F\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP 0x00000690\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP 0x00000691\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP 0x00000692\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP 0x00000693\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP 0x00000694\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP 0x00000695\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP 0x00000696\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP 0x00000697\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP 0x00000698\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP 0x00000699\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP 0x0000069A\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP 0x0000069B\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP 0x0000069C\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP 0x0000069D\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP 0x0000069E\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP 0x0000069F\r
-\r
-/**\r
- Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up\r
- the first entry of the 32-entry LBR stack. The To_IP part of the stack\r
- contains pointers to the Destination instruction. See also: - Section 17.7,\r
- "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors\r
- based on Goldmont Plus Microarchitecture.".\r
-\r
- @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);\r
- @endcode\r
-**/\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP 0x000006CF\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP 0x000006D0\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP 0x000006D1\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP 0x000006D2\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP 0x000006D3\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP 0x000006D4\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP 0x000006D5\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP 0x000006D6\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP 0x000006D7\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP 0x000006D8\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP 0x000006D9\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP 0x000006DA\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP 0x000006DB\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP 0x000006DC\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP 0x000006DD\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP 0x000006DE\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP 0x000006DF\r
-\r
-\r
-/**\r
- Core. Last Branch Record N Additional Information (R/W) One of the three\r
- MSRs that make up the first entry of the 32-entry LBR stack. This part of\r
- the stack contains flag and elapsed cycle information. See also: - Last\r
- Branch Record Stack TOS at 1C9H. - Section 17.9.1, "LBR Stack.".\r
-\r
- @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);\r
- AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);\r
- @endcode\r
-**/\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 0x00000DC0\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1 0x00000DC1\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2 0x00000DC2\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3 0x00000DC3\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4 0x00000DC4\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5 0x00000DC5\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6 0x00000DC6\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7 0x00000DC7\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8 0x00000DC8\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9 0x00000DC9\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10 0x00000DCA\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11 0x00000DCB\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12 0x00000DCC\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13 0x00000DCD\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14 0x00000DCE\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15 0x00000DCF\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16 0x00000DD0\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17 0x00000DD1\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18 0x00000DD2\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19 0x00000DD3\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20 0x00000DD4\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21 0x00000DD5\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22 0x00000DD6\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23 0x00000DD7\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24 0x00000DD8\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25 0x00000DD9\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26 0x00000DDA\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27 0x00000DDB\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28 0x00000DDC\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29 0x00000DDD\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30 0x00000DDE\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31 0x00000DDF\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel processors based on the Haswell-E microarchitecture.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __HASWELL_E_MSR_H__\r
-#define __HASWELL_E_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel processors based on the Haswell-E microarchitecture?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x3F \\r
- ) \\r
- )\r
-\r
-/**\r
- Package. Configured State of Enabled Processor Core Count and Logical\r
- Processor Count (RO) - After a Power-On RESET, enumerates factory\r
- configuration of the number of processor cores and logical processors in the\r
- physical package. - Following the sequence of (i) BIOS modified a\r
- Configuration Mask which selects a subset of processor cores to be active\r
- post RESET and (ii) a RESET event after the modification, enumerates the\r
- current configuration of enabled processor core count and logical processor\r
- count in the physical package.\r
-\r
- @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);\r
- @endcode\r
- @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.\r
-**/\r
-#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are\r
- /// currently enabled (by either factory configuration or BIOS\r
- /// configuration) in the physical package.\r
- ///\r
- UINT32 Core_Count:16;\r
- ///\r
- /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that\r
- /// are currently enabled (by either factory configuration or BIOS\r
- /// configuration) in the physical package.\r
- ///\r
- UINT32 Thread_Count:16;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;\r
-\r
-\r
-/**\r
- Thread. A Hardware Assigned ID for the Logical Processor (RO).\r
-\r
- @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);\r
- @endcode\r
- @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.\r
-**/\r
-#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific\r
- /// numerical. value physically assigned to each logical processor. This\r
- /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within\r
- /// a physical package.\r
- ///\r
- UINT32 Logical_Processor_ID:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
- specific C-state code names, unrelated to MWAIT extension C-state parameters\r
- or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
-\r
- @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
- /// processor-specific C-state code name (consuming the least power) for\r
- /// the package. The default is set as factory-configured package C-state\r
- /// limit. The following C-state code name encodings are supported: 000b:\r
- /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
- /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
- /// supported by the processor are available.\r
- ///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
- ///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO).\r
- ///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
- ///\r
- /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
- ///\r
- UINT32 C3AutoDemotion:1;\r
- ///\r
- /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
- ///\r
- UINT32 C1AutoDemotion:1;\r
- ///\r
- /// [Bit 27] Enable C3 Undemotion (R/W).\r
- ///\r
- UINT32 C3Undemotion:1;\r
- ///\r
- /// [Bit 28] Enable C1 Undemotion (R/W).\r
- ///\r
- UINT32 C1Undemotion:1;\r
- ///\r
- /// [Bit 29] Package C State Demotion Enable (R/W).\r
- ///\r
- UINT32 CStateDemotion:1;\r
- ///\r
- /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
- ///\r
- UINT32 CStateUndemotion:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Global Machine Check Capability (R/O).\r
-\r
- @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);\r
- @endcode\r
- @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
-**/\r
-#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Count.\r
- ///\r
- UINT32 Count:8;\r
- ///\r
- /// [Bit 8] MCG_CTL_P.\r
- ///\r
- UINT32 MCG_CTL_P:1;\r
- ///\r
- /// [Bit 9] MCG_EXT_P.\r
- ///\r
- UINT32 MCG_EXT_P:1;\r
- ///\r
- /// [Bit 10] MCP_CMCI_P.\r
- ///\r
- UINT32 MCP_CMCI_P:1;\r
- ///\r
- /// [Bit 11] MCG_TES_P.\r
- ///\r
- UINT32 MCG_TES_P:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 23:16] MCG_EXT_CNT.\r
- ///\r
- UINT32 MCG_EXT_CNT:8;\r
- ///\r
- /// [Bit 24] MCG_SER_P.\r
- ///\r
- UINT32 MCG_SER_P:1;\r
- ///\r
- /// [Bit 25] MCG_EM_P.\r
- ///\r
- UINT32 MCG_EM_P:1;\r
- ///\r
- /// [Bit 26] MCG_ELOG_P.\r
- ///\r
- UINT32 MCG_ELOG_P:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;\r
-\r
-\r
-/**\r
- THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
- Enhancement. Accessible only while in SMM.\r
-\r
- @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);\r
- AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
-**/\r
-#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
- ///\r
- /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
- /// SMM code access restriction is supported and a host-space interface\r
- /// available to SMM handler.\r
- ///\r
- UINT32 SMM_Code_Access_Chk:1;\r
- ///\r
- /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
- /// SMM long flow indicator is supported and a host-space interface\r
- /// available to SMM handler.\r
- ///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;\r
-\r
-\r
-/**\r
- Package. MC Bank Error Configuration (R/W).\r
-\r
- @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
- /// to log additional info in bits 36:32.\r
- ///\r
- UINT32 MemErrorLogEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_ERROR_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);\r
- @endcode\r
- @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
- /// limit of 1 core active.\r
- ///\r
- UINT32 Maximum1C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
- /// limit of 2 core active.\r
- ///\r
- UINT32 Maximum2C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
- /// limit of 3 core active.\r
- ///\r
- UINT32 Maximum3C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
- /// limit of 4 core active.\r
- ///\r
- UINT32 Maximum4C:8;\r
- ///\r
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
- /// limit of 5 core active.\r
- ///\r
- UINT32 Maximum5C:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
- /// limit of 6 core active.\r
- ///\r
- UINT32 Maximum6C:8;\r
- ///\r
- /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
- /// limit of 7 core active.\r
- ///\r
- UINT32 Maximum7C:8;\r
- ///\r
- /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
- /// limit of 8 core active.\r
- ///\r
- UINT32 Maximum8C:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);\r
- @endcode\r
- @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
- /// limit of 9 core active.\r
- ///\r
- UINT32 Maximum9C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
- /// limit of 10 core active.\r
- ///\r
- UINT32 Maximum10C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
- /// limit of 11 core active.\r
- ///\r
- UINT32 Maximum11C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
- /// limit of 12 core active.\r
- ///\r
- UINT32 Maximum12C:8;\r
- ///\r
- /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
- /// limit of 13 core active.\r
- ///\r
- UINT32 Maximum13C:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
- /// limit of 14 core active.\r
- ///\r
- UINT32 Maximum14C:8;\r
- ///\r
- /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
- /// limit of 15 core active.\r
- ///\r
- UINT32 Maximum15C:8;\r
- ///\r
- /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio\r
- /// limit of 16 core active.\r
- ///\r
- UINT32 Maximum16C:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);\r
- @endcode\r
- @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio\r
- /// limit of 17 core active.\r
- ///\r
- UINT32 Maximum17C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio\r
- /// limit of 18 core active.\r
- ///\r
- UINT32 Maximum18C:8;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:31;\r
- ///\r
- /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
- /// the processor uses override configuration specified in\r
- /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and\r
- /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set\r
- /// configuration (Default).\r
- ///\r
- UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;\r
-\r
-\r
-/**\r
- Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
-\r
- @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);\r
- @endcode\r
- @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
-**/\r
-#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
- ///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 12:8] Package. Energy Status Units Energy related information\r
- /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
- /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
- /// micro-joules).\r
- ///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
- /// Interfaces.".\r
- ///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
- Domain.".\r
-\r
- @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618\r
-\r
-\r
-/**\r
- Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.\r
-\r
- @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
- /// to enable DRAM RAPL mode 0 (Direct VR).\r
- ///\r
- UINT32 Energy:32;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);\r
- @endcode\r
- @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);\r
- AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
-**/\r
-#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r
-\r
-\r
-/**\r
- Package. Configuration of PCIE PLL Relative to BCLK(R/W).\r
-\r
- @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz\r
- /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use\r
- /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz\r
- /// operation.\r
- ///\r
- UINT32 PCIERatio:2;\r
- ///\r
- /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of\r
- /// PCIE Ratio.\r
- ///\r
- UINT32 LPLLSelect:1;\r
- ///\r
- /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out\r
- /// before re-locking Gen2/Gen3 PLLs.\r
- ///\r
- UINT32 LONGRESET:1;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
- fields represent the widest possible range of uncore frequencies. Writing to\r
- these fields allows software to control the minimum and the maximum\r
- frequency that hardware will select.\r
-\r
- @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);\r
- AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
- /// LLC/Ring.\r
- ///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
- /// possible ratio of the LLC/Ring.\r
- ///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
-\r
-/**\r
- Package. Reserved (R/O) Reads return 0.\r
-\r
- @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639\r
-\r
-\r
-/**\r
- Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
- refers to processor core frequency).\r
-\r
- @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
- /// reduced below the operating system request due to assertion of\r
- /// external PROCHOT.\r
- ///\r
- UINT32 PROCHOT_Status:1;\r
- ///\r
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to a thermal event.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- ///\r
- /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to PBM limit.\r
- ///\r
- UINT32 PowerBudgetManagementStatus:1;\r
- ///\r
- /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
- /// frequency is reduced below the operating system request due to PCS\r
- /// limit.\r
- ///\r
- UINT32 PlatformConfigurationServicesStatus:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
- /// When set, frequency is reduced below the operating system request\r
- /// because the processor has detected that utilization is low.\r
- ///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
- ///\r
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to a thermal alert from the\r
- /// Voltage Regulator.\r
- ///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to electrical design\r
- /// point constraints (e.g. maximum electrical current consumption).\r
- ///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to Multi-Core Turbo limits.\r
- ///\r
- UINT32 MultiCoreTurboStatus:1;\r
- UINT32 Reserved4:2;\r
- ///\r
- /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
- /// below max non-turbo P1.\r
- ///\r
- UINT32 FrequencyP1Status:1;\r
- ///\r
- /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
- /// set, frequency is reduced below max n-core turbo frequency.\r
- ///\r
- UINT32 TurboFrequencyLimitingStatus:1;\r
- ///\r
- /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
- /// reduced below the operating system request.\r
- ///\r
- UINT32 FrequencyLimitingStatus:1;\r
- ///\r
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PROCHOT_Log:1;\r
- ///\r
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ThermalLog:1;\r
- ///\r
- /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PowerBudgetManagementLog:1;\r
- ///\r
- /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
- /// the PCS Status bit has asserted since the log bit was last cleared.\r
- /// This log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PlatformConfigurationServicesLog:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
- /// indicates that the AUBFC Status bit has asserted since the log bit was\r
- /// last cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
- ///\r
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
- /// Alert Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ElectricalDesignPointLog:1;\r
- UINT32 Reserved7:1;\r
- ///\r
- /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
- /// Turbo Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 MultiCoreTurboLog:1;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
- /// Frequency P1 Status bit has asserted since the log bit was last\r
- /// cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 CoreFrequencyP1Log:1;\r
- ///\r
- /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
- /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 TurboFrequencyLimitingLog:1;\r
- ///\r
- /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
- /// Frequency Limiting Status bit has asserted since the log bit was last\r
- /// cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 CoreFrequencyLimitingLog:1;\r
- UINT32 Reserved9:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;\r
-\r
-\r
-/**\r
- THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,\r
- ECX=0):EBX.RDT-M[bit 12] = 1.\r
-\r
- @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3\r
- /// occupancy monitoring all other encoding reserved..\r
- ///\r
- UINT32 EventID:8;\r
- UINT32 Reserved1:24;\r
- ///\r
- /// [Bits 41:32] RMID (RW).\r
- ///\r
- UINT32 RMID:10;\r
- UINT32 Reserved2:22;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;\r
-\r
-\r
-/**\r
- THREAD. Resource Association Register (R/W)..\r
-\r
- @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);\r
- AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
-**/\r
-#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] RMID.\r
- ///\r
- UINT32 RMID:10;\r
- UINT32 Reserved1:22;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore perfmon per-socket global control.\r
-\r
- @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700\r
-\r
-\r
-/**\r
- Package. Uncore perfmon per-socket global status.\r
-\r
- @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701\r
-\r
-\r
-/**\r
- Package. Uncore perfmon per-socket global configuration.\r
-\r
- @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702\r
-\r
-\r
-/**\r
- Package. Uncore U-box UCLK fixed counter control.\r
-\r
- @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703\r
-\r
-\r
-/**\r
- Package. Uncore U-box UCLK fixed counter.\r
-\r
- @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);\r
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
-**/\r
-#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon event select for U-box counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon event select for U-box counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon U-box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon for PCU-box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon event select for PCU counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon event select for PCU counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon event select for PCU counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon event select for PCU counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon box-wide filter.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A\r
-\r
-\r
-/**\r
- Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720\r
-\r
-\r
-/**\r
- Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721\r
-\r
-\r
-/**\r
- Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722\r
-\r
-\r
-/**\r
- Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723\r
-\r
-\r
-/**\r
- Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724\r
-\r
-\r
-/**\r
- Package. Uncore SBo 0 perfmon box-wide filter.\r
-\r
- @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725\r
-\r
-\r
-/**\r
- Package. Uncore SBo 0 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726\r
-\r
-\r
-/**\r
- Package. Uncore SBo 0 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727\r
-\r
-\r
-/**\r
- Package. Uncore SBo 0 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728\r
-\r
-\r
-/**\r
- Package. Uncore SBo 0 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729\r
-\r
-\r
-/**\r
- Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A\r
-\r
-\r
-/**\r
- Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B\r
-\r
-\r
-/**\r
- Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C\r
-\r
-\r
-/**\r
- Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D\r
-\r
-\r
-/**\r
- Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E\r
-\r
-\r
-/**\r
- Package. Uncore SBo 1 perfmon box-wide filter.\r
-\r
- @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F\r
-\r
-\r
-/**\r
- Package. Uncore SBo 1 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730\r
-\r
-\r
-/**\r
- Package. Uncore SBo 1 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731\r
-\r
-\r
-/**\r
- Package. Uncore SBo 1 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732\r
-\r
-\r
-/**\r
- Package. Uncore SBo 1 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733\r
-\r
-\r
-/**\r
- Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734\r
-\r
-\r
-/**\r
- Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735\r
-\r
-\r
-/**\r
- Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736\r
-\r
-\r
-/**\r
- Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737\r
-\r
-\r
-/**\r
- Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738\r
-\r
-\r
-/**\r
- Package. Uncore SBo 2 perfmon box-wide filter.\r
-\r
- @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739\r
-\r
-\r
-/**\r
- Package. Uncore SBo 2 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A\r
-\r
-\r
-/**\r
- Package. Uncore SBo 2 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B\r
-\r
-\r
-/**\r
- Package. Uncore SBo 2 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C\r
-\r
-\r
-/**\r
- Package. Uncore SBo 2 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D\r
-\r
-\r
-/**\r
- Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E\r
-\r
-\r
-/**\r
- Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F\r
-\r
-\r
-/**\r
- Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740\r
-\r
-\r
-/**\r
- Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741\r
-\r
-\r
-/**\r
- Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742\r
-\r
-\r
-/**\r
- Package. Uncore SBo 3 perfmon box-wide filter.\r
-\r
- @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743\r
-\r
-\r
-/**\r
- Package. Uncore SBo 3 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744\r
-\r
-\r
-/**\r
- Package. Uncore SBo 3 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745\r
-\r
-\r
-/**\r
- Package. Uncore SBo 3 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746\r
-\r
-\r
-/**\r
- Package. Uncore SBo 3 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon for box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon box wide filter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon box wide filter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon for box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon box wide filter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon for box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon box wide filter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon for box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon box wide filter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon for box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon box wide filter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon for box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon box wide filter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon for box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon box wide filter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon for box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon box wide filter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon local box wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon box wide filter0.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon local box wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon box wide filter0.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon local box wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon box wide filter0.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon local box wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon box wide filter0.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon local box wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon box wide filter0.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon local box wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon box wide filter0.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon local box wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon box wide filter0.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon local box wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon box wide filter0.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 15 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon for box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon box wide filter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon box wide filter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 16 perfmon counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 17 perfmon for box-wide control.\r
-\r
- @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10\r
-\r
-\r
-/**\r
- Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11\r
-\r
-\r
-/**\r
- Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.\r
-\r
- @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12\r
-\r
-\r
-/**\r
- Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.\r
-\r
- @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13\r
-\r
-\r
-/**\r
- Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.\r
-\r
- @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14\r
-\r
-\r
-/**\r
- Package. Uncore C-box 17 perfmon box wide filter 0.\r
-\r
- @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15\r
-\r
-\r
-/**\r
- Package. Uncore C-box 17 perfmon box wide filter1.\r
-\r
- @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16\r
-\r
-/**\r
- Package. Uncore C-box 17 perfmon box wide status.\r
-\r
- @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17\r
-\r
-\r
-/**\r
- Package. Uncore C-box 17 perfmon counter n.\r
-\r
- @param ECX MSR_HASWELL_E_C17_PMON_CTRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.\r
- MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.\r
- MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.\r
- MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.\r
- @{\r
-**/\r
-#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18\r
-#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19\r
-#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A\r
-#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B\r
-/// @}\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel processors based on the Haswell microarchitecture.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __HASWELL_MSR_H__\r
-#define __HASWELL_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel processors based on the Haswell microarchitecture?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x3C || \\r
- DisplayModel == 0x45 || \\r
- DisplayModel == 0x46 \\r
- ) \\r
- )\r
-\r
-/**\r
- Package.\r
-\r
- @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_PLATFORM_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);\r
- AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
-**/\r
-#define MSR_HASWELL_PLATFORM_INFO 0x000000CE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
- /// MHz.\r
- ///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
- ///\r
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
- /// Turbo mode is disabled.\r
- ///\r
- UINT32 RatioLimit:1;\r
- ///\r
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
- /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
- /// programmable.\r
- ///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r
- /// indicates that LPM is supported, and when set to 0, indicates LPM is\r
- /// not supported.\r
- ///\r
- UINT32 LowPowerModeSupport:1;\r
- ///\r
- /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
- /// TDP level available. 01: One additional TDP level available. 02: Two\r
- /// additional TDP level available. 11: Reserved.\r
- ///\r
- UINT32 ConfigTDPLevels:2;\r
- UINT32 Reserved4:5;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
- /// minimum ratio (maximum efficiency) that the processor can operates, in\r
- /// units of 100MHz.\r
- ///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- ///\r
- /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
- /// minimum supported operating ratio in units of 100 MHz.\r
- ///\r
- UINT32 MinimumOperatingRatio:8;\r
- UINT32 Reserved5:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_PLATFORM_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Performance Event Select for Counter n (R/W) Supports all fields\r
- described inTable 2-2 and the fields below.\r
-\r
- @param ECX MSR_HASWELL_IA32_PERFEVTSELn\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r
- MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r
- MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
- @{\r
-**/\r
-#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186\r
-#define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187\r
-#define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,\r
- #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
- ///\r
- UINT32 EventSelect:8;\r
- ///\r
- /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
- /// detect on the selected event logic.\r
- ///\r
- UINT32 UMASK:8;\r
- ///\r
- /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
- ///\r
- UINT32 USR:1;\r
- ///\r
- /// [Bit 17] OS: Counts while in privilege level is ring 0.\r
- ///\r
- UINT32 OS:1;\r
- ///\r
- /// [Bit 18] Edge: Enables edge detection if set.\r
- ///\r
- UINT32 E:1;\r
- ///\r
- /// [Bit 19] PC: enables pin control.\r
- ///\r
- UINT32 PC:1;\r
- ///\r
- /// [Bit 20] INT: enables interrupt on counter overflow.\r
- ///\r
- UINT32 INT:1;\r
- ///\r
- /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
- /// event conditions occurring across all logical processors sharing a\r
- /// processor core. When set to 0, the counter only increments the\r
- /// associated event conditions occurring in the logical processor which\r
- /// programmed the MSR.\r
- ///\r
- UINT32 ANY:1;\r
- ///\r
- /// [Bit 22] EN: enables the corresponding performance counter to commence\r
- /// counting when this bit is set.\r
- ///\r
- UINT32 EN:1;\r
- ///\r
- /// [Bit 23] INV: invert the CMASK.\r
- ///\r
- UINT32 INV:1;\r
- ///\r
- /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
- /// performance counter increments each cycle if the event count is\r
- /// greater than or equal to the CMASK.\r
- ///\r
- UINT32 CMASK:8;\r
- UINT32 Reserved:32;\r
- ///\r
- /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r
- /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
- ///\r
- UINT32 IN_TX:1;\r
- UINT32 Reserved2:31;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Performance Event Select for Counter 2 (R/W) Supports all fields\r
- described inTable 2-2 and the fields below.\r
-\r
- @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);\r
- AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
- ///\r
- UINT32 EventSelect:8;\r
- ///\r
- /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
- /// detect on the selected event logic.\r
- ///\r
- UINT32 UMASK:8;\r
- ///\r
- /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
- ///\r
- UINT32 USR:1;\r
- ///\r
- /// [Bit 17] OS: Counts while in privilege level is ring 0.\r
- ///\r
- UINT32 OS:1;\r
- ///\r
- /// [Bit 18] Edge: Enables edge detection if set.\r
- ///\r
- UINT32 E:1;\r
- ///\r
- /// [Bit 19] PC: enables pin control.\r
- ///\r
- UINT32 PC:1;\r
- ///\r
- /// [Bit 20] INT: enables interrupt on counter overflow.\r
- ///\r
- UINT32 INT:1;\r
- ///\r
- /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
- /// event conditions occurring across all logical processors sharing a\r
- /// processor core. When set to 0, the counter only increments the\r
- /// associated event conditions occurring in the logical processor which\r
- /// programmed the MSR.\r
- ///\r
- UINT32 ANY:1;\r
- ///\r
- /// [Bit 22] EN: enables the corresponding performance counter to commence\r
- /// counting when this bit is set.\r
- ///\r
- UINT32 EN:1;\r
- ///\r
- /// [Bit 23] INV: invert the CMASK.\r
- ///\r
- UINT32 INV:1;\r
- ///\r
- /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
- /// performance counter increments each cycle if the event count is\r
- /// greater than or equal to the CMASK.\r
- ///\r
- UINT32 CMASK:8;\r
- UINT32 Reserved:32;\r
- ///\r
- /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r
- /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
- ///\r
- UINT32 IN_TX:1;\r
- ///\r
- /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and\r
- /// in sampling, spurious PMI may occur and transactions may continuously\r
- /// abort near overflow conditions. Software should favor using IN_TXCP\r
- /// for counting over sampling. If sampling, software should use large\r
- /// "sample-after" value after clearing the counter configured to use\r
- /// IN_TXCP and also always reset the counter even when no overflow\r
- /// condition was reported.\r
- ///\r
- UINT32 IN_TXCP:1;\r
- UINT32 Reserved2:30;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Last Branch Record Filtering Select Register (R/W).\r
-\r
- @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_LBR_SELECT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);\r
- AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
-**/\r
-#define MSR_HASWELL_LBR_SELECT 0x000001C8\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] CPL_EQ_0.\r
- ///\r
- UINT32 CPL_EQ_0:1;\r
- ///\r
- /// [Bit 1] CPL_NEQ_0.\r
- ///\r
- UINT32 CPL_NEQ_0:1;\r
- ///\r
- /// [Bit 2] JCC.\r
- ///\r
- UINT32 JCC:1;\r
- ///\r
- /// [Bit 3] NEAR_REL_CALL.\r
- ///\r
- UINT32 NEAR_REL_CALL:1;\r
- ///\r
- /// [Bit 4] NEAR_IND_CALL.\r
- ///\r
- UINT32 NEAR_IND_CALL:1;\r
- ///\r
- /// [Bit 5] NEAR_RET.\r
- ///\r
- UINT32 NEAR_RET:1;\r
- ///\r
- /// [Bit 6] NEAR_IND_JMP.\r
- ///\r
- UINT32 NEAR_IND_JMP:1;\r
- ///\r
- /// [Bit 7] NEAR_REL_JMP.\r
- ///\r
- UINT32 NEAR_REL_JMP:1;\r
- ///\r
- /// [Bit 8] FAR_BRANCH.\r
- ///\r
- UINT32 FAR_BRANCH:1;\r
- ///\r
- /// [Bit 9] EN_CALL_STACK.\r
- ///\r
- UINT32 EN_CALL_STACK:1;\r
- UINT32 Reserved1:22;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_LBR_SELECT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines\r
- the interrupt response time limit used by the processor to manage transition\r
- to package C6 or C7 state. The latency programmed in this register is for\r
- the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.\r
- Note: C-state values are processor specific C-state code names, unrelated to\r
- MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_PKGC_IRTL1_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);\r
- AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_PKGC_IRTL1 0x0000060B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
- /// that should be used to decide if the package should be put into a\r
- /// package C6 or C7 state.\r
- ///\r
- UINT32 InterruptResponseTimeLimit:10;\r
- ///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
- /// of the interrupt response time limit. See Table 2-19 for supported\r
- /// time unit encodings.\r
- ///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
- /// valid and can be used by the processor for package C-sate management.\r
- ///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_PKGC_IRTL1_REGISTER;\r
-\r
-\r
-/**\r
- Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines\r
- the interrupt response time limit used by the processor to manage transition\r
- to package C6 or C7 state. The latency programmed in this register is for\r
- the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.\r
- Note: C-state values are processor specific C-state code names, unrelated to\r
- MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_PKGC_IRTL2_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);\r
- AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_PKGC_IRTL2 0x0000060C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
- /// that should be used to decide if the package should be put into a\r
- /// package C6 or C7 state.\r
- ///\r
- UINT32 InterruptResponseTimeLimit:10;\r
- ///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
- /// of the interrupt response time limit. See Table 2-19 for supported\r
- /// time unit encodings.\r
- ///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
- /// valid and can be used by the processor for package C-sate management.\r
- ///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_PKGC_IRTL2_REGISTER;\r
-\r
-\r
-/**\r
- Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
-\r
- @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);\r
- @endcode\r
- @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613\r
-\r
-\r
-/**\r
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619\r
-\r
-\r
-/**\r
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);\r
- @endcode\r
- @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B\r
-\r
-\r
-/**\r
- Package. Base TDP Ratio (R/O).\r
-\r
- @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);\r
- @endcode\r
- @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
-**/\r
-#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
- /// specific processor (in units of 100 MHz).\r
- ///\r
- UINT32 Config_TDP_Base:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;\r
-\r
-\r
-/**\r
- Package. ConfigTDP Level 1 ratio and power level (R/O).\r
-\r
- @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);\r
- @endcode\r
- @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
- ///\r
- UINT32 PKG_TDP_LVL1:15;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
- /// for this specific processor.\r
- ///\r
- UINT32 Config_TDP_LVL1_Ratio:8;\r
- UINT32 Reserved2:8;\r
- ///\r
- /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
- /// Level 1.\r
- ///\r
- UINT32 PKG_MAX_PWR_LVL1:15;\r
- ///\r
- /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
- /// Level 1.\r
- ///\r
- UINT32 PKG_MIN_PWR_LVL1:16;\r
- UINT32 Reserved3:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;\r
-\r
-\r
-/**\r
- Package. ConfigTDP Level 2 ratio and power level (R/O).\r
-\r
- @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);\r
- @endcode\r
- @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
-**/\r
-#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
- ///\r
- UINT32 PKG_TDP_LVL2:15;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
- /// for this specific processor.\r
- ///\r
- UINT32 Config_TDP_LVL2_Ratio:8;\r
- UINT32 Reserved2:8;\r
- ///\r
- /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
- /// Level 2.\r
- ///\r
- UINT32 PKG_MAX_PWR_LVL2:15;\r
- ///\r
- /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
- /// Level 2.\r
- ///\r
- UINT32 PKG_MIN_PWR_LVL2:16;\r
- UINT32 Reserved3:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;\r
-\r
-\r
-/**\r
- Package. ConfigTDP Control (R/W).\r
-\r
- @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);\r
- AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
-**/\r
-#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
- ///\r
- UINT32 TDP_LEVEL:2;\r
- UINT32 Reserved1:29;\r
- ///\r
- /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
- /// this register is locked until a reset.\r
- ///\r
- UINT32 Config_TDP_Lock:1;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package. ConfigTDP Control (R/W).\r
-\r
- @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);\r
- AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
-**/\r
-#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
- /// field.\r
- ///\r
- UINT32 MAX_NON_TURBO_RATIO:8;\r
- UINT32 Reserved1:23;\r
- ///\r
- /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
- /// content of this register is locked until a reset.\r
- ///\r
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;\r
-\r
-\r
-/**\r
- Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
- specific C-state code names, unrelated to MWAIT extension C-state parameters\r
- or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.\r
-\r
- @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
-**/\r
-#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
- /// processor-specific C-state code name (consuming the least power) for\r
- /// the package. The default is set as factory-configured package C-state\r
- /// limit. The following C-state code name encodings are supported: 0000b:\r
- /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
- /// 0100b: C7 0101b: C7s Package C states C7 are not available to\r
- /// processor with signature 06_3CH.\r
- ///\r
- UINT32 Limit:4;\r
- UINT32 Reserved1:6;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
- ///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO).\r
- ///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
- ///\r
- /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
- ///\r
- UINT32 C3AutoDemotion:1;\r
- ///\r
- /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
- ///\r
- UINT32 C1AutoDemotion:1;\r
- ///\r
- /// [Bit 27] Enable C3 Undemotion (R/W).\r
- ///\r
- UINT32 C3Undemotion:1;\r
- ///\r
- /// [Bit 28] Enable C1 Undemotion (R/W).\r
- ///\r
- UINT32 C1Undemotion:1;\r
- UINT32 Reserved4:3;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
- Enhancement. Accessible only while in SMM.\r
-\r
- @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);\r
- AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
-**/\r
-#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
- ///\r
- /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
- /// SMM code access restriction is supported and the\r
- /// MSR_SMM_FEATURE_CONTROL is supported.\r
- ///\r
- UINT32 SMM_Code_Access_Chk:1;\r
- ///\r
- /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
- /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r
- /// supported.\r
- ///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_SMM_MCA_CAP_REGISTER;\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);\r
- @endcode\r
- @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
- /// limit of 1 core active.\r
- ///\r
- UINT32 Maximum1C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
- /// limit of 2 core active.\r
- ///\r
- UINT32 Maximum2C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
- /// limit of 3 core active.\r
- ///\r
- UINT32 Maximum3C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
- /// limit of 4 core active.\r
- ///\r
- UINT32 Maximum4C:8;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore PMU global control.\r
-\r
- @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Core 0 select.\r
- ///\r
- UINT32 PMI_Sel_Core0:1;\r
- ///\r
- /// [Bit 1] Core 1 select.\r
- ///\r
- UINT32 PMI_Sel_Core1:1;\r
- ///\r
- /// [Bit 2] Core 2 select.\r
- ///\r
- UINT32 PMI_Sel_Core2:1;\r
- ///\r
- /// [Bit 3] Core 3 select.\r
- ///\r
- UINT32 PMI_Sel_Core3:1;\r
- UINT32 Reserved1:15;\r
- UINT32 Reserved2:10;\r
- ///\r
- /// [Bit 29] Enable all uncore counters.\r
- ///\r
- UINT32 EN:1;\r
- ///\r
- /// [Bit 30] Enable wake on PMI.\r
- ///\r
- UINT32 WakePMI:1;\r
- ///\r
- /// [Bit 31] Enable Freezing counter when overflow.\r
- ///\r
- UINT32 FREEZE:1;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore PMU main status.\r
-\r
- @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Fixed counter overflowed.\r
- ///\r
- UINT32 Fixed:1;\r
- ///\r
- /// [Bit 1] An ARB counter overflowed.\r
- ///\r
- UINT32 ARB:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 3] A CBox counter overflowed (on any slice).\r
- ///\r
- UINT32 CBox:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore fixed counter control (R/W).\r
-\r
- @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:20;\r
- ///\r
- /// [Bit 20] Enable overflow propagation.\r
- ///\r
- UINT32 EnableOverflow:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 22] Enable counting.\r
- ///\r
- UINT32 EnableCounting:1;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore fixed counter.\r
-\r
- @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Current count.\r
- ///\r
- UINT32 CurrentCount:32;\r
- ///\r
- /// [Bits 47:32] Current count.\r
- ///\r
- UINT32 CurrentCountHi:16;\r
- UINT32 Reserved:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore C-Box configuration information (R/O).\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".\r
- ///\r
- UINT32 CBox:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, performance counter 0.\r
-\r
- @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, performance counter 1.\r
-\r
- @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, counter 0 event select MSR.\r
-\r
- @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, counter 1 event select MSR.\r
-\r
- @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3\r
-\r
-\r
-/**\r
- Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r
- Enhancement. Accessible only while in SMM.\r
-\r
- @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r
- /// further changes.\r
- ///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r
- /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r
- /// logical processors are prevented from executing SMM code outside the\r
- /// ranges defined by the SMRR. When set to '1' any logical processor in\r
- /// the package that attempts to execute SMM code not within the ranges\r
- /// defined by the SMRR will assert an unrecoverable MCE.\r
- ///\r
- UINT32 SMM_Code_Chk_En:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r
- processors in the package. Available only while in SMM and\r
- MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.\r
-\r
- [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
- processor of its state in a long flow of internal operation which\r
- delays servicing an interrupt. The corresponding bit will be set at\r
- the start of long events such as: Microcode Update Load, C6, WBINVD,\r
- Ratio Change, Throttle. The bit is automatically cleared at the end of\r
- each long event. The reset value of this field is 0. Only bit\r
- positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be\r
- updated.\r
-\r
- [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
- processor of its state in a long flow of internal operation which\r
- delays servicing an interrupt. The corresponding bit will be set at\r
- the start of long events such as: Microcode Update Load, C6, WBINVD,\r
- Ratio Change, Throttle. The bit is automatically cleared at the end of\r
- each long event. The reset value of this field is 0. Only bit\r
- positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be\r
- updated.\r
-\r
- @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);\r
- @endcode\r
- @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r
-**/\r
-#define MSR_HASWELL_SMM_DELAYED 0x000004E2\r
-\r
-\r
-/**\r
- Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r
- processors in the package. Available only while in SMM.\r
-\r
- [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
- processor of its blocked state to service an SMI. The corresponding\r
- bit will be set if the logical processor is in one of the following\r
- states: Wait For SIPI or SENTER Sleep. The reset value of this field\r
- is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,\r
- ECX=PKG_LVL):EBX[15:0] can be updated.\r
-\r
-\r
- [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
- processor of its blocked state to service an SMI. The corresponding\r
- bit will be set if the logical processor is in one of the following\r
- states: Wait For SIPI or SENTER Sleep. The reset value of this field\r
- is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,\r
- ECX=PKG_LVL):EBX[15:0] can be updated.\r
-\r
- @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);\r
- @endcode\r
- @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r
-**/\r
-#define MSR_HASWELL_SMM_BLOCKED 0x000004E3\r
-\r
-\r
-/**\r
- Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
-\r
- @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);\r
- @endcode\r
- @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
-**/\r
-#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
- ///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 12:8] Package. Energy Status Units Energy related information\r
- /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
- /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
- /// micro-joules).\r
- ///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
- /// Interfaces.".\r
- ///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639\r
-\r
-\r
-/**\r
- Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
- RAPL Domains.".\r
-\r
- @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640\r
-\r
-\r
-/**\r
- Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641\r
-\r
-\r
-/**\r
- Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_HASWELL_PP1_POLICY (0x00000642)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);\r
- AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);\r
- @endcode\r
- @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r
-**/\r
-#define MSR_HASWELL_PP1_POLICY 0x00000642\r
-\r
-\r
-/**\r
- Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
- refers to processor core frequency).\r
-\r
- @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);\r
- AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
-**/\r
-#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
- /// reduced below the operating system request due to assertion of\r
- /// external PROCHOT.\r
- ///\r
- UINT32 PROCHOT_Status:1;\r
- ///\r
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to a thermal event.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to Processor Graphics driver\r
- /// override.\r
- ///\r
- UINT32 GraphicsDriverStatus:1;\r
- ///\r
- /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
- /// When set, frequency is reduced below the operating system request\r
- /// because the processor has detected that utilization is low.\r
- ///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
- ///\r
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to a thermal alert from the\r
- /// Voltage Regulator.\r
- ///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to electrical design\r
- /// point constraints (e.g. maximum electrical current consumption).\r
- ///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- ///\r
- /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to domain-level power limiting.\r
- ///\r
- UINT32 PLStatus:1;\r
- ///\r
- /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
- /// frequency is reduced below the operating system request due to\r
- /// package-level power limiting PL1.\r
- ///\r
- UINT32 PL1Status:1;\r
- ///\r
- /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
- /// frequency is reduced below the operating system request due to\r
- /// package-level power limiting PL2.\r
- ///\r
- UINT32 PL2Status:1;\r
- ///\r
- /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to multi-core turbo limits.\r
- ///\r
- UINT32 MaxTurboLimitStatus:1;\r
- ///\r
- /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
- /// is reduced below the operating system request due to Turbo transition\r
- /// attenuation. This prevents performance degradation due to frequent\r
- /// operating ratio changes.\r
- ///\r
- UINT32 TurboTransitionAttenuationStatus:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PROCHOT_Log:1;\r
- ///\r
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:2;\r
- ///\r
- /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
- /// Driver Status bit has asserted since the log bit was last cleared.\r
- /// This log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 GraphicsDriverLog:1;\r
- ///\r
- /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
- /// indicates that the Autonomous Utilization-Based Frequency Control\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
- ///\r
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
- /// Alert Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ElectricalDesignPointLog:1;\r
- ///\r
- /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
- /// Power Limiting Status bit has asserted since the log bit was last\r
- /// cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 PLLog:1;\r
- ///\r
- /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
- /// that the Package Level PL1 Power Limiting Status bit has asserted\r
- /// since the log bit was last cleared. This log bit will remain set until\r
- /// cleared by software writing 0.\r
- ///\r
- UINT32 PL1Log:1;\r
- ///\r
- /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
- /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
- /// log bit was last cleared. This log bit will remain set until cleared\r
- /// by software writing 0.\r
- ///\r
- UINT32 PL2Log:1;\r
- ///\r
- /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
- /// Limit Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 MaxTurboLimitLog:1;\r
- ///\r
- /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
- /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
- /// was last cleared. This log bit will remain set until cleared by\r
- /// software writing 0.\r
- ///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved6:2;\r
- UINT32 Reserved7:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;\r
-\r
-\r
-/**\r
- Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
- (frequency refers to processor graphics frequency).\r
-\r
- @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);\r
- AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r
-**/\r
-#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to assertion of external PROCHOT.\r
- ///\r
- UINT32 PROCHOT_Status:1;\r
- ///\r
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to a thermal event.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to Processor Graphics driver\r
- /// override.\r
- ///\r
- UINT32 GraphicsDriverStatus:1;\r
- ///\r
- /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
- /// When set, frequency is reduced below the operating system request\r
- /// because the processor has detected that utilization is low.\r
- ///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
- ///\r
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to a thermal alert from the\r
- /// Voltage Regulator.\r
- ///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to electrical design\r
- /// point constraints (e.g. maximum electrical current consumption).\r
- ///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- ///\r
- /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to domain-level power\r
- /// limiting.\r
- ///\r
- UINT32 GraphicsPowerLimitingStatus:1;\r
- ///\r
- /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
- /// frequency is reduced below the operating system request due to\r
- /// package-level power limiting PL1.\r
- ///\r
- UINT32 PL1STatus:1;\r
- ///\r
- /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
- /// frequency is reduced below the operating system request due to\r
- /// package-level power limiting PL2.\r
- ///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved3:4;\r
- ///\r
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PROCHOT_Log:1;\r
- ///\r
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:2;\r
- ///\r
- /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
- /// Driver Status bit has asserted since the log bit was last cleared.\r
- /// This log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 GraphicsDriverLog:1;\r
- ///\r
- /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
- /// indicates that the Autonomous Utilization-Based Frequency Control\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
- ///\r
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
- /// Alert Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ElectricalDesignPointLog:1;\r
- ///\r
- /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
- /// Power Limiting Status bit has asserted since the log bit was last\r
- /// cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 CorePowerLimitingLog:1;\r
- ///\r
- /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
- /// that the Package Level PL1 Power Limiting Status bit has asserted\r
- /// since the log bit was last cleared. This log bit will remain set until\r
- /// cleared by software writing 0.\r
- ///\r
- UINT32 PL1Log:1;\r
- ///\r
- /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
- /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
- /// log bit was last cleared. This log bit will remain set until cleared\r
- /// by software writing 0.\r
- ///\r
- UINT32 PL2Log:1;\r
- ///\r
- /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
- /// Limit Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 MaxTurboLimitLog:1;\r
- ///\r
- /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
- /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
- /// was last cleared. This log bit will remain set until cleared by\r
- /// software writing 0.\r
- ///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved6:2;\r
- UINT32 Reserved7:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
-\r
-\r
-/**\r
- Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
- (frequency refers to ring interconnect in the uncore).\r
-\r
- @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);\r
- AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
-**/\r
-#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to assertion of external PROCHOT.\r
- ///\r
- UINT32 PROCHOT_Status:1;\r
- ///\r
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to a thermal event.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to a thermal alert from the\r
- /// Voltage Regulator.\r
- ///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to electrical design\r
- /// point constraints (e.g. maximum electrical current consumption).\r
- ///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
- /// frequency is reduced below the operating system request due to\r
- /// package-level power limiting PL1.\r
- ///\r
- UINT32 PL1STatus:1;\r
- ///\r
- /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
- /// frequency is reduced below the operating system request due to\r
- /// package-level power limiting PL2.\r
- ///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved4:4;\r
- ///\r
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PROCHOT_Log:1;\r
- ///\r
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved5:2;\r
- ///\r
- /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
- /// Driver Status bit has asserted since the log bit was last cleared.\r
- /// This log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 GraphicsDriverLog:1;\r
- ///\r
- /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
- /// indicates that the Autonomous Utilization-Based Frequency Control\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
- ///\r
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
- /// Alert Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ElectricalDesignPointLog:1;\r
- ///\r
- /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
- /// Power Limiting Status bit has asserted since the log bit was last\r
- /// cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 CorePowerLimitingLog:1;\r
- ///\r
- /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
- /// that the Package Level PL1 Power Limiting Status bit has asserted\r
- /// since the log bit was last cleared. This log bit will remain set until\r
- /// cleared by software writing 0.\r
- ///\r
- UINT32 PL1Log:1;\r
- ///\r
- /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
- /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
- /// log bit was last cleared. This log bit will remain set until cleared\r
- /// by software writing 0.\r
- ///\r
- UINT32 PL2Log:1;\r
- ///\r
- /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
- /// Limit Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 MaxTurboLimitLog:1;\r
- ///\r
- /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
- /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
- /// was last cleared. This log bit will remain set until cleared by\r
- /// software writing 0.\r
- ///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved7:2;\r
- UINT32 Reserved8:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, counter 0 event select MSR.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, counter 1 event select MSR.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, performance counter 0.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, performance counter 1.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, counter 0 event select MSR.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, counter 1 event select MSR.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, performance counter 0.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, performance counter 1.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, counter 0 event select MSR.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, counter 1 event select MSR.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, performance counter 0.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, performance counter 1.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 3, counter 0 event select MSR.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 3, counter 1 event select MSR.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 3, performance counter 0.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 3, performance counter 1.\r
-\r
- @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);\r
- AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);\r
- AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.\r
-**/\r
-#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset\r
- /// that this package is in processor-specific C8 states. Count at the\r
- /// same frequency as the TSC.\r
- ///\r
- UINT32 C8ResidencyCounter:32;\r
- ///\r
- /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C8 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C8ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);\r
- AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.\r
-**/\r
-#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset\r
- /// that this package is in processor-specific C9 states. Count at the\r
- /// same frequency as the TSC.\r
- ///\r
- UINT32 C9ResidencyCounter:32;\r
- ///\r
- /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C9 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C9ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
-\r
- @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);\r
- AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);\r
- @endcode\r
- @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
-**/\r
-#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C10 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C10ResidencyCounter:32;\r
- ///\r
- /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r
- /// reset that this package is in processor-specific C10 states. Count at\r
- /// the same frequency as the TSC.\r
- ///\r
- UINT32 C10ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __IVY_BRIDGE_MSR_H__\r
-#define __IVY_BRIDGE_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel processors based on the Ivy Bridge microarchitecture?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x3A || \\r
- DisplayModel == 0x3E \\r
- ) \\r
- )\r
-\r
-/**\r
- Package. See http://biosbits.org.\r
-\r
- @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
- /// MHz.\r
- ///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
- ///\r
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
- /// Turbo mode is disabled.\r
- ///\r
- UINT32 RatioLimit:1;\r
- ///\r
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
- /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
- /// programmable.\r
- ///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r
- /// indicates that LPM is supported, and when set to 0, indicates LPM is\r
- /// not supported.\r
- ///\r
- UINT32 LowPowerModeSupport:1;\r
- ///\r
- /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
- /// TDP level available. 01: One additional TDP level available. 02: Two\r
- /// additional TDP level available. 11: Reserved.\r
- ///\r
- UINT32 ConfigTDPLevels:2;\r
- UINT32 Reserved4:5;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
- /// minimum ratio (maximum efficiency) that the processor can operates, in\r
- /// units of 100MHz.\r
- ///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- ///\r
- /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
- /// minimum supported operating ratio in units of 100 MHz.\r
- ///\r
- UINT32 MinimumOperatingRatio:8;\r
- UINT32 Reserved5:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Core. C-State Configuration Control (R/W) Note: C-state values are\r
- processor specific C-state code names, unrelated to MWAIT extension C-state\r
- parameters or ACPI C-States. See http://biosbits.org.\r
-\r
- @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
- /// processor-specific C-state code name (consuming the least power). for\r
- /// the package. The default is set as factory-configured package C-state\r
- /// limit. The following C-state code name encodings are supported: 000b:\r
- /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r
- /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
- /// This field cannot be used to limit package C-state to C3.\r
- ///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
- /// IO_read instructions sent to IO register specified by\r
- /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
- ///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
- /// until next reset.\r
- ///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
- ///\r
- /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
- /// will conditionally demote C6/C7 requests to C3 based on uncore\r
- /// auto-demote information.\r
- ///\r
- UINT32 C3AutoDemotion:1;\r
- ///\r
- /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
- /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
- /// auto-demote information.\r
- ///\r
- UINT32 C1AutoDemotion:1;\r
- ///\r
- /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
- /// demoted C3.\r
- ///\r
- UINT32 C3Undemotion:1;\r
- ///\r
- /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
- /// demoted C1.\r
- ///\r
- UINT32 C1Undemotion:1;\r
- UINT32 Reserved4:3;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
-\r
-\r
-/**\r
- Package. Base TDP Ratio (R/O).\r
-\r
- @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
- /// specific processor (in units of 100 MHz).\r
- ///\r
- UINT32 Config_TDP_Base:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;\r
-\r
-\r
-/**\r
- Package. ConfigTDP Level 1 ratio and power level (R/O).\r
-\r
- @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
- ///\r
- UINT32 PKG_TDP_LVL1:15;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
- /// for this specific processor.\r
- ///\r
- UINT32 Config_TDP_LVL1_Ratio:8;\r
- UINT32 Reserved2:8;\r
- ///\r
- /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
- /// Level 1.\r
- ///\r
- UINT32 PKG_MAX_PWR_LVL1:15;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
- /// Level 1.\r
- ///\r
- UINT32 PKG_MIN_PWR_LVL1:15;\r
- UINT32 Reserved4:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;\r
-\r
-\r
-/**\r
- Package. ConfigTDP Level 2 ratio and power level (R/O).\r
-\r
- @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
- ///\r
- UINT32 PKG_TDP_LVL2:15;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
- /// for this specific processor.\r
- ///\r
- UINT32 Config_TDP_LVL2_Ratio:8;\r
- UINT32 Reserved2:8;\r
- ///\r
- /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
- /// Level 2.\r
- ///\r
- UINT32 PKG_MAX_PWR_LVL2:15;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
- /// Level 2.\r
- ///\r
- UINT32 PKG_MIN_PWR_LVL2:15;\r
- UINT32 Reserved4:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;\r
-\r
-\r
-/**\r
- Package. ConfigTDP Control (R/W).\r
-\r
- @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
- ///\r
- UINT32 TDP_LEVEL:2;\r
- UINT32 Reserved1:29;\r
- ///\r
- /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
- /// this register is locked until a reset.\r
- ///\r
- UINT32 Config_TDP_Lock:1;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package. ConfigTDP Control (R/W).\r
-\r
- @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
- /// field.\r
- ///\r
- UINT32 MAX_NON_TURBO_RATIO:8;\r
- UINT32 Reserved1:23;\r
- ///\r
- /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
- /// content of this register is locked until a reset.\r
- ///\r
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;\r
-\r
-\r
-/**\r
- Package. Protected Processor Inventory Number Enable Control (R/W).\r
-\r
- @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.\r
- /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit\r
- /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to\r
- /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged\r
- /// inventory initialization agent to access MSR_PPIN. After reading\r
- /// MSR_PPIN, the privileged inventory initialization agent should write\r
- /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
- /// prevent unauthorized modification to MSR_PPIN_CTL.\r
- ///\r
- UINT32 LockOut:1;\r
- ///\r
- /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
- /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will\r
- /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default\r
- /// is 0.\r
- ///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Protected Processor Inventory Number (R/O). Protected Processor\r
- Inventory Number (R/O) A unique value within a given CPUID\r
- family/model/stepping signature that a privileged inventory initialization\r
- agent can access to identify each physical processor, when access to\r
- MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r
- MSR_PPIN_CTL[bits 1:0] = '10b'.\r
-\r
- @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PPIN 0x0000004F\r
-\r
-\r
-/**\r
- Package. See http://biosbits.org.\r
-\r
- @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
- /// MHz.\r
- ///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:7;\r
- ///\r
- /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that\r
- /// Protected Processor Inventory Number (PPIN) capability can be enabled\r
- /// for privileged system inventory agent to read PPIN from MSR_PPIN. When\r
- /// set to 0, PPIN capability is not supported. An attempt to access\r
- /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.\r
- ///\r
- UINT32 PPIN_CAP:1;\r
- UINT32 Reserved3:4;\r
- ///\r
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
- /// Turbo mode is disabled.\r
- ///\r
- UINT32 RatioLimit:1;\r
- ///\r
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
- /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
- /// programmable.\r
- ///\r
- UINT32 TDPLimit:1;\r
- ///\r
- /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r
- /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r
- /// specify an temperature offset.\r
- ///\r
- UINT32 TJOFFSET:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
- /// minimum ratio (maximum efficiency) that the processor can operates, in\r
- /// units of 100MHz.\r
- ///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved6:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;\r
-\r
-\r
-/**\r
- Package. MC Bank Error Configuration (R/W).\r
-\r
- @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
- /// to log additional info in bits 36:32.\r
- ///\r
- UINT32 MemErrorLogEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package.\r
-\r
- @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which\r
- /// PROCHOT# will be asserted. The value is degree C.\r
- ///\r
- UINT32 TemperatureTarget:8;\r
- ///\r
- /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature\r
- /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#\r
- /// will assert at the offset target temperature. Write is permitted only\r
- /// MSR_PLATFORM_INFO.[30] is set.\r
- ///\r
- UINT32 TCCActivationOffset:4;\r
- UINT32 Reserved2:4;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
- /// limit of 9 core active.\r
- ///\r
- UINT32 Maximum9C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
- /// limit of 10core active.\r
- ///\r
- UINT32 Maximum10C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
- /// limit of 11 core active.\r
- ///\r
- UINT32 Maximum11C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
- /// limit of 12 core active.\r
- ///\r
- UINT32 Maximum12C:8;\r
- ///\r
- /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
- /// limit of 13 core active.\r
- ///\r
- UINT32 Maximum13C:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
- /// limit of 14 core active.\r
- ///\r
- UINT32 Maximum14C:8;\r
- ///\r
- /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
- /// limit of 15 core active.\r
- ///\r
- UINT32 Maximum15C:8;\r
- UINT32 Reserved:7;\r
- ///\r
- /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
- /// the processor uses override configuration specified in\r
- /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
- /// uses factory-set configuration (Default).\r
- ///\r
- UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;\r
-\r
-\r
-/**\r
- Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.\r
-\r
- @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 5:0] Recoverable Address LSB.\r
- ///\r
- UINT32 RecoverableAddressLSB:6;\r
- ///\r
- /// [Bits 8:6] Address Mode.\r
- ///\r
- UINT32 AddressMode:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bits 31:16] PCI Express Requestor ID.\r
- ///\r
- UINT32 PCIExpressRequestorID:16;\r
- ///\r
- /// [Bits 39:32] PCI Express Segment Number.\r
- ///\r
- UINT32 PCIExpressSegmentNumber:8;\r
- UINT32 Reserved2:24;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
- and its corresponding slice of L3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.\r
- MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.\r
- MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474\r
-#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478\r
-#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
- and its corresponding slice of L3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.\r
- MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.\r
- MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475\r
-#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479\r
-#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
- and its corresponding slice of L3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.\r
- MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.\r
- MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476\r
-#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A\r
-#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E\r
-/// @}\r
-\r
-\r
-/**\r
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
- 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r
- and its corresponding slice of L3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.\r
- MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.\r
- MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.\r
- @{\r
-**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477\r
-#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B\r
-#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Package RAPL Perf Status (R/O).\r
-\r
- @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
- Domain.".\r
-\r
- @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
-\r
-\r
-/**\r
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
-\r
-\r
-/**\r
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
-\r
-\r
-/**\r
- Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
-\r
- @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC0:1;\r
- ///\r
- /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC1:1;\r
- ///\r
- /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC2:1;\r
- ///\r
- /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC3:1;\r
- UINT32 Reserved1:28;\r
- ///\r
- /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC0:1;\r
- ///\r
- /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC1:1;\r
- ///\r
- /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC2:1;\r
- ///\r
- /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC3:1;\r
- UINT32 Reserved2:28;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore perfmon per-socket global control.\r
-\r
- @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00\r
-\r
-\r
-/**\r
- Package. Uncore perfmon per-socket global status.\r
-\r
- @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01\r
-\r
-\r
-/**\r
- Package. Uncore perfmon per-socket global configuration.\r
-\r
- @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon U-box wide status.\r
-\r
- @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon box wide status.\r
-\r
- @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon local box wide control.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon box wide filter.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon local box wide control.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon box wide filter.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon local box wide control.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon box wide filter.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59\r
-\r
-\r
-/**\r
- Package. Uncore C-box 10 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon local box wide control.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon box wide filter.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79\r
-\r
-\r
-/**\r
- Package. Uncore C-box 11 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon local box wide control.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon box wide filter.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99\r
-\r
-\r
-/**\r
- Package. Uncore C-box 12 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon local box wide control.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon box wide filter.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 13 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon local box wide control.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon box wide filter.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon counter 0.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon counter 1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon counter 2.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon counter 3.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 14 perfmon box wide filter1.\r
-\r
- @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);\r
- AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);\r
- @endcode\r
- @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
-**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel processors based on the Nehalem microarchitecture.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __NEHALEM_MSR_H__\r
-#define __NEHALEM_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel processors based on the Nehalem microarchitecture?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x1A || \\r
- DisplayModel == 0x1E || \\r
- DisplayModel == 0x1F || \\r
- DisplayModel == 0x2E \\r
- ) \\r
- )\r
-\r
-/**\r
- Package. Model Specific Platform ID (R).\r
-\r
- @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);\r
- @endcode\r
- @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
-**/\r
-#define MSR_NEHALEM_PLATFORM_ID 0x00000017\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:18;\r
- ///\r
- /// [Bits 52:50] See Table 2-2.\r
- ///\r
- UINT32 PlatformId:3;\r
- UINT32 Reserved3:11;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_PLATFORM_ID_REGISTER;\r
-\r
-\r
-/**\r
- Thread. SMI Counter (R/O).\r
-\r
- @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_SMI_COUNT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);\r
- @endcode\r
- @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
-**/\r
-#define MSR_NEHALEM_SMI_COUNT 0x00000034\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r
- /// RESET.\r
- ///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_SMI_COUNT_REGISTER;\r
-\r
-\r
-/**\r
- Package. see http://biosbits.org.\r
-\r
- @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);\r
- AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
-**/\r
-#define MSR_NEHALEM_PLATFORM_INFO 0x000000CE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
- /// of the frequency that invariant TSC runs at. The invariant TSC\r
- /// frequency can be computed by multiplying this ratio by 133.33 MHz.\r
- ///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
- ///\r
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
- /// Turbo mode is disabled.\r
- ///\r
- UINT32 RatioLimit:1;\r
- ///\r
- /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)\r
- /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are\r
- /// programmable, and when set to 0, indicates TDC and TDP Limits for\r
- /// Turbo mode are not programmable.\r
- ///\r
- UINT32 TDC_TDPLimit:1;\r
- UINT32 Reserved3:2;\r
- UINT32 Reserved4:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
- /// minimum ratio (maximum efficiency) that the processor can operates, in\r
- /// units of 133.33MHz.\r
- ///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_PLATFORM_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Core. C-State Configuration Control (R/W) Note: C-state values are\r
- processor specific C-state code names, unrelated to MWAIT extension C-state\r
- parameters or ACPI CStates. See http://biosbits.org.\r
-\r
- @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
-**/\r
-#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
- /// processor-specific C-state code name (consuming the least power). for\r
- /// the package. The default is set as factory-configured package C-state\r
- /// limit. The following C-state code name encodings are supported: 000b:\r
- /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r
- /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package\r
- /// C-state limit. Note: This field cannot be used to limit package\r
- /// C-state to C3.\r
- ///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
- /// IO_read instructions sent to IO register specified by\r
- /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
- ///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
- /// until next reset.\r
- ///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:8;\r
- ///\r
- /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores\r
- /// in a deep C-State will wake only when the event message is destined\r
- /// for that core. When 0, all processor cores in a deep C-State will wake\r
- /// for an event message.\r
- ///\r
- UINT32 InterruptFiltering:1;\r
- ///\r
- /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
- /// will conditionally demote C6/C7 requests to C3 based on uncore\r
- /// auto-demote information.\r
- ///\r
- UINT32 C3AutoDemotion:1;\r
- ///\r
- /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
- /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
- /// auto-demote information.\r
- ///\r
- UINT32 C1AutoDemotion:1;\r
- ///\r
- /// [Bit 27] Enable C3 Undemotion (R/W).\r
- ///\r
- UINT32 C3Undemotion:1;\r
- ///\r
- /// [Bit 28] Enable C1 Undemotion (R/W).\r
- ///\r
- UINT32 C1Undemotion:1;\r
- ///\r
- /// [Bit 29] Package C State Demotion Enable (R/W).\r
- ///\r
- UINT32 CStateDemotion:1;\r
- ///\r
- /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
- ///\r
- UINT32 CStateUndemotion:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Core. Power Management IO Redirection in C-state (R/W) See\r
- http://biosbits.org.\r
-\r
- @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);\r
- AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
-**/\r
-#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
- /// visible to software for IO redirection. If IO MWAIT Redirection is\r
- /// enabled, reads to this address will be consumed by the power\r
- /// management logic and decoded to MWAIT instructions. When IO port\r
- /// address redirection is enabled, this is the IO port address reported\r
- /// to the OS/software.\r
- ///\r
- UINT32 Lvl2Base:16;\r
- ///\r
- /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
- /// maximum C-State code name to be included when IO read to MWAIT\r
- /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r
- /// is the max C-State to include 001b - C6 is the max C-State to include\r
- /// 010b - C7 is the max C-State to include.\r
- ///\r
- UINT32 CStateRange:3;\r
- UINT32 Reserved1:13;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER;\r
-\r
-\r
-/**\r
- Enable Misc. Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r
- ///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 2-2. Default value is 1.\r
- ///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
- ///\r
- /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
- ///\r
- /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.\r
- ///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
- ///\r
- /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r
- ///\r
- UINT32 LimitCpuidMaxval:1;\r
- ///\r
- /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
- ///\r
- /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
- /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
- /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
- /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
- /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
- /// the power-on default value is used by BIOS to detect hardware support\r
- /// of turbo mode. If power-on default value is 1, turbo mode is available\r
- /// in the processor. If power-on default value is 0, turbo mode is not\r
- /// available.\r
- ///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Thread.\r
-\r
- @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);\r
- AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
-**/\r
-#define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
- /// PROCHOT# will be asserted. The value is degree C.\r
- ///\r
- UINT32 TemperatureTarget:8;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER;\r
-\r
-\r
-/**\r
- Miscellaneous Feature Control (R/W).\r
-\r
- @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
- /// L2 hardware prefetcher, which fetches additional lines of code or data\r
- /// into the L2 cache.\r
- ///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- ///\r
- /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
- /// disables the adjacent cache line prefetcher, which fetches the cache\r
- /// line that comprises a cache line pair (128 bytes).\r
- ///\r
- UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
- ///\r
- /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
- /// the L1 data cache prefetcher, which fetches the next cache line into\r
- /// L1 data cache.\r
- ///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
- ///\r
- /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
- /// data cache IP prefetcher, which uses sequential load history (based on\r
- /// instruction Pointer of previous loads) to determine whether to\r
- /// prefetch additional lines.\r
- ///\r
- UINT32 DCUIPPrefetcherDisable:1;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Offcore Response Event Select Register (R/W).\r
-\r
- @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);\r
- AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6\r
-\r
-\r
-/**\r
- See http://biosbits.org.\r
-\r
- @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);\r
- AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
-**/\r
-#define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,\r
- /// enables hardware coordination of Enhanced Intel Speedstep Technology\r
- /// request from processor cores; When 1, disables hardware coordination\r
- /// of Enhanced Intel Speedstep Technology requests.\r
- ///\r
- UINT32 EISTHardwareCoordinationDisable:1;\r
- ///\r
- /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes\r
- /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with\r
- /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by\r
- /// CPUID.(EAX=06h):ECX[3].\r
- ///\r
- UINT32 EnergyPerformanceBiasEnable:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_MISC_PWR_MGMT_REGISTER;\r
-\r
-\r
-/**\r
- See http://biosbits.org.\r
-\r
- @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);\r
- AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.\r
-**/\r
-#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt\r
- /// granularity.\r
- ///\r
- UINT32 TDPLimit:15;\r
- ///\r
- /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0\r
- /// indicates override is not active, and a value = 1 indicates active.\r
- ///\r
- UINT32 TDPLimitOverrideEnable:1;\r
- ///\r
- /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp\r
- /// granularity.\r
- ///\r
- UINT32 TDCLimit:15;\r
- ///\r
- /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0\r
- /// indicates override is not active, and a value = 1 indicates active.\r
- ///\r
- UINT32 TDCLimitOverrideEnable:1;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);\r
- @endcode\r
- @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
- /// limit of 1 core active.\r
- ///\r
- UINT32 Maximum1C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
- /// limit of 2 core active.\r
- ///\r
- UINT32 Maximum2C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
- /// limit of 3 core active.\r
- ///\r
- UINT32 Maximum3C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
- /// limit of 4 core active.\r
- ///\r
- UINT32 Maximum4C:8;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
- "Filtering of Last Branch Records.".\r
-\r
- @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_LBR_SELECT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);\r
- AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
-**/\r
-#define MSR_NEHALEM_LBR_SELECT 0x000001C8\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] CPL_EQ_0.\r
- ///\r
- UINT32 CPL_EQ_0:1;\r
- ///\r
- /// [Bit 1] CPL_NEQ_0.\r
- ///\r
- UINT32 CPL_NEQ_0:1;\r
- ///\r
- /// [Bit 2] JCC.\r
- ///\r
- UINT32 JCC:1;\r
- ///\r
- /// [Bit 3] NEAR_REL_CALL.\r
- ///\r
- UINT32 NEAR_REL_CALL:1;\r
- ///\r
- /// [Bit 4] NEAR_IND_CALL.\r
- ///\r
- UINT32 NEAR_IND_CALL:1;\r
- ///\r
- /// [Bit 5] NEAR_RET.\r
- ///\r
- UINT32 NEAR_RET:1;\r
- ///\r
- /// [Bit 6] NEAR_IND_JMP.\r
- ///\r
- UINT32 NEAR_IND_JMP:1;\r
- ///\r
- /// [Bit 7] NEAR_REL_JMP.\r
- ///\r
- UINT32 NEAR_REL_JMP:1;\r
- ///\r
- /// [Bit 8] FAR_BRANCH.\r
- ///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_LBR_SELECT_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
- that points to the MSR containing the most recent branch record. See\r
- MSR_LASTBRANCH_0_FROM_IP (at 680H).\r
-\r
- @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
- last branch instruction that the processor executed prior to the last\r
- exception that was generated or the last interrupt that was handled.\r
-\r
- @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);\r
- @endcode\r
- @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
-**/\r
-#define MSR_NEHALEM_LER_FROM_LIP 0x000001DD\r
-\r
-\r
-/**\r
- Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
- to the target of the last branch instruction that the processor executed\r
- prior to the last exception that was generated or the last interrupt that\r
- was handled.\r
-\r
- @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);\r
- @endcode\r
- @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
-**/\r
-#define MSR_NEHALEM_LER_TO_LIP 0x000001DE\r
-\r
-\r
-/**\r
- Core. Power Control Register. See http://biosbits.org.\r
-\r
- @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_POWER_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);\r
- AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
-**/\r
-#define MSR_NEHALEM_POWER_CTL 0x000001FC\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r
- /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r
- /// operating point when all execution cores enter MWAIT (C1).\r
- ///\r
- UINT32 C1EEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_POWER_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Thread. (RO).\r
-\r
- @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);\r
- @endcode\r
- @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:29;\r
- ///\r
- /// [Bit 61] UNC_Ovf Uncore overflowed if 1.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- UINT32 Reserved3:2;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Thread. (R/W).\r
-\r
- @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:29;\r
- ///\r
- /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- UINT32 Reserved3:2;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
-\r
- @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
-**/\r
-#define MSR_NEHALEM_PEBS_ENABLE 0x000003F1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC0:1;\r
- ///\r
- /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC1:1;\r
- ///\r
- /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC2:1;\r
- ///\r
- /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC3:1;\r
- UINT32 Reserved1:28;\r
- ///\r
- /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC0:1;\r
- ///\r
- /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC1:1;\r
- ///\r
- /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC2:1;\r
- ///\r
- /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC3:1;\r
- UINT32 Reserved2:28;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_PEBS_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r
- Facility.".\r
-\r
- @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);\r
- AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r
-**/\r
-#define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
- /// that will be counted. (R/W).\r
- ///\r
- UINT32 MinimumThreshold:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_PEBS_LD_LAT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C3 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);\r
- AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
-**/\r
-#define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C6 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C7 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);\r
- AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
-**/\r
-#define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA\r
-\r
-\r
-/**\r
- Core. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
- Residency Counter. (R/O) Value since last reset that this core is in\r
- processor-specific C3 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);\r
- AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
-**/\r
-#define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC\r
-\r
-\r
-/**\r
- Core. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
- Residency Counter. (R/O) Value since last reset that this core is in\r
- processor-specific C6 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD\r
-\r
-\r
-/**\r
- Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
- branch record registers on the last branch record stack. The From_IP part of\r
- the stack contains pointers to the source instruction. See also: - Last\r
- Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in\r
- Section 17.4.8.1.\r
-\r
- @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);\r
- AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F\r
-/// @}\r
-\r
-\r
-/**\r
- Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction.\r
-\r
- @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);\r
- AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
- MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF\r
-/// @}\r
-\r
-\r
-/**\r
- Package.\r
-\r
- @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);\r
- AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);\r
- @endcode\r
- @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.\r
-**/\r
-#define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] From M to S (R/W).\r
- ///\r
- UINT32 FromMtoS:1;\r
- ///\r
- /// [Bit 1] From E to S (R/W).\r
- ///\r
- UINT32 FromEtoS:1;\r
- ///\r
- /// [Bit 2] From S to S (R/W).\r
- ///\r
- UINT32 FromStoS:1;\r
- ///\r
- /// [Bit 3] From F to S (R/W).\r
- ///\r
- UINT32 FromFtoS:1;\r
- ///\r
- /// [Bit 4] From M to I (R/W).\r
- ///\r
- UINT32 FromMtoI:1;\r
- ///\r
- /// [Bit 5] From E to I (R/W).\r
- ///\r
- UINT32 FromEtoI:1;\r
- ///\r
- /// [Bit 6] From S to I (R/W).\r
- ///\r
- UINT32 FromStoI:1;\r
- ///\r
- /// [Bit 7] From F to I (R/W).\r
- ///\r
- UINT32 FromFtoI:1;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER;\r
-\r
-\r
-/**\r
- Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
- Facility.".\r
-\r
- @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391\r
-\r
-\r
-/**\r
- Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
- Facility.".\r
-\r
- @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392\r
-\r
-\r
-/**\r
- Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
- Facility.".\r
-\r
- @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393\r
-\r
-\r
-/**\r
- Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
- Facility.".\r
-\r
- @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394\r
-\r
-\r
-/**\r
- Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
- Facility.".\r
-\r
- @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395\r
-\r
-\r
-/**\r
- Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".\r
-\r
- @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);\r
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.\r
-**/\r
-#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396\r
-\r
-\r
-/**\r
- Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration\r
- Facility.".\r
-\r
- @param ECX MSR_NEHALEM_UNCORE_PMCi\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);\r
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.\r
- MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.\r
- MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.\r
- MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.\r
- MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.\r
- MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.\r
- MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.\r
- MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_UNCORE_PMC0 0x000003B0\r
-#define MSR_NEHALEM_UNCORE_PMC1 0x000003B1\r
-#define MSR_NEHALEM_UNCORE_PMC2 0x000003B2\r
-#define MSR_NEHALEM_UNCORE_PMC3 0x000003B3\r
-#define MSR_NEHALEM_UNCORE_PMC4 0x000003B4\r
-#define MSR_NEHALEM_UNCORE_PMC5 0x000003B5\r
-#define MSR_NEHALEM_UNCORE_PMC6 0x000003B6\r
-#define MSR_NEHALEM_UNCORE_PMC7 0x000003B7\r
-/// @}\r
-\r
-/**\r
- Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration\r
- Facility.".\r
-\r
- @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.\r
- MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.\r
- MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.\r
- MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.\r
- MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.\r
- MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.\r
- MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.\r
- MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon fixed counter.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon fixed counter control MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon global control MSR.\r
-\r
- @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon global status MSR.\r
-\r
- @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon global overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);\r
- AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.\r
-**/\r
-#define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);\r
- AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.\r
-**/\r
-#define MSR_NEHALEM_U_PMON_CTR 0x00000C11\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1vperfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_CTR0 0x00000C91\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_CTR1 0x00000C93\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_CTR2 0x00000C95\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96\r
-\r
-\r
-/**\r
- Package. Uncore W-box perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_W_PMON_CTR3 0x00000C97\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon time stamp unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon DSP unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon ISS unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon MAP unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon MIC THR select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon PGT unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon PLD unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon ZDP unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon time stamp unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon DSP unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon ISS unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon MAP unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon MIC THR select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon PGT unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon PLD unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon ZDP unit select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E\r
-\r
-\r
-/**\r
- Package. Uncore R-box 0 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);\r
- AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon local box control MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon local box status MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon event select MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E\r
-\r
-\r
-/**\r
- Package. Uncore R-box 1 perfmon counter MSR.\r
-\r
- @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);\r
- AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.\r
-**/\r
-#define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon local box match MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45\r
-\r
-\r
-/**\r
- Package. Uncore B-box 0 perfmon local box mask MSR.\r
-\r
- @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);\r
- AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.\r
-**/\r
-#define MSR_NEHALEM_B0_PMON_MASK 0x00000E46\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon local box match MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49\r
-\r
-\r
-/**\r
- Package. Uncore S-box 0 perfmon local box mask MSR.\r
-\r
- @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);\r
- AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.\r
-**/\r
-#define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon local box match MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D\r
-\r
-\r
-/**\r
- Package. Uncore B-box 1 perfmon local box mask MSR.\r
-\r
- @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);\r
- AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.\r
-**/\r
-#define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon local box address match/mask config MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon local box address match MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55\r
-\r
-\r
-/**\r
- Package. Uncore M-box 0 perfmon local box address mask MSR.\r
-\r
- @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);\r
- AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.\r
-**/\r
-#define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon local box match MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59\r
-\r
-\r
-/**\r
- Package. Uncore S-box 1 perfmon local box mask MSR.\r
-\r
- @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);\r
- AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.\r
-**/\r
-#define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon local box address match/mask config MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon local box address match MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D\r
-\r
-\r
-/**\r
- Package. Uncore M-box 1 perfmon local box address mask MSR.\r
-\r
- @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);\r
- AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.\r
-**/\r
-#define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for P6 Family Processors.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __P6_MSR_H__\r
-#define __P6_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is P6 Family Processors?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x03 || \\r
- DisplayModel == 0x05 || \\r
- DisplayModel == 0x07 || \\r
- DisplayModel == 0x08 || \\r
- DisplayModel == 0x0A || \\r
- DisplayModel == 0x0B \\r
- ) \\r
- )\r
-\r
-/**\r
- See Section 2.22, "MSRs in Pentium Processors.".\r
-\r
- @param ECX MSR_P6_P5_MC_ADDR (0x00000000)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);\r
- AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);\r
- @endcode\r
- @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
-**/\r
-#define MSR_P6_P5_MC_ADDR 0x00000000\r
-\r
-\r
-/**\r
- See Section 2.22, "MSRs in Pentium Processors.".\r
-\r
- @param ECX MSR_P6_P5_MC_TYPE (0x00000001)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);\r
- AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);\r
- @endcode\r
- @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
-**/\r
-#define MSR_P6_P5_MC_TYPE 0x00000001\r
-\r
-\r
-/**\r
- See Section 17.17, "Time-Stamp Counter.".\r
-\r
- @param ECX MSR_P6_TSC (0x00000010)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_TSC);\r
- AsmWriteMsr64 (MSR_P6_TSC, Msr);\r
- @endcode\r
- @note MSR_P6_TSC is defined as TSC in SDM.\r
-**/\r
-#define MSR_P6_TSC 0x00000010\r
-\r
-\r
-/**\r
- Platform ID (R) The operating system can use this MSR to determine "slot"\r
- information for the processor and the proper microcode update to load.\r
-\r
- @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_IA32_PLATFORM_ID_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);\r
- @endcode\r
- @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r
-**/\r
-#define MSR_P6_IA32_PLATFORM_ID 0x00000017\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:18;\r
- ///\r
- /// [Bits 52:50] Platform Id (R) Contains information concerning the\r
- /// intended platform for the processor.\r
- ///\r
- /// 52 51 50\r
- /// 0 0 0 Processor Flag 0.\r
- /// 0 0 1 Processor Flag 1\r
- /// 0 1 0 Processor Flag 2\r
- /// 0 1 1 Processor Flag 3\r
- /// 1 0 0 Processor Flag 4\r
- /// 1 0 1 Processor Flag 5\r
- /// 1 1 0 Processor Flag 6\r
- /// 1 1 1 Processor Flag 7\r
- ///\r
- UINT32 PlatformId:3;\r
- ///\r
- /// [Bits 56:53] L2 Cache Latency Read.\r
- ///\r
- UINT32 L2CacheLatencyRead:4;\r
- UINT32 Reserved3:3;\r
- ///\r
- /// [Bit 60] Clock Frequency Ratio Read.\r
- ///\r
- UINT32 ClockFrequencyRatioRead:1;\r
- UINT32 Reserved4:3;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_IA32_PLATFORM_ID_REGISTER;\r
-\r
-\r
-/**\r
- Section 10.4.4, "Local APIC Status and Location.".\r
-\r
- @param ECX MSR_P6_APIC_BASE (0x0000001B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_APIC_BASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_APIC_BASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_APIC_BASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);\r
- AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);\r
- @endcode\r
- @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.\r
-**/\r
-#define MSR_P6_APIC_BASE 0x0000001B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_P6_APIC_BASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.\r
- ///\r
- UINT32 BSP:1;\r
- UINT32 Reserved2:2;\r
- ///\r
- /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =\r
- /// Disabled.\r
- ///\r
- UINT32 EN:1;\r
- ///\r
- /// [Bits 31:12] APIC Base Address.\r
- ///\r
- UINT32 ApicBase:20;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_APIC_BASE_REGISTER;\r
-\r
-\r
-/**\r
- Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
- features; (R) indicates current processor configuration.\r
-\r
- @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_EBL_CR_POWERON_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);\r
- AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);\r
- @endcode\r
- @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.\r
-**/\r
-#define MSR_P6_EBL_CR_POWERON 0x0000002A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.\r
- ///\r
- UINT32 DataErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)\r
- /// 1 = Enabled 0 = Disabled.\r
- ///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.\r
- ///\r
- UINT32 AERR_DriveEnable:1;\r
- ///\r
- /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =\r
- /// Disabled.\r
- ///\r
- UINT32 BERR_Enable:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =\r
- /// Enabled 0 = Disabled.\r
- ///\r
- UINT32 BERR_DriverEnable:1;\r
- ///\r
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.\r
- ///\r
- UINT32 BINIT_DriverEnable:1;\r
- ///\r
- /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.\r
- ///\r
- UINT32 OutputTriStateEnable:1;\r
- ///\r
- /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.\r
- ///\r
- UINT32 ExecuteBIST:1;\r
- ///\r
- /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.\r
- ///\r
- UINT32 AERR_ObservationEnabled:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.\r
- ///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- ///\r
- /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.\r
- ///\r
- UINT32 InOrderQueueDepth:1;\r
- ///\r
- /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.\r
- ///\r
- UINT32 ResetVector:1;\r
- ///\r
- /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.\r
- ///\r
- UINT32 FRCModeEnable:1;\r
- ///\r
- /// [Bits 17:16] APIC Cluster ID (R).\r
- ///\r
- UINT32 APICClusterID:2;\r
- ///\r
- /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =\r
- /// 133MHz 11 = Reserved.\r
- ///\r
- UINT32 SystemBusFrequency:2;\r
- ///\r
- /// [Bits 21:20] Symmetric Arbitration ID (R).\r
- ///\r
- UINT32 SymmetricArbitrationID:2;\r
- ///\r
- /// [Bits 25:22] Clock Frequency Ratio (R).\r
- ///\r
- UINT32 ClockFrequencyRatio:4;\r
- ///\r
- /// [Bit 26] Low Power Mode Enable (R/W).\r
- ///\r
- UINT32 LowPowerModeEnable:1;\r
- ///\r
- /// [Bit 27] Clock Frequency Ratio.\r
- ///\r
- UINT32 ClockFrequencyRatio1:1;\r
- UINT32 Reserved4:4;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_EBL_CR_POWERON_REGISTER;\r
-\r
-\r
-/**\r
- Test Control Register.\r
-\r
- @param ECX MSR_P6_TEST_CTL (0x00000033)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_TEST_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_TEST_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_TEST_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);\r
- AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.\r
-**/\r
-#define MSR_P6_TEST_CTL 0x00000033\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_P6_TEST_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:30;\r
- ///\r
- /// [Bit 30] Streaming Buffer Disable.\r
- ///\r
- UINT32 StreamingBufferDisable:1;\r
- ///\r
- /// [Bit 31] Disable LOCK# Assertion for split locked access.\r
- ///\r
- UINT32 Disable_LOCK:1;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_TEST_CTL_REGISTER;\r
-\r
-\r
-/**\r
- BIOS Update Trigger Register.\r
-\r
- @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);\r
- AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);\r
- @endcode\r
- @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.\r
-**/\r
-#define MSR_P6_BIOS_UPDT_TRIG 0x00000079\r
-\r
-\r
-/**\r
- Chunk n data register D[63:0]: used to write to and read from the L2.\r
-\r
- @param ECX MSR_P6_BBL_CR_Dn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);\r
- AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);\r
- @endcode\r
- @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.\r
- MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.\r
- MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.\r
- @{\r
-**/\r
-#define MSR_P6_BBL_CR_D0 0x00000088\r
-#define MSR_P6_BBL_CR_D1 0x00000089\r
-#define MSR_P6_BBL_CR_D2 0x0000008A\r
-/// @}\r
-\r
-\r
-/**\r
- BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to\r
- write to and read from the L2 depending on the usage model.\r
-\r
- @param ECX MSR_P6_BIOS_SIGN (0x0000008B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);\r
- AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);\r
- @endcode\r
- @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.\r
-**/\r
-#define MSR_P6_BIOS_SIGN 0x0000008B\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_PERFCTR0 (0x000000C1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);\r
- AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.\r
- MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.\r
- @{\r
-**/\r
-#define MSR_P6_PERFCTR0 0x000000C1\r
-#define MSR_P6_PERFCTR1 0x000000C2\r
-/// @}\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRCAP (0x000000FE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);\r
- AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.\r
-**/\r
-#define MSR_P6_MTRRCAP 0x000000FE\r
-\r
-\r
-/**\r
- Address register: used to send specified address (A31-A3) to L2 during cache\r
- initialization accesses.\r
-\r
- @param ECX MSR_P6_BBL_CR_ADDR (0x00000116)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_BBL_CR_ADDR_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);\r
- AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);\r
- @endcode\r
- @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.\r
-**/\r
-#define MSR_P6_BBL_CR_ADDR 0x00000116\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:3;\r
- ///\r
- /// [Bits 31:3] Address bits\r
- ///\r
- UINT32 Address:29;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_BBL_CR_ADDR_REGISTER;\r
-\r
-\r
-/**\r
- Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.\r
-\r
- @param ECX MSR_P6_BBL_CR_DECC (0x00000118)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);\r
- AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);\r
- @endcode\r
- @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.\r
-**/\r
-#define MSR_P6_BBL_CR_DECC 0x00000118\r
-\r
-\r
-/**\r
- Control register: used to program L2 commands to be issued via cache\r
- configuration accesses mechanism. Also receives L2 lookup response.\r
-\r
- @param ECX MSR_P6_BBL_CR_CTL (0x00000119)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_BBL_CR_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_BBL_CR_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_BBL_CR_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);\r
- AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.\r
-**/\r
-#define MSR_P6_BBL_CR_CTL 0x00000119\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_P6_BBL_CR_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 4:0] L2 Command\r
- /// Data Read w/ LRU update (RLU)\r
- /// Tag Read w/ Data Read (TRR)\r
- /// Tag Inquire (TI)\r
- /// L2 Control Register Read (CR)\r
- /// L2 Control Register Write (CW)\r
- /// Tag Write w/ Data Read (TWR)\r
- /// Tag Write w/ Data Write (TWW)\r
- /// Tag Write (TW).\r
- ///\r
- UINT32 L2Command:5;\r
- ///\r
- /// [Bits 6:5] State to L2\r
- ///\r
- UINT32 StateToL2:2;\r
- UINT32 Reserved:1;\r
- ///\r
- /// [Bits 9:8] Way to L2.\r
- ///\r
- UINT32 WayToL2:2;\r
- ///\r
- /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.\r
- ///\r
- UINT32 Way:2;\r
- ///\r
- /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.\r
- ///\r
- UINT32 MESI:2;\r
- ///\r
- /// [Bits 15:14] State from L2.\r
- ///\r
- UINT32 StateFromL2:2;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 17] L2 Hit.\r
- ///\r
- UINT32 L2Hit:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bits 20:19] User supplied ECC.\r
- ///\r
- UINT32 UserEcc:2;\r
- ///\r
- /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.\r
- ///\r
- UINT32 ProcessorNumber:1;\r
- UINT32 Reserved4:10;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_BBL_CR_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Trigger register: used to initiate a cache configuration accesses access,\r
- Write only with Data = 0.\r
-\r
- @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);\r
- AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);\r
- @endcode\r
- @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.\r
-**/\r
-#define MSR_P6_BBL_CR_TRIG 0x0000011A\r
-\r
-\r
-/**\r
- Busy register: indicates when a cache configuration accesses L2 command is\r
- in progress. D[0] = 1 = BUSY.\r
-\r
- @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);\r
- AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);\r
- @endcode\r
- @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.\r
-**/\r
-#define MSR_P6_BBL_CR_BUSY 0x0000011B\r
-\r
-\r
-/**\r
- Control register 3: used to configure the L2 Cache.\r
-\r
- @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_BBL_CR_CTL3_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);\r
- AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);\r
- @endcode\r
- @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.\r
-**/\r
-#define MSR_P6_BBL_CR_CTL3 0x0000011E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] L2 Configured (read/write ).\r
- ///\r
- UINT32 L2Configured:1;\r
- ///\r
- /// [Bits 4:1] L2 Cache Latency (read/write).\r
- ///\r
- UINT32 L2CacheLatency:4;\r
- ///\r
- /// [Bit 5] ECC Check Enable (read/write).\r
- ///\r
- UINT32 ECCCheckEnable:1;\r
- ///\r
- /// [Bit 6] Address Parity Check Enable (read/write).\r
- ///\r
- UINT32 AddressParityCheckEnable:1;\r
- ///\r
- /// [Bit 7] CRTN Parity Check Enable (read/write).\r
- ///\r
- UINT32 CRTNParityCheckEnable:1;\r
- ///\r
- /// [Bit 8] L2 Enabled (read/write).\r
- ///\r
- UINT32 L2Enabled:1;\r
- ///\r
- /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way\r
- /// Reserved.\r
- ///\r
- UINT32 L2Associativity:2;\r
- ///\r
- /// [Bits 12:11] Number of L2 banks (read only).\r
- ///\r
- UINT32 L2Banks:2;\r
- ///\r
- /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes\r
- /// 1MByte 2MByte 4MBytes.\r
- ///\r
- UINT32 CacheSizePerBank:5;\r
- ///\r
- /// [Bit 18] Cache State error checking enable (read/write).\r
- ///\r
- UINT32 CacheStateErrorEnable:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes\r
- /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.\r
- ///\r
- UINT32 L2AddressRange:3;\r
- ///\r
- /// [Bit 23] L2 Hardware Disable (read only).\r
- ///\r
- UINT32 L2HardwareDisable:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 25] Cache bus fraction (read only).\r
- ///\r
- UINT32 CacheBusFraction:1;\r
- UINT32 Reserved3:6;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_BBL_CR_CTL3_REGISTER;\r
-\r
-\r
-/**\r
- CS register target for CPL 0 code.\r
-\r
- @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);\r
- AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);\r
- @endcode\r
- @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.\r
-**/\r
-#define MSR_P6_SYSENTER_CS_MSR 0x00000174\r
-\r
-\r
-/**\r
- Stack pointer for CPL 0 stack.\r
-\r
- @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);\r
- AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);\r
- @endcode\r
- @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.\r
-**/\r
-#define MSR_P6_SYSENTER_ESP_MSR 0x00000175\r
-\r
-\r
-/**\r
- CPL 0 code entry point.\r
-\r
- @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);\r
- AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);\r
- @endcode\r
- @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.\r
-**/\r
-#define MSR_P6_SYSENTER_EIP_MSR 0x00000176\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MCG_CAP (0x00000179)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);\r
- AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);\r
- @endcode\r
- @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.\r
-**/\r
-#define MSR_P6_MCG_CAP 0x00000179\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MCG_STATUS (0x0000017A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);\r
- AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);\r
- @endcode\r
- @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.\r
-**/\r
-#define MSR_P6_MCG_STATUS 0x0000017A\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MCG_CTL (0x0000017B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);\r
- AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);\r
- @endcode\r
- @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.\r
-**/\r
-#define MSR_P6_MCG_CTL 0x0000017B\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_PERFEVTSELn\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_PERFEVTSEL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_PERFEVTSEL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_PERFEVTSEL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);\r
- @endcode\r
- @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM.\r
- MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.\r
- @{\r
-**/\r
-#define MSR_P6_PERFEVTSEL0 0x00000186\r
-#define MSR_P6_PERFEVTSEL1 0x00000187\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and\r
- #MSR_P6_PERFEVTSEL1.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Event Select Refer to Performance Counter section for a\r
- /// list of event encodings.\r
- ///\r
- UINT32 EventSelect:8;\r
- ///\r
- /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable\r
- /// all count options.\r
- ///\r
- UINT32 UMASK:8;\r
- ///\r
- /// [Bit 16] USER Controls the counting of events at Privilege levels of\r
- /// 1, 2, and 3.\r
- ///\r
- UINT32 USR:1;\r
- ///\r
- /// [Bit 17] OS Controls the counting of events at Privilege level of 0.\r
- ///\r
- UINT32 OS:1;\r
- ///\r
- /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.\r
- ///\r
- UINT32 E:1;\r
- ///\r
- /// [Bit 19] PC Enabled the signaling of performance counter overflow via\r
- /// BP0 pin.\r
- ///\r
- UINT32 PC:1;\r
- ///\r
- /// [Bit 20] INT Enables the signaling of counter overflow via input to\r
- /// APIC 1 = Enable 0 = Disable.\r
- ///\r
- UINT32 INT:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 22] ENABLE Enables the counting of performance events in both\r
- /// counters 1 = Enable 0 = Disable.\r
- ///\r
- UINT32 EN:1;\r
- ///\r
- /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0\r
- /// = Non-Inverted.\r
- ///\r
- UINT32 INV:1;\r
- ///\r
- /// [Bits 31:24] CMASK (Counter Mask).\r
- ///\r
- UINT32 CMASK:8;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_PERFEVTSEL_REGISTER;\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_DEBUGCTLMSR_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);\r
- AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);\r
- @endcode\r
- @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.\r
-**/\r
-#define MSR_P6_DEBUGCTLMSR 0x000001D9\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable/Disable Last Branch Records.\r
- ///\r
- UINT32 LBR:1;\r
- ///\r
- /// [Bit 1] Branch Trap Flag.\r
- ///\r
- UINT32 BTF:1;\r
- ///\r
- /// [Bit 2] Performance Monitoring/Break Point Pins.\r
- ///\r
- UINT32 PB0:1;\r
- ///\r
- /// [Bit 3] Performance Monitoring/Break Point Pins.\r
- ///\r
- UINT32 PB1:1;\r
- ///\r
- /// [Bit 4] Performance Monitoring/Break Point Pins.\r
- ///\r
- UINT32 PB2:1;\r
- ///\r
- /// [Bit 5] Performance Monitoring/Break Point Pins.\r
- ///\r
- UINT32 PB3:1;\r
- ///\r
- /// [Bit 6] Enable/Disable Execution Trace Messages.\r
- ///\r
- UINT32 TR:1;\r
- UINT32 Reserved1:25;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_DEBUGCTLMSR_REGISTER;\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);\r
- AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);\r
- @endcode\r
- @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.\r
-**/\r
-#define MSR_P6_LASTBRANCHFROMIP 0x000001DB\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);\r
- AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);\r
- @endcode\r
- @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.\r
-**/\r
-#define MSR_P6_LASTBRANCHTOIP 0x000001DC\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_LASTINTFROMIP (0x000001DD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);\r
- AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);\r
- @endcode\r
- @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.\r
-**/\r
-#define MSR_P6_LASTINTFROMIP 0x000001DD\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_LASTINTTOIP (0x000001DE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);\r
- AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);\r
- @endcode\r
- @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.\r
-**/\r
-#define MSR_P6_LASTINTTOIP 0x000001DE\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRPHYSBASEn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);\r
- AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.\r
- MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.\r
- MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.\r
- MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.\r
- MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.\r
- MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.\r
- MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.\r
- MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r
- @{\r
-**/\r
-#define MSR_P6_MTRRPHYSBASE0 0x00000200\r
-#define MSR_P6_MTRRPHYSBASE1 0x00000202\r
-#define MSR_P6_MTRRPHYSBASE2 0x00000204\r
-#define MSR_P6_MTRRPHYSBASE3 0x00000206\r
-#define MSR_P6_MTRRPHYSBASE4 0x00000208\r
-#define MSR_P6_MTRRPHYSBASE5 0x0000020A\r
-#define MSR_P6_MTRRPHYSBASE6 0x0000020C\r
-#define MSR_P6_MTRRPHYSBASE7 0x0000020E\r
-/// @}\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRPHYSMASKn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);\r
- AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.\r
- MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.\r
- MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.\r
- MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.\r
- MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.\r
- MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.\r
- MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.\r
- MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r
- @{\r
-**/\r
-#define MSR_P6_MTRRPHYSMASK0 0x00000201\r
-#define MSR_P6_MTRRPHYSMASK1 0x00000203\r
-#define MSR_P6_MTRRPHYSMASK2 0x00000205\r
-#define MSR_P6_MTRRPHYSMASK3 0x00000207\r
-#define MSR_P6_MTRRPHYSMASK4 0x00000209\r
-#define MSR_P6_MTRRPHYSMASK5 0x0000020B\r
-#define MSR_P6_MTRRPHYSMASK6 0x0000020D\r
-#define MSR_P6_MTRRPHYSMASK7 0x0000020F\r
-/// @}\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX64K_00000 0x00000250\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX16K_80000 0x00000258\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX16K_A0000 0x00000259\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX4K_C0000 0x00000268\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX4K_C8000 0x00000269\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX4K_D0000 0x0000026A\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX4K_D8000 0x0000026B\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX4K_E0000 0x0000026C\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX4K_E8000 0x0000026D\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX4K_F0000 0x0000026E\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);\r
- AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);\r
- @endcode\r
- @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r
-**/\r
-#define MSR_P6_MTRRFIX4K_F8000 0x0000026F\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_MTRRDEFTYPE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);\r
- AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);\r
- @endcode\r
- @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.\r
-**/\r
-#define MSR_P6_MTRRDEFTYPE 0x000002FF\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Default memory type.\r
- ///\r
- UINT32 Type:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 10] Fixed MTRR enable.\r
- ///\r
- UINT32 FE:1;\r
- ///\r
- /// [Bit 11] MTRR Enable.\r
- ///\r
- UINT32 E:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_MTRRDEFTYPE_REGISTER;\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_P6_MC0_CTL (0x00000400)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);\r
- AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);\r
- @endcode\r
- @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM.\r
- MSR_P6_MC1_CTL is defined as MC1_CTL in SDM.\r
- MSR_P6_MC2_CTL is defined as MC2_CTL in SDM.\r
- MSR_P6_MC3_CTL is defined as MC3_CTL in SDM.\r
- MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_P6_MC0_CTL 0x00000400\r
-#define MSR_P6_MC1_CTL 0x00000404\r
-#define MSR_P6_MC2_CTL 0x00000408\r
-#define MSR_P6_MC3_CTL 0x00000410\r
-#define MSR_P6_MC4_CTL 0x0000040C\r
-/// @}\r
-\r
-\r
-/**\r
-\r
- Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,\r
- except bits 0, 4, 57, and 61 are hardcoded to 1.\r
-\r
- @param ECX MSR_P6_MCn_STATUS\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_P6_MC_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_P6_MC_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_P6_MC_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);\r
- AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM.\r
- MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM.\r
- MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM.\r
- MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM.\r
- MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_P6_MC0_STATUS 0x00000401\r
-#define MSR_P6_MC1_STATUS 0x00000405\r
-#define MSR_P6_MC2_STATUS 0x00000409\r
-#define MSR_P6_MC3_STATUS 0x00000411\r
-#define MSR_P6_MC4_STATUS 0x0000040D\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_P6_MC0_STATUS to\r
- #MSR_P6_MC4_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] MC_STATUS_MCACOD.\r
- ///\r
- UINT32 MC_STATUS_MCACOD:16;\r
- ///\r
- /// [Bits 31:16] MC_STATUS_MSCOD.\r
- ///\r
- UINT32 MC_STATUS_MSCOD:16;\r
- UINT32 Reserved:25;\r
- ///\r
- /// [Bit 57] MC_STATUS_DAM.\r
- ///\r
- UINT32 MC_STATUS_DAM:1;\r
- ///\r
- /// [Bit 58] MC_STATUS_ADDRV.\r
- ///\r
- UINT32 MC_STATUS_ADDRV:1;\r
- ///\r
- /// [Bit 59] MC_STATUS_MISCV.\r
- ///\r
- UINT32 MC_STATUS_MISCV:1;\r
- ///\r
- /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is\r
- /// hardcoded to 1.).\r
- ///\r
- UINT32 MC_STATUS_EN:1;\r
- ///\r
- /// [Bit 61] MC_STATUS_UC.\r
- ///\r
- UINT32 MC_STATUS_UC:1;\r
- ///\r
- /// [Bit 62] MC_STATUS_O.\r
- ///\r
- UINT32 MC_STATUS_O:1;\r
- ///\r
- /// [Bit 63] MC_STATUS_V.\r
- ///\r
- UINT32 MC_STATUS_V:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_P6_MC_STATUS_REGISTER;\r
-\r
-\r
-/**\r
-\r
- MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.\r
-\r
- @param ECX MSR_P6_MC0_ADDR (0x00000402)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);\r
- AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);\r
- @endcode\r
- @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM.\r
- MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM.\r
- MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM.\r
- MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM.\r
- MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_P6_MC0_ADDR 0x00000402\r
-#define MSR_P6_MC1_ADDR 0x00000406\r
-#define MSR_P6_MC2_ADDR 0x0000040A\r
-#define MSR_P6_MC3_ADDR 0x00000412\r
-#define MSR_P6_MC4_ADDR 0x0000040E\r
-/// @}\r
-\r
-\r
-/**\r
- Defined in MCA architecture but not implemented in the P6 family processors.\r
-\r
- @param ECX MSR_P6_MC0_MISC (0x00000403)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);\r
- AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);\r
- @endcode\r
- @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM.\r
- MSR_P6_MC1_MISC is defined as MC1_MISC in SDM.\r
- MSR_P6_MC2_MISC is defined as MC2_MISC in SDM.\r
- MSR_P6_MC3_MISC is defined as MC3_MISC in SDM.\r
- MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.\r
- @{\r
-**/\r
-#define MSR_P6_MC0_MISC 0x00000403\r
-#define MSR_P6_MC1_MISC 0x00000407\r
-#define MSR_P6_MC2_MISC 0x0000040B\r
-#define MSR_P6_MC3_MISC 0x00000413\r
-#define MSR_P6_MC4_MISC 0x0000040F\r
-/// @}\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Pentium(R) 4 Processors.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __PENTIUM_4_MSR_H__\r
-#define __PENTIUM_4_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Pentium(R) 4 Processors?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x0F \\r
- )\r
-\r
-/**\r
- 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range\r
- Determination.".\r
-\r
- @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)\r
- Enables and disables processor features; (R) indicates current processor\r
- configuration.\r
-\r
- @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state\r
- /// output is enabled (1) or disabled (0) as set by the strapping of SMI#.\r
- /// The value in this bit is written on the deassertion of RESET#; the bit\r
- /// is set to 1 when the address bus signal is asserted.\r
- ///\r
- UINT32 OutputTriStateEnabled:1;\r
- ///\r
- /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST\r
- /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The\r
- /// value in this bit is written on the deassertion of RESET#; the bit is\r
- /// set to 1 when the address bus signal is asserted.\r
- ///\r
- UINT32 ExecuteBIST:1;\r
- ///\r
- /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue\r
- /// depth for the system bus is 1 (1) or up to 12 (0) as set by the\r
- /// strapping of A7#. The value in this bit is written on the deassertion\r
- /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
- ///\r
- UINT32 InOrderQueueDepth:1;\r
- ///\r
- /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#\r
- /// observation is enabled (0) or disabled (1) as determined by the\r
- /// strapping of A9#. The value in this bit is written on the deassertion\r
- /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
- ///\r
- UINT32 MCERR_ObservationDisabled:1;\r
- ///\r
- /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#\r
- /// observation is enabled (0) or disabled (1) as determined by the\r
- /// strapping of A10#. The value in this bit is written on the deassertion\r
- /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
- ///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- ///\r
- /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID\r
- /// value as set by the strapping of A12# and A11#. The logical cluster ID\r
- /// value is written into the field on the deassertion of RESET#; the\r
- /// field is set to 1 when the address bus signal is asserted.\r
- ///\r
- UINT32 APICClusterID:2;\r
- ///\r
- /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled\r
- /// (0) or disabled (1) as set by the strapping of A15#. The value in this\r
- /// bit is written on the deassertion of RESET#; the bit is set to 1 when\r
- /// the address bus signal is asserted.\r
- ///\r
- UINT32 BusParkDisable:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set\r
- /// by the strapping of BR[3:0]. The logical ID value is written into the\r
- /// field on the deassertion of RESET#; the field is set to 1 when the\r
- /// address bus signal is asserted.\r
- ///\r
- UINT32 AgentID:2;\r
- UINT32 Reserved2:18;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)\r
- Enables and disables processor features.\r
-\r
- @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the\r
- /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear\r
- /// to disabled (0, default).\r
- ///\r
- UINT32 RCNT_SCNT:1;\r
- ///\r
- /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data\r
- /// bus parity checking; clear to enable parity checking.\r
- ///\r
- UINT32 DataErrorCheckingDisable:1;\r
- ///\r
- /// [Bit 2] Response Error Checking Disable (R/W) Set to disable\r
- /// (default); clear to enable.\r
- ///\r
- UINT32 ResponseErrorCheckingDisable:1;\r
- ///\r
- /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable\r
- /// (default); clear to enable.\r
- ///\r
- UINT32 AddressRequestErrorCheckingDisable:1;\r
- ///\r
- /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving\r
- /// for initiator bus requests (default); clear to enable.\r
- ///\r
- UINT32 InitiatorMCERR_Disable:1;\r
- ///\r
- /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving\r
- /// for initiator internal errors (default); clear to enable.\r
- ///\r
- UINT32 InternalMCERR_Disable:1;\r
- ///\r
- /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver\r
- /// (default); clear to enable driver.\r
- ///\r
- UINT32 BINIT_DriverDisable:1;\r
- UINT32 Reserved1:25;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;\r
-\r
-\r
-/**\r
- 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of\r
- this MSR varies according to the MODEL value in the CPUID version\r
- information. The following bit field layout applies to Pentium 4 and Xeon\r
- Processors with MODEL encoding equal or greater than 2. (R) The field\r
- Indicates the current processor frequency configuration.\r
-\r
- @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);\r
- @endcode\r
- @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable\r
- /// bus speed: *EncodingScalable Bus Speed*\r
- ///\r
- /// 000B 100 MHz (Model 2).\r
- /// 000B 266 MHz (Model 3 or 4)\r
- /// 001B 133 MHz\r
- /// 010B 200 MHz\r
- /// 011B 166 MHz\r
- /// 100B 333 MHz (Model 6)\r
- ///\r
- /// 133.33 MHz should be utilized if performing calculation with System\r
- /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if\r
- /// performing calculation with System Bus Speed when encoding is 011B.\r
- /// 266.67 MHz should be utilized if performing calculation with System\r
- /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33\r
- /// MHz should be utilized if performing calculation with System Bus\r
- /// Speed when encoding is 100B and model encoding = 6. All other values\r
- /// are reserved.\r
- ///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved2:5;\r
- ///\r
- /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R)\r
- /// The processor core clock frequency to system bus frequency ratio\r
- /// observed at the de-assertion of the reset pin.\r
- ///\r
- UINT32 ClockRatio:8;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;\r
-\r
-\r
-/**\r
- 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of\r
- this MSR varies according to the MODEL value of the CPUID version\r
- information. This bit field layout applies to Pentium 4 and Xeon Processors\r
- with MODEL encoding less than 2. Indicates current processor frequency\r
- configuration.\r
-\r
- @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);\r
- @endcode\r
- @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:21;\r
- ///\r
- /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable\r
- /// bus speed: *Encoding* *Scalable Bus Speed*\r
- ///\r
- /// 000B 100 MHz All others values reserved.\r
- ///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section\r
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
- state at time of machine check error. When in non-64-bit modes at the time\r
- of the error, bits 63-32 do not contain valid data.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_RAX 0x00000180\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section\r
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
- state at time of machine check error. When in non-64-bit modes at the time\r
- of the error, bits 63-32 do not contain valid data.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_RBX 0x00000181\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section\r
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
- state at time of machine check error. When in non-64-bit modes at the time\r
- of the error, bits 63-32 do not contain valid data.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_RCX 0x00000182\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section\r
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
- state at time of machine check error. When in non-64-bit modes at the time\r
- of the error, bits 63-32 do not contain valid data.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_RDX 0x00000183\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section\r
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
- state at time of machine check error. When in non-64-bit modes at the time\r
- of the error, bits 63-32 do not contain valid data.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_RSI 0x00000184\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section\r
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
- state at time of machine check error. When in non-64-bit modes at the time\r
- of the error, bits 63-32 do not contain valid data.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_RDI 0x00000185\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section\r
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
- state at time of machine check error. When in non-64-bit modes at the time\r
- of the error, bits 63-32 do not contain valid data.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_RBP 0x00000186\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section\r
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
- state at time of machine check error. When in non-64-bit modes at the time\r
- of the error, bits 63-32 do not contain valid data.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_RSP 0x00000187\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section\r
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
- state at time of machine check error. When in non-64-bit modes at the time\r
- of the error, bits 63-32 do not contain valid data.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section\r
- 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
- state at time of machine check error. When in non-64-bit modes at the time\r
- of the error, bits 63-32 do not contain valid data.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_RIP 0x00000189\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,\r
- "IA32_MCG Extended Machine Check State MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_4_MCG_MISC_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_MISC 0x0000018A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] DS When set, the bit indicates that a page assist or page\r
- /// fault occurred during DS normal operation. The processors response is\r
- /// to shut down. The bit is used as an aid for debugging DS handling\r
- /// code. It is the responsibility of the user (BIOS or operating system)\r
- /// to clear this bit for normal operation.\r
- ///\r
- UINT32 DS:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_4_MCG_MISC_REGISTER;\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG\r
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
- state-save MSRs) exist only in Intel 64 processors. These registers contain\r
- valid information only when the processor is operating in 64-bit mode at the\r
- time of the error.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_R8 0x00000190\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,\r
- "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the\r
- associated state-save MSRs) exist only in Intel 64 processors. These\r
- registers contain valid information only when the processor is operating in\r
- 64-bit mode at the time of the error.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_R9 0x00000191\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG\r
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
- state-save MSRs) exist only in Intel 64 processors. These registers contain\r
- valid information only when the processor is operating in 64-bit mode at the\r
- time of the error.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_R10 0x00000192\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG\r
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
- state-save MSRs) exist only in Intel 64 processors. These registers contain\r
- valid information only when the processor is operating in 64-bit mode at the\r
- time of the error.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_R11 0x00000193\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG\r
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
- state-save MSRs) exist only in Intel 64 processors. These registers contain\r
- valid information only when the processor is operating in 64-bit mode at the\r
- time of the error.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_R12 0x00000194\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG\r
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
- state-save MSRs) exist only in Intel 64 processors. These registers contain\r
- valid information only when the processor is operating in 64-bit mode at the\r
- time of the error.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_R13 0x00000195\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG\r
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
- state-save MSRs) exist only in Intel 64 processors. These registers contain\r
- valid information only when the processor is operating in 64-bit mode at the\r
- time of the error.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_R14 0x00000196\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG\r
- Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
- state-save MSRs) exist only in Intel 64 processors. These registers contain\r
- valid information only when the processor is operating in 64-bit mode at the\r
- time of the error.\r
-\r
- @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MCG_R15 0x00000197\r
-\r
-\r
-/**\r
- Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:\r
- When read, specifies the value of the target TM2 transition last written.\r
- When set, it sets the next target value for TM2 transition. 4, 6. Shared.\r
- For Family F, Model 4 and Model 6 processors: When read, specifies the value\r
- of the target TM2 transition last written. Writes may cause #GP exceptions.\r
-\r
- @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).\r
-\r
- @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Fast-Strings Enable. See Table 2-2.\r
- ///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.\r
- ///\r
- UINT32 FPU:1;\r
- ///\r
- /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal\r
- /// Monitor," and see Table 2-2.\r
- ///\r
- UINT32 TM1:1;\r
- ///\r
- /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception\r
- /// to be issued instead of a split-lock cycle. Operating systems that set\r
- /// this bit must align system structures to avoid split-lock scenarios.\r
- /// When the bit is clear (default), normal split-locks are issued to the\r
- /// bus.\r
- /// This debug feature is specific to the Pentium 4 processor.\r
- ///\r
- UINT32 SplitLockDisable:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level\r
- /// cache is disabled; when clear (default) the third-level cache is\r
- /// enabled. This flag is reserved for processors that do not have a\r
- /// third-level cache. Note that the bit controls only the third-level\r
- /// cache; and only if overall caching is enabled through the CD flag of\r
- /// control register CR0, the page-level cache controls, and/or the MTRRs.\r
- /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".\r
- ///\r
- UINT32 ThirdLevelCacheDisable:1;\r
- ///\r
- /// [Bit 7] Performance Monitoring Available (R) See Table 2-2.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- ///\r
- /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is\r
- /// suppressed during a Split Lock access. When clear (default), LOCK is\r
- /// not suppressed.\r
- ///\r
- UINT32 SuppressLockEnable:1;\r
- ///\r
- /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.\r
- /// When clear (default), enables the prefetch queue.\r
- ///\r
- UINT32 PrefetchQueueDisable:1;\r
- ///\r
- /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt\r
- /// reporting through the FERR# pin is enabled; when clear, this interrupt\r
- /// reporting function is disabled.\r
- /// When this flag is set and the processor is in the stop-clock state\r
- /// (STPCLK# is asserted), asserting the FERR# pin signals to the\r
- /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,\r
- /// SMI#, or RESET#) is pending and that the processor should return to\r
- /// normal operation to handle the interrupt. This flag does not affect\r
- /// the normal operation of the FERR# pin (to indicate an unmasked\r
- /// floatingpoint error) when the STPCLK# pin is not asserted.\r
- ///\r
- UINT32 FERR:1;\r
- ///\r
- /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See\r
- /// Table 2-2. When set, the processor does not support branch trace\r
- /// storage (BTS); when clear, BTS is supported.\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable\r
- /// (R) See Table 2-2. When set, the processor does not support processor\r
- /// event-based sampling (PEBS); when clear, PEBS is supported.\r
- ///\r
- UINT32 PEBS:1;\r
- ///\r
- /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal\r
- /// sensor indicates that the die temperature is at the predetermined\r
- /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce\r
- /// the bus to core ratio and voltage according to the value last written\r
- /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the\r
- /// processor does not change the VID signals or the bus to core ratio\r
- /// when the processor enters a thermal managed state. If the TM2 feature\r
- /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then\r
- /// this feature is not supported and BIOS must not alter the contents of\r
- /// this bit location. The processor is operating out of spec if both this\r
- /// bit and the TM1 bit are set to disabled states.\r
- ///\r
- UINT32 TM2:1;\r
- UINT32 Reserved3:4;\r
- ///\r
- /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
- ///\r
- UINT32 MONITOR:1;\r
- ///\r
- /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1,\r
- /// the processor fetches the cache line of the 128-byte sector containing\r
- /// currently required data. When set to 0, the processor fetches both\r
- /// cache lines in the sector.\r
- /// Single processor platforms should not set this bit. Server platforms\r
- /// should set or clear this bit based on platform performance observed\r
- /// in validation and testing. BIOS may contain a setup option that\r
- /// controls the setting of this bit.\r
- ///\r
- UINT32 AdjacentCacheLinePrefetchDisable:1;\r
- UINT32 Reserved4:2;\r
- ///\r
- /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this\r
- /// can cause unexpected behavior to software that depends on the\r
- /// availability of CPUID leaves greater than 3.\r
- ///\r
- UINT32 LimitCpuidMaxval:1;\r
- ///\r
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- ///\r
- /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache\r
- /// is placed in shared mode; when clear (default), the cache is placed in\r
- /// adaptive mode. This bit is only enabled for IA-32 processors that\r
- /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data\r
- /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are\r
- /// identical, data in L1 is shared across logical processors. Otherwise,\r
- /// L1 is not shared and cache use is competitive. If the Context ID\r
- /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1,\r
- /// the ability to switch modes is not supported. BIOS must not alter the\r
- /// contents of IA32_MISC_ENABLE[24].\r
- ///\r
- UINT32 L1DataCacheContextMode:1;\r
- UINT32 Reserved5:7;\r
- UINT32 Reserved6:2;\r
- ///\r
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 XD:1;\r
- UINT32 Reserved7:29;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- 3, 4, 6. Shared. Platform Feature Requirements (R).\r
-\r
- @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);\r
- @endcode\r
- @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:18;\r
- ///\r
- /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor\r
- /// has specific platform requirements. The details of the platform\r
- /// requirements are listed in the respective data sheets of the processor.\r
- ///\r
- UINT32 PLATFORM:1;\r
- UINT32 Reserved2:13;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains\r
- a pointer to the last branch instruction that the processor executed prior\r
- to the last exception that was generated or the last interrupt that was\r
- handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear\r
- IP Linear address of the last branch instruction (If IA-32e mode is active).\r
- From Linear IP Linear address of the last branch instruction. Reserved.\r
-\r
- @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);\r
- @endcode\r
- @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area\r
- contains a pointer to the target of the last branch instruction that the\r
- processor executed prior to the last exception that was generated or the\r
- last interrupt that was handled. See Section 17.13.3, "Last Exception\r
- Records.". Unique. From Linear IP Linear address of the target of the last\r
- branch instruction (If IA-32e mode is active). From Linear IP Linear address\r
- of the target of the last branch instruction. Reserved.\r
-\r
- @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);\r
- @endcode\r
- @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug\r
- features are used. Bit definitions are discussed in the referenced section.\r
- See Section 17.13.1, "MSR_DEBUGCTLA MSR.".\r
-\r
- @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an\r
- index (0-3 or 0-15) that points to the top of the last branch record stack\r
- (that is, that points the index of the MSR containing the most recent branch\r
- record). See Section 17.13.2, "LBR Stack for Processors Based on Intel\r
- NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.\r
-\r
- @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA\r
-\r
-\r
-/**\r
- 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record\r
- registers on the last branch record stack. It contains pointers to the\r
- source and destination instruction for one of the last four branches,\r
- exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through\r
- MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models\r
- 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See\r
- Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
- for Processors based on Skylake Microarchitecture.".\r
-\r
- @param ECX MSR_PENTIUM_4_LASTBRANCH_n\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB\r
-#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC\r
-#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD\r
-#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE\r
-/// @}\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
-\r
- @param ECX MSR_PENTIUM_4_BPU_COUNTERn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM.\r
- MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM.\r
- MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM.\r
- MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300\r
-#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301\r
-#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302\r
-#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303\r
-/// @}\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
-\r
- @param ECX MSR_PENTIUM_4_MS_COUNTERn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM.\r
- MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM.\r
- MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM.\r
- MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304\r
-#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305\r
-#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306\r
-#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307\r
-/// @}\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
-\r
- @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM.\r
- MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM.\r
- MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM.\r
- MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308\r
-#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309\r
-#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A\r
-#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B\r
-/// @}\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
-\r
- @param ECX MSR_PENTIUM_4_IQ_COUNTERn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM.\r
- MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM.\r
- MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM.\r
- MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM.\r
- MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM.\r
- MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C\r
-#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D\r
-#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E\r
-#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F\r
-#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310\r
-#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311\r
-/// @}\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_BPU_CCCRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM.\r
- MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM.\r
- MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM.\r
- MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360\r
-#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361\r
-#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362\r
-#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363\r
-/// @}\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_MS_CCCRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM.\r
- MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM.\r
- MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM.\r
- MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_MS_CCCR0 0x00000364\r
-#define MSR_PENTIUM_4_MS_CCCR1 0x00000365\r
-#define MSR_PENTIUM_4_MS_CCCR2 0x00000366\r
-#define MSR_PENTIUM_4_MS_CCCR3 0x00000367\r
-/// @}\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_FLAME_CCCRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM.\r
- MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM.\r
- MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM.\r
- MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368\r
-#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369\r
-#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A\r
-#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B\r
-/// @}\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_IQ_CCCRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM.\r
- MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM.\r
- MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM.\r
- MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM.\r
- MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM.\r
- MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C\r
-#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D\r
-#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E\r
-#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F\r
-#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370\r
-#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371\r
-/// @}\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9\r
-\r
-\r
-/**\r
- 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r
- available on later processors. It is only available on processor family 0FH,\r
- models 01H-02H.\r
-\r
- @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA\r
-\r
-\r
-/**\r
- 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r
- available on later processors. It is only available on processor family 0FH,\r
- models 01H-02H.\r
-\r
- @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_ALF_ESCRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM.\r
- MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM.\r
- MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM.\r
- MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM.\r
- MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM.\r
- MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA\r
-#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB\r
-#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC\r
-#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD\r
-#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0\r
-#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1\r
-/// @}\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)\r
- Controls the enabling of processor event sampling and replay tagging.\r
-\r
- @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 12:0] See Table 19-36.\r
- ///\r
- UINT32 EventNum:13;\r
- UINT32 Reserved1:11;\r
- ///\r
- /// [Bit 24] UOP Tag Enables replay tagging when set.\r
- ///\r
- UINT32 UOP:1;\r
- ///\r
- /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical\r
- /// processor when set; disables PEBS when clear (default). See Section\r
- /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
- /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors\r
- /// that do not support Intel HyperThreading Technology.\r
- ///\r
- UINT32 ENABLE_PEBS_MY_THR:1;\r
- ///\r
- /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical\r
- /// processor when set; disables PEBS when clear (default). See Section\r
- /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
- /// logical processor. This bit is reserved for IA-32 processors that do\r
- /// not support Intel Hyper-Threading Technology.\r
- ///\r
- UINT32 ENABLE_PEBS_OTH_THR:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- 0, 1, 2, 3, 4, 6. Shared. See Table 19-36.\r
-\r
- @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2\r
-\r
-\r
-/**\r
- 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
- record registers on the last branch record stack (680H-68FH). This part of\r
- the stack contains pointers to the source instruction for one of the last 16\r
- branches, exceptions, or interrupts taken by the processor. The MSRs at\r
- 680H-68FH, 6C0H-6CfH are not available in processor releases before family\r
- 0FH, model 03H. These MSRs replace MSRs previously located at\r
- 1DBH-1DEH.which performed the same function for early releases. See Section\r
- 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for\r
- Processors based on Skylake Microarchitecture.".\r
-\r
- @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F\r
-/// @}\r
-\r
-\r
-/**\r
- 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
- record registers on the last branch record stack (6C0H-6CFH). This part of\r
- the stack contains pointers to the destination instruction for one of the\r
- last 16 branches, exceptions, or interrupts that the processor took. See\r
- Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
- for Processors based on Skylake Microarchitecture.".\r
-\r
- @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
- MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF\r
-/// @}\r
-\r
-\r
-/**\r
- 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section\r
- 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
- 8-MByte L3 Cache.".\r
-\r
- @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC\r
-\r
-\r
-/**\r
- 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).\r
-\r
- @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD\r
-\r
-\r
-/**\r
- 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section\r
- 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
- 8-MByte L3 Cache.".\r
-\r
- @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE\r
-\r
-\r
-/**\r
- 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).\r
-\r
- @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF\r
-\r
-\r
-/**\r
- 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section\r
- 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
- 8-MByte L3 Cache.".\r
-\r
- @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0\r
-\r
-\r
-/**\r
- 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).\r
-\r
- @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1\r
-\r
-\r
-/**\r
- 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,\r
- "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte\r
- L3 Cache.".\r
-\r
- @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2\r
-\r
-\r
-/**\r
- 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,\r
- "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte\r
- L3 Cache.".\r
-\r
- @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3\r
-\r
-\r
-/**\r
- 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section\r
- 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
- 8MByte L3 Cache.".\r
-\r
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC\r
-\r
-\r
-/**\r
- 6. Shared. GBUSQ Event Control and Counter Register (R/W).\r
-\r
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD\r
-\r
-\r
-/**\r
- 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section\r
- 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
- 8MByte L3 Cache.".\r
-\r
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE\r
-\r
-\r
-/**\r
- 6. Shared. GSNPQ Event Control and Counter Register (R/W).\r
-\r
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF\r
-\r
-\r
-/**\r
- 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,\r
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte\r
- L3 Cache.".\r
-\r
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0\r
-\r
-\r
-/**\r
- 6. Shared. FSB Event Control and Counter Register (R/W).\r
-\r
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1\r
-\r
-\r
-/**\r
- 6. Shared. FSB Event Control and Counter Register (R/W).\r
-\r
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2\r
-\r
-\r
-/**\r
- 6. Shared. FSB Event Control and Counter Register (R/W).\r
-\r
- @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);\r
- AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r
-**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Pentium M Processors.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __PENTIUM_M_MSR_H__\r
-#define __PENTIUM_M_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Pentium M Processors?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x0D \\r
- ) \\r
- )\r
-\r
-/**\r
- See Section 2.22, "MSRs in Pentium Processors.".\r
-\r
- @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000\r
-\r
-\r
-/**\r
- See Section 2.22, "MSRs in Pentium Processors.".\r
-\r
- @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001\r
-\r
-\r
-/**\r
- Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
- features. (R) Indicates current processor configuration.\r
-\r
- @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the\r
- /// Pentium M processor.\r
- ///\r
- UINT32 DataErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on\r
- /// the Pentium M processor.\r
- ///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
- ///\r
- /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium\r
- /// M processor.\r
- ///\r
- UINT32 MCERR_DriveEnable:1;\r
- ///\r
- /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium\r
- /// M processor.\r
- ///\r
- UINT32 AddressParityEnable:1;\r
- UINT32 Reserved2:2;\r
- ///\r
- /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on\r
- /// the Pentium M processor.\r
- ///\r
- UINT32 BINIT_DriverEnable:1;\r
- ///\r
- /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 OutputTriStateEnable:1;\r
- ///\r
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
- ///\r
- UINT32 ExecuteBIST:1;\r
- ///\r
- /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
- /// Always 0 on the Pentium M processor.\r
- ///\r
- UINT32 MCERR_ObservationEnabled:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
- /// Always 0 on the Pentium M processor.\r
- ///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes\r
- /// Always 0 on the Pentium M processor.\r
- ///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M\r
- /// processor.\r
- ///\r
- UINT32 APICClusterID:2;\r
- ///\r
- /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always\r
- /// 0 on the Pentium M processor.\r
- ///\r
- UINT32 SystemBusFrequency:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium\r
- /// M processor.\r
- ///\r
- UINT32 SymmetricArbitrationID:2;\r
- ///\r
- /// [Bits 26:22] Clock Frequency Ratio (R/O).\r
- ///\r
- UINT32 ClockFrequencyRatio:5;\r
- UINT32 Reserved7:5;\r
- UINT32 Reserved8:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;\r
-\r
-\r
-/**\r
- Last Branch Record n (R/W) One of 8 last branch record registers on the last\r
- branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold\r
- the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section\r
- 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
- Processors)".\r
-\r
- @param ECX MSR_PENTIUM_M_LASTBRANCH_n\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
- MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040\r
-#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041\r
-#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042\r
-#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043\r
-#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044\r
-#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045\r
-#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046\r
-#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047\r
-/// @}\r
-\r
-\r
-/**\r
- Reserved.\r
-\r
- @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
- /// Indicates if the L2 is hardware-disabled.\r
- ///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the\r
- /// cache data bus. ECC is always generated on write cycles. 1. = Disabled\r
- /// (default) 2. = Enabled For the Pentium M processor, ECC checking on\r
- /// the cache data bus is always enabled.\r
- ///\r
- UINT32 ECCCheckEnable:1;\r
- UINT32 Reserved2:2;\r
- ///\r
- /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
- /// Disabled (default) Until this bit is set the processor will not\r
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
- ///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved3:14;\r
- ///\r
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
- ///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved4:8;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;\r
-\r
-\r
-/**\r
-\r
-\r
- @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
- /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
- /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
- /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
- /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
- ///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_M_THERM2_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:3;\r
- ///\r
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
- /// this bit enables the thermal control circuit (TCC) portion of the\r
- /// Intel Thermal Monitor feature. This allows processor clocks to be\r
- /// automatically modulated based on the processor's thermal sensor\r
- /// operation. 0 = Disabled (default). The automatic thermal control\r
- /// circuit enable bit determines if the thermal control circuit (TCC)\r
- /// will be activated when the processor's internal thermal sensor\r
- /// determines the processor is about to exceed its maximum operating\r
- /// temperature. When the TCC is activated and TM1 is enabled, the\r
- /// processors clocks will be forced to a 50% duty cycle. BIOS must enable\r
- /// this feature. The bit should not be confused with the on-demand\r
- /// thermal control circuit enable bit.\r
- ///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
- /// monitoring enabled 0 = Performance monitoring disabled.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the\r
- /// processor to indicate a pending break event within the processor 0 =\r
- /// Indicates compatible FERR# signaling behavior This bit must be set to\r
- /// 1 to support XAPIC interrupt model usage.\r
- /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't\r
- /// support branch trace storage (BTS) 0 = BTS is supported\r
- ///\r
- UINT32 FERR:1;\r
- ///\r
- /// [Bit 11] Branch Trace Storage Unavailable (RO)\r
- /// 1 = Processor doesn't support branch trace storage (BTS)\r
- /// 0 = BTS is supported\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =\r
- /// Processor does not support processor event based sampling (PEBS); 0 =\r
- /// PEBS is supported. The Pentium M processor does not support PEBS.\r
- ///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved5:3;\r
- ///\r
- /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
- /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M\r
- /// processor, this bit may be configured to be read-only.\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved6:6;\r
- ///\r
- /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
- /// disabled. xTPR messages are optional messages that allow the processor\r
- /// to inform the chipset of its priority. The default is processor\r
- /// specific.\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points\r
- to the MSR containing the most recent branch record. See also: -\r
- MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,\r
- and Exception Recording (Pentium M Processors)".\r
-\r
- @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Debug Control (R/W) Controls how several debug features are used. Bit\r
- definitions are discussed in the referenced section. See Section 17.15,\r
- "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".\r
-\r
- @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9\r
-\r
-\r
-/**\r
- Last Exception Record To Linear IP (R) This area contains a pointer to the\r
- target of the last branch instruction that the processor executed prior to\r
- the last exception that was generated or the last interrupt that was\r
- handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording\r
- (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception\r
- MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);\r
- @endcode\r
- @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD\r
-\r
-\r
-/**\r
- Last Exception Record From Linear IP (R) Contains a pointer to the last\r
- branch instruction that the processor executed prior to the last exception\r
- that was generated or the last interrupt that was handled. See Section\r
- 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
- Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);\r
- @endcode\r
- @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE\r
-\r
-\r
-/**\r
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC4_CTL 0x0000040C\r
-\r
-\r
-/**\r
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is\r
- either not implemented or contains no address if the ADDRV flag in the\r
- MSR_MC4_STATUS register is clear. When not implemented in the processor, all\r
- reads and writes to this MSR will cause a general-protection exception.\r
-\r
- @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC3_CTL 0x00000410\r
-\r
-\r
-/**\r
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC3_STATUS 0x00000411\r
-\r
-\r
-/**\r
- See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is\r
- either not implemented or contains no address if the ADDRV flag in the\r
- MSR_MC3_STATUS register is clear. When not implemented in the processor, all\r
- reads and writes to this MSR will cause a general-protection exception.\r
-\r
- @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
-**/\r
-#define MSR_PENTIUM_M_MC3_ADDR 0x00000412\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Pentium Processors.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __PENTIUM_MSR_H__\r
-#define __PENTIUM_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Pentium Processors?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x05 && \\r
- ( \\r
- DisplayModel == 0x01 || \\r
- DisplayModel == 0x02 || \\r
- DisplayModel == 0x04 \\r
- ) \\r
- )\r
-\r
-/**\r
- See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r
-\r
- @param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);\r
- AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
-**/\r
-#define MSR_PENTIUM_P5_MC_ADDR 0x00000000\r
-\r
-\r
-/**\r
- See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r
-\r
- @param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);\r
- AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
-**/\r
-#define MSR_PENTIUM_P5_MC_TYPE 0x00000001\r
-\r
-\r
-/**\r
- See Section 17.17, "Time-Stamp Counter.".\r
-\r
- @param ECX MSR_PENTIUM_TSC (0x00000010)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);\r
- AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_TSC is defined as TSC in SDM.\r
-**/\r
-#define MSR_PENTIUM_TSC 0x00000010\r
-\r
-\r
-/**\r
- See Section 18.6.9.1, "Control and Event Select Register (CESR).".\r
-\r
- @param ECX MSR_PENTIUM_CESR (0x00000011)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);\r
- AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_CESR is defined as CESR in SDM.\r
-**/\r
-#define MSR_PENTIUM_CESR 0x00000011\r
-\r
-\r
-/**\r
- Section 18.6.9.3, "Events Counted.".\r
-\r
- @param ECX MSR_PENTIUM_CTRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);\r
- AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);\r
- @endcode\r
- @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.\r
- MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.\r
- @{\r
-**/\r
-#define MSR_PENTIUM_CTR0 0x00000012\r
-#define MSR_PENTIUM_CTR1 0x00000013\r
-/// @}\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __SANDY_BRIDGE_MSR_H__\r
-#define __SANDY_BRIDGE_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel processors based on the Sandy Bridge microarchitecture?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x2A || \\r
- DisplayModel == 0x2D \\r
- ) \\r
- )\r
-\r
-/**\r
- Thread. SMI Counter (R/O).\r
-\r
- @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] SMI Count (R/O) Count SMIs.\r
- ///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Platform Information Contains power management and other model\r
- specific features enumeration. See http://biosbits.org.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
- /// MHz.\r
- ///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
- ///\r
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
- /// Turbo mode is disabled.\r
- ///\r
- UINT32 RatioLimit:1;\r
- ///\r
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
- /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
- /// programmable.\r
- ///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
- UINT32 Reserved4:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
- /// minimum ratio (maximum efficiency) that the processor can operates, in\r
- /// units of 100MHz.\r
- ///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Core. C-State Configuration Control (R/W) Note: C-state values are\r
- processor specific C-state code names, unrelated to MWAIT extension C-state\r
- parameters or ACPI CStates. See http://biosbits.org.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
- /// processor-specific C-state code name (consuming the least power). for\r
- /// the package. The default is set as factory-configured package C-state\r
- /// limit. The following C-state code name encodings are supported: 000b:\r
- /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r
- /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
- /// This field cannot be used to limit package C-state to C3.\r
- ///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
- /// IO_read instructions sent to IO register specified by\r
- /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
- ///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
- /// until next reset.\r
- ///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
- ///\r
- /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
- /// will conditionally demote C6/C7 requests to C3 based on uncore\r
- /// auto-demote information.\r
- ///\r
- UINT32 C3AutoDemotion:1;\r
- ///\r
- /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
- /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
- /// auto-demote information.\r
- ///\r
- UINT32 C1AutoDemotion:1;\r
- ///\r
- /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
- /// demoted C3.\r
- ///\r
- UINT32 C3Undemotion:1;\r
- ///\r
- /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
- /// demoted C1.\r
- ///\r
- UINT32 C1Undemotion:1;\r
- UINT32 Reserved4:3;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Core. Power Management IO Redirection in C-state (R/W) See\r
- http://biosbits.org.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
- /// visible to software for IO redirection. If IO MWAIT Redirection is\r
- /// enabled, reads to this address will be consumed by the power\r
- /// management logic and decoded to MWAIT instructions. When IO port\r
- /// address redirection is enabled, this is the IO port address reported\r
- /// to the OS/software.\r
- ///\r
- UINT32 Lvl2Base:16;\r
- ///\r
- /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
- /// maximum C-State code name to be included when IO read to MWAIT\r
- /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r
- /// is the max C-State to include 001b - C6 is the max C-State to include\r
- /// 010b - C7 is the max C-State to include.\r
- ///\r
- UINT32 CStateRange:3;\r
- UINT32 Reserved1:13;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER;\r
-\r
-\r
-/**\r
- Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
- handler to handle unsuccessful read of this MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
- /// MSR, the configuration of AES instruction set availability is as\r
- /// follows: 11b: AES instructions are not available until next RESET.\r
- /// otherwise, AES instructions are available. Note, AES instruction set\r
- /// is not available if read is unsuccessful. If the configuration is not\r
- /// 01b, AES instruction can be mis-configured if a privileged agent\r
- /// unintentionally writes 11b.\r
- ///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER;\r
-\r
-\r
-/**\r
- Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.\r
- MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.\r
- MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.\r
- MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D\r
-/// @}\r
-\r
-\r
-/**\r
- Package.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- ///\r
- /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed\r
- /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).\r
- ///\r
- UINT32 CoreVoltage:16;\r
- UINT32 Reserved2:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was\r
- originally named IA32_THERM_CONTROL MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%\r
- /// increment.\r
- ///\r
- UINT32 OnDemandClockModulationDutyCycle:4;\r
- ///\r
- /// [Bit 4] On demand Clock Modulation Enable (R/W).\r
- ///\r
- UINT32 OnDemandClockModulationEnable:1;\r
- UINT32 Reserved1:27;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER;\r
-\r
-\r
-/**\r
- Enable Misc. Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r
- ///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:6;\r
- ///\r
- /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved3:3;\r
- ///\r
- /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved4:1;\r
- ///\r
- /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
- ///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved5:3;\r
- ///\r
- /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r
- ///\r
- UINT32 LimitCpuidMaxval:1;\r
- ///\r
- /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved6:8;\r
- UINT32 Reserved7:2;\r
- ///\r
- /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 XD:1;\r
- UINT32 Reserved8:3;\r
- ///\r
- /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
- /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
- /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
- /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
- /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
- /// the power-on default value is used by BIOS to detect hardware support\r
- /// of turbo mode. If power-on default value is 1, turbo mode is available\r
- /// in the processor. If power-on default value is 0, turbo mode is not\r
- /// available.\r
- ///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved9:25;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
- /// PROCHOT# will be asserted. The value is degree C.\r
- ///\r
- UINT32 TemperatureTarget:8;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
-\r
-\r
-/**\r
- Miscellaneous Feature Control (R/W).\r
-\r
- @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
- /// L2 hardware prefetcher, which fetches additional lines of code or data\r
- /// into the L2 cache.\r
- ///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- ///\r
- /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
- /// disables the adjacent cache line prefetcher, which fetches the cache\r
- /// line that comprises a cache line pair (128 bytes).\r
- ///\r
- UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
- ///\r
- /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
- /// the L1 data cache prefetcher, which fetches the next cache line into\r
- /// L1 data cache.\r
- ///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
- ///\r
- /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
- /// data cache IP prefetcher, which uses sequential load history (based on\r
- /// instruction Pointer of previous loads) to determine whether to\r
- /// prefetch additional lines.\r
- ///\r
- UINT32 DCUIPPrefetcherDisable:1;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Offcore Response Event Select Register (R/W).\r
-\r
- @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6\r
-\r
-\r
-/**\r
- Thread. Offcore Response Event Select Register (R/W).\r
-\r
- @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7\r
-\r
-\r
-/**\r
- See http://biosbits.org.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA\r
-\r
-\r
-/**\r
- Thread. Last Branch Record Filtering Select Register (R/W) See Section\r
- 17.9.2, "Filtering of Last Branch Records.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] CPL_EQ_0.\r
- ///\r
- UINT32 CPL_EQ_0:1;\r
- ///\r
- /// [Bit 1] CPL_NEQ_0.\r
- ///\r
- UINT32 CPL_NEQ_0:1;\r
- ///\r
- /// [Bit 2] JCC.\r
- ///\r
- UINT32 JCC:1;\r
- ///\r
- /// [Bit 3] NEAR_REL_CALL.\r
- ///\r
- UINT32 NEAR_REL_CALL:1;\r
- ///\r
- /// [Bit 4] NEAR_IND_CALL.\r
- ///\r
- UINT32 NEAR_IND_CALL:1;\r
- ///\r
- /// [Bit 5] NEAR_RET.\r
- ///\r
- UINT32 NEAR_RET:1;\r
- ///\r
- /// [Bit 6] NEAR_IND_JMP.\r
- ///\r
- UINT32 NEAR_IND_JMP:1;\r
- ///\r
- /// [Bit 7] NEAR_REL_JMP.\r
- ///\r
- UINT32 NEAR_REL_JMP:1;\r
- ///\r
- /// [Bit 8] FAR_BRANCH.\r
- ///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
- that points to the MSR containing the most recent branch record. See\r
- MSR_LASTBRANCH_0_FROM_IP (at 680H).\r
-\r
- @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
- last branch instruction that the processor executed prior to the last\r
- exception that was generated or the last interrupt that was handled.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD\r
-\r
-\r
-/**\r
- Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
- to the target of the last branch instruction that the processor executed\r
- prior to the last exception that was generated or the last interrupt that\r
- was handled.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE\r
-\r
-\r
-/**\r
- Core. See http://biosbits.org.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC\r
-\r
-\r
-/**\r
- Package. Always 0 (CMCI not supported).\r
-\r
- @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284\r
-\r
-\r
-/**\r
- See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Thread. Ovf_PMC0.\r
- ///\r
- UINT32 Ovf_PMC0:1;\r
- ///\r
- /// [Bit 1] Thread. Ovf_PMC1.\r
- ///\r
- UINT32 Ovf_PMC1:1;\r
- ///\r
- /// [Bit 2] Thread. Ovf_PMC2.\r
- ///\r
- UINT32 Ovf_PMC2:1;\r
- ///\r
- /// [Bit 3] Thread. Ovf_PMC3.\r
- ///\r
- UINT32 Ovf_PMC3:1;\r
- ///\r
- /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
- ///\r
- UINT32 Ovf_PMC4:1;\r
- ///\r
- /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
- ///\r
- UINT32 Ovf_PMC5:1;\r
- ///\r
- /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
- ///\r
- UINT32 Ovf_PMC6:1;\r
- ///\r
- /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
- ///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
- ///\r
- /// [Bit 32] Thread. Ovf_FixedCtr0.\r
- ///\r
- UINT32 Ovf_FixedCtr0:1;\r
- ///\r
- /// [Bit 33] Thread. Ovf_FixedCtr1.\r
- ///\r
- UINT32 Ovf_FixedCtr1:1;\r
- ///\r
- /// [Bit 34] Thread. Ovf_FixedCtr2.\r
- ///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:26;\r
- ///\r
- /// [Bit 61] Thread. Ovf_Uncore.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Thread. Ovf_BufDSSAVE.\r
- ///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- ///\r
- /// [Bit 63] Thread. CondChgd.\r
- ///\r
- UINT32 CondChgd:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
- Facilities.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Thread. Set 1 to enable PMC0 to count.\r
- ///\r
- UINT32 PCM0_EN:1;\r
- ///\r
- /// [Bit 1] Thread. Set 1 to enable PMC1 to count.\r
- ///\r
- UINT32 PCM1_EN:1;\r
- ///\r
- /// [Bit 2] Thread. Set 1 to enable PMC2 to count.\r
- ///\r
- UINT32 PCM2_EN:1;\r
- ///\r
- /// [Bit 3] Thread. Set 1 to enable PMC3 to count.\r
- ///\r
- UINT32 PCM3_EN:1;\r
- ///\r
- /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >\r
- /// 4).\r
- ///\r
- UINT32 PCM4_EN:1;\r
- ///\r
- /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >\r
- /// 5).\r
- ///\r
- UINT32 PCM5_EN:1;\r
- ///\r
- /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >\r
- /// 6).\r
- ///\r
- UINT32 PCM6_EN:1;\r
- ///\r
- /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >\r
- /// 7).\r
- ///\r
- UINT32 PCM7_EN:1;\r
- UINT32 Reserved1:24;\r
- ///\r
- /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.\r
- ///\r
- UINT32 FIXED_CTR0:1;\r
- ///\r
- /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.\r
- ///\r
- UINT32 FIXED_CTR1:1;\r
- ///\r
- /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.\r
- ///\r
- UINT32 FIXED_CTR2:1;\r
- UINT32 Reserved2:29;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
- ///\r
- UINT32 Ovf_PMC0:1;\r
- ///\r
- /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
- ///\r
- UINT32 Ovf_PMC1:1;\r
- ///\r
- /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
- ///\r
- UINT32 Ovf_PMC2:1;\r
- ///\r
- /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
- ///\r
- UINT32 Ovf_PMC3:1;\r
- ///\r
- /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
- ///\r
- UINT32 Ovf_PMC4:1;\r
- ///\r
- /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
- ///\r
- UINT32 Ovf_PMC5:1;\r
- ///\r
- /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
- ///\r
- UINT32 Ovf_PMC6:1;\r
- ///\r
- /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
- ///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
- ///\r
- /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
- ///\r
- UINT32 Ovf_FixedCtr0:1;\r
- ///\r
- /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
- ///\r
- UINT32 Ovf_FixedCtr1:1;\r
- ///\r
- /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
- ///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:26;\r
- ///\r
- /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
- ///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- ///\r
- /// [Bit 63] Thread. Set 1 to clear CondChgd.\r
- ///\r
- UINT32 CondChgd:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC0:1;\r
- ///\r
- /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC1:1;\r
- ///\r
- /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC2:1;\r
- ///\r
- /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
- ///\r
- UINT32 PEBS_EN_PMC3:1;\r
- UINT32 Reserved1:28;\r
- ///\r
- /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC0:1;\r
- ///\r
- /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC1:1;\r
- ///\r
- /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC2:1;\r
- ///\r
- /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
- ///\r
- UINT32 LL_EN_PMC3:1;\r
- UINT32 Reserved2:27;\r
- ///\r
- /// [Bit 63] Enable Precise Store. (R/W).\r
- ///\r
- UINT32 PS_EN:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r
- Facility.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
- /// that will be counted. (R/W).\r
- ///\r
- UINT32 MinimumThreshold:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C3 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C6 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C7 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA\r
-\r
-\r
-/**\r
- Core. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
- Residency Counter. (R/O) Value since last reset that this core is in\r
- processor-specific C3 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC\r
-\r
-\r
-/**\r
- Core. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
- Residency Counter. (R/O) Value since last reset that this core is in\r
- processor-specific C6 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD\r
-\r
-\r
-/**\r
- Core. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7\r
- Residency Counter. (R/O) Value since last reset that this core is in\r
- processor-specific C7 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU\r
- /// hardware detected errors.\r
- ///\r
- UINT32 PCUHardwareError:1;\r
- ///\r
- /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU\r
- /// controller detected errors.\r
- ///\r
- UINT32 PCUControllerError:1;\r
- ///\r
- /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU\r
- /// firmware detected errors.\r
- ///\r
- UINT32 PCUFirmwareError:1;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
-\r
-\r
-/**\r
- Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
- "RAPL Interfaces.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606\r
-\r
-\r
-/**\r
- Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r
- processor specific C-state code names, unrelated to MWAIT extension C-state\r
- parameters or ACPI CStates.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
- /// that should be used to decide if the package should be put into a\r
- /// package C3 state.\r
- ///\r
- UINT32 TimeLimit:10;\r
- ///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
- /// unit of the interrupt response time limit. The following time unit\r
- /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
- /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
- ///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
- /// valid and can be used by the processor for package C-sate management.\r
- ///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the\r
- budget allocated for the package to exit from C6 to a C0 state, where\r
- interrupt request can be delivered to the core and serviced. Additional\r
- core-exit latency amy be applicable depending on the actual C-state the core\r
- is in. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
- /// that should be used to decide if the package should be put into a\r
- /// package C6 state.\r
- ///\r
- UINT32 TimeLimit:10;\r
- ///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
- /// unit of the interrupt response time limit. The following time unit\r
- /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
- /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
- ///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
- /// valid and can be used by the processor for package C-sate management.\r
- ///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C2 states. Count at the same frequency as the TSC.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D\r
-\r
-\r
-/**\r
- Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610\r
-\r
-\r
-/**\r
- Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611\r
-\r
-\r
-/**\r
- Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
- Domain.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614\r
-\r
-\r
-/**\r
- Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
- RAPL Domains.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638\r
-\r
-\r
-/**\r
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
-\r
-\r
-/**\r
- Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
- branch record registers on the last branch record stack. This part of the\r
- stack contains pointers to the source instruction. See also: - Last Branch\r
- Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section\r
- 17.4.8.1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F\r
-/// @}\r
-\r
-\r
-/**\r
- Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
- MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
- /// limit of 1 core active.\r
- ///\r
- UINT32 Maximum1C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
- /// limit of 2 core active.\r
- ///\r
- UINT32 Maximum2C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
- /// limit of 3 core active.\r
- ///\r
- UINT32 Maximum3C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
- /// limit of 4 core active.\r
- ///\r
- UINT32 Maximum4C:8;\r
- ///\r
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
- /// limit of 5 core active.\r
- ///\r
- UINT32 Maximum5C:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
- /// limit of 6 core active.\r
- ///\r
- UINT32 Maximum6C:8;\r
- ///\r
- /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
- /// limit of 7 core active.\r
- ///\r
- UINT32 Maximum7C:8;\r
- ///\r
- /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
- /// limit of 8 core active.\r
- ///\r
- UINT32 Maximum8C:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore PMU global control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Slice 0 select.\r
- ///\r
- UINT32 PMI_Sel_Slice0:1;\r
- ///\r
- /// [Bit 1] Slice 1 select.\r
- ///\r
- UINT32 PMI_Sel_Slice1:1;\r
- ///\r
- /// [Bit 2] Slice 2 select.\r
- ///\r
- UINT32 PMI_Sel_Slice2:1;\r
- ///\r
- /// [Bit 3] Slice 3 select.\r
- ///\r
- UINT32 PMI_Sel_Slice3:1;\r
- ///\r
- /// [Bit 4] Slice 4 select.\r
- ///\r
- UINT32 PMI_Sel_Slice4:1;\r
- UINT32 Reserved1:14;\r
- UINT32 Reserved2:10;\r
- ///\r
- /// [Bit 29] Enable all uncore counters.\r
- ///\r
- UINT32 EN:1;\r
- ///\r
- /// [Bit 30] Enable wake on PMI.\r
- ///\r
- UINT32 WakePMI:1;\r
- ///\r
- /// [Bit 31] Enable Freezing counter when overflow.\r
- ///\r
- UINT32 FREEZE:1;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore PMU main status.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Fixed counter overflowed.\r
- ///\r
- UINT32 Fixed:1;\r
- ///\r
- /// [Bit 1] An ARB counter overflowed.\r
- ///\r
- UINT32 ARB:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 3] A CBox counter overflowed (on any slice).\r
- ///\r
- UINT32 CBox:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore fixed counter control (R/W).\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:20;\r
- ///\r
- /// [Bit 20] Enable overflow propagation.\r
- ///\r
- UINT32 EnableOverflow:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 22] Enable counting.\r
- ///\r
- UINT32 EnableCounting:1;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore fixed counter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Current count.\r
- ///\r
- UINT32 CurrentCount:32;\r
- ///\r
- /// [Bits 47:32] Current count.\r
- ///\r
- UINT32 CurrentCountHi:16;\r
- UINT32 Reserved:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore C-Box configuration information (R/O).\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Report the number of C-Box units with performance counters,\r
- /// including processor cores and processor graphics".\r
- ///\r
- UINT32 CBox:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, performance counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, performance counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, counter 0 event select MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, counter 1 event select MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
-\r
-\r
-/**\r
- Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the\r
- budget allocated for the package to exit from C7 to a C0 state, where\r
- interrupt request can be delivered to the core and serviced. Additional\r
- core-exit latency amy be applicable depending on the actual C-state the core\r
- is in. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
- /// that should be used to decide if the package should be put into a\r
- /// package C7 state.\r
- ///\r
- UINT32 TimeLimit:10;\r
- ///\r
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
- /// unit of the interrupt response time limit. The following time unit\r
- /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
- /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
- ///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
- /// valid and can be used by the processor for package C-sate management.\r
- ///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A\r
-\r
-\r
-/**\r
- Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
- RAPL Domains.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640\r
-\r
-\r
-/**\r
- Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641\r
-\r
-\r
-/**\r
- Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, counter n event select MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-Box n, unit status for counter 0-3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, performance counter n.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, counter n event select MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, performance counter n.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, counter n event select MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, performance counter n.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 3, counter n event select MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 3, performance counter n.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 4, counter n event select MSR.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 4, performance counter n.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.\r
- MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.\r
- @{\r
-**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749\r
-/// @}\r
-\r
-\r
-/**\r
- Package. MC Bank Error Configuration (R/W).\r
-\r
- @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
- /// to log additional info in bits 36:32.\r
- ///\r
- UINT32 MemErrorLogEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Package.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS\r
- /// counting logic for specific events requiring additional configuration,\r
- /// see Table 19-17.\r
- ///\r
- UINT32 ENABLE_PEBS_NUM_ALT:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Package RAPL Perf Status (R/O).\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
- Domain.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
-\r
-\r
-/**\r
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
-\r
-\r
-/**\r
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
-\r
-\r
-/**\r
- Package. Uncore U-box UCLK fixed counter control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08\r
-\r
-\r
-/**\r
- Package. Uncore U-box UCLK fixed counter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon event select for U-box counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon event select for U-box counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16\r
-\r
-\r
-/**\r
- Package. Uncore U-box perfmon counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon for PCU-box-wide control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon event select for PCU counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon event select for PCU counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon event select for PCU counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon event select for PCU counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon box-wide filter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38\r
-\r
-\r
-/**\r
- Package. Uncore PCU perfmon counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon local box wide control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon box wide filter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18\r
-\r
-\r
-/**\r
- Package. Uncore C-box 0 perfmon counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon local box wide control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon box wide filter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38\r
-\r
-\r
-/**\r
- Package. Uncore C-box 1 perfmon counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon local box wide control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon box wide filter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58\r
-\r
-\r
-/**\r
- Package. Uncore C-box 2 perfmon counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon local box wide control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon box wide filter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78\r
-\r
-\r
-/**\r
- Package. Uncore C-box 3 perfmon counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon local box wide control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon box wide filter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98\r
-\r
-\r
-/**\r
- Package. Uncore C-box 4 perfmon counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon local box wide control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon box wide filter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 5 perfmon counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon local box wide control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon box wide filter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 6 perfmon counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon local box wide control.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon box wide filter.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter 0.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter 1.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter 2.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8\r
-\r
-\r
-/**\r
- Package. Uncore C-box 7 perfmon counter 3.\r
-\r
- @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);\r
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);\r
- @endcode\r
- @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
-**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel processors based on the Silvermont microarchitecture.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __SILVERMONT_MSR_H__\r
-#define __SILVERMONT_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel processors based on the Silvermont microarchitecture?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x37 || \\r
- DisplayModel == 0x4A || \\r
- DisplayModel == 0x4D || \\r
- DisplayModel == 0x5A || \\r
- DisplayModel == 0x5D \\r
- ) \\r
- )\r
-\r
-/**\r
- Module. Model Specific Platform ID (R).\r
-\r
- @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);\r
- @endcode\r
- @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
-**/\r
-#define MSR_SILVERMONT_PLATFORM_ID 0x00000017\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
- ///\r
- UINT32 MaximumQualifiedRatio:5;\r
- UINT32 Reserved2:19;\r
- UINT32 Reserved3:18;\r
- ///\r
- /// [Bits 52:50] See Table 2-2.\r
- ///\r
- UINT32 PlatformId:3;\r
- UINT32 Reserved4:11;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_PLATFORM_ID_REGISTER;\r
-\r
-\r
-/**\r
- Module. Processor Hard Power-On Configuration (R/W) Writes ignored.\r
-\r
- @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);\r
- AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
-**/\r
-#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;\r
-\r
-\r
-/**\r
- Core. SMI Counter (R/O).\r
-\r
- @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_SMI_COUNT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);\r
- @endcode\r
- @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
-**/\r
-#define MSR_SILVERMONT_SMI_COUNT 0x00000034\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r
- /// RESET.\r
- ///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_SMI_COUNT_REGISTER;\r
-\r
-\r
-/**\r
- Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.\r
-\r
- @param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type\r
- MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type\r
- MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Lock (R/WL).\r
- ///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 2] Enable VMX outside SMX operation (R/WL).\r
- ///\r
- UINT32 EnableVmxOutsideSmx:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
- record registers on the last branch record stack. The From_IP part of the\r
- stack contains pointers to the source instruction. See also: - Last Branch\r
- Record Stack TOS at 1C9H - Section 17.5 and record format in Section\r
- 17.4.8.1.\r
-\r
- @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);\r
- AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040\r
-#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041\r
-#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042\r
-#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043\r
-#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044\r
-#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045\r
-#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046\r
-#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047\r
-/// @}\r
-\r
-\r
-/**\r
- Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
- record registers on the last branch record stack. The To_IP part of the\r
- stack contains pointers to the destination instruction.\r
-\r
- @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);\r
- AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
- MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060\r
-#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061\r
-#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062\r
-#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063\r
-#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064\r
-#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065\r
-#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066\r
-#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067\r
-/// @}\r
-\r
-\r
-/**\r
- Module. Scalable Bus Speed(RO) This field indicates the intended scalable\r
- bus clock speed for processors based on Silvermont microarchitecture:.\r
-\r
- @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_FSB_FREQ_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);\r
- @endcode\r
- @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
-**/\r
-#define MSR_SILVERMONT_FSB_FREQ 0x000000CD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Scalable Bus Speed\r
- ///\r
- /// Silvermont Processor Family\r
- /// ---------------------------\r
- /// 100B: 080.0 MHz\r
- /// 000B: 083.3 MHz\r
- /// 001B: 100.0 MHz\r
- /// 010B: 133.3 MHz\r
- /// 011B: 116.7 MHz\r
- ///\r
- /// Airmont Processor Family\r
- /// ---------------------------\r
- /// 0000B: 083.3 MHz\r
- /// 0001B: 100.0 MHz\r
- /// 0010B: 133.3 MHz\r
- /// 0011B: 116.7 MHz\r
- /// 0100B: 080.0 MHz\r
- /// 0101B: 093.3 MHz\r
- /// 0110B: 090.0 MHz\r
- /// 0111B: 088.9 MHz\r
- /// 1000B: 087.5 MHz\r
- ///\r
- UINT32 ScalableBusSpeed:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_FSB_FREQ_REGISTER;\r
-\r
-\r
-/**\r
- Package. Platform Information: Contains power management and other model\r
- specific features enumeration. See http://biosbits.org.\r
-\r
- @param ECX MSR_SILVERMONT_PLATFORM_INFO (0x000000CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_PLATFORM_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);\r
- AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio\r
- /// of the maximum frequency that does not require turbo. Frequency =\r
- /// ratio * Scalable Bus Frequency.\r
- ///\r
- UINT32 MaximumNon_TurboRatio:8;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;\r
-\r
-/**\r
- Module. C-State Configuration Control (R/W) Note: C-state values are\r
- processor specific C-state code names, unrelated to MWAIT extension C-state\r
- parameters or ACPI CStates. See http://biosbits.org.\r
-\r
- @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
-**/\r
-#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
- /// processor-specific C-state code name (consuming the least power). for\r
- /// the package. The default is set as factory-configured package C-state\r
- /// limit. The following C-state code name encodings are supported: 000b:\r
- /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r
- /// 100b: C4 110b: C6 111b: C7 (Silvermont only).\r
- ///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
- /// IO_read instructions sent to IO register specified by\r
- /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
- ///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
- /// until next reset.\r
- ///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:16;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Module. Power Management IO Redirection in C-state (R/W) See\r
- http://biosbits.org.\r
-\r
- @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);\r
- AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
-**/\r
-#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
- /// visible to software for IO redirection. If IO MWAIT Redirection is\r
- /// enabled, reads to this address will be consumed by the power\r
- /// management logic and decoded to MWAIT instructions. When IO port\r
- /// address redirection is enabled, this is the IO port address reported\r
- /// to the OS/software.\r
- ///\r
- UINT32 Lvl2Base:16;\r
- ///\r
- /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
- /// maximum C-State code name to be included when IO read to MWAIT\r
- /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4\r
- /// is the max C-State to include 110b - C6 is the max C-State to include\r
- /// 111b - C7 is the max C-State to include.\r
- ///\r
- UINT32 CStateRange:3;\r
- UINT32 Reserved1:13;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;\r
-\r
-\r
-/**\r
- Module.\r
-\r
- @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);\r
- AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
-**/\r
-#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
- /// Indicates if the L2 is hardware-disabled.\r
- ///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r
- /// Disabled (default) Until this bit is set the processor will not\r
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
- ///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved2:14;\r
- ///\r
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
- ///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved3:8;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;\r
-\r
-\r
-/**\r
- Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
- handler to handle unsuccessful read of this MSR.\r
-\r
- @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);\r
- AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
-**/\r
-#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
- /// MSR, the configuration of AES instruction set availability is as\r
- /// follows: 11b: AES instructions are not available until next RESET.\r
- /// otherwise, AES instructions are available. Note, AES instruction set\r
- /// is not available if read is unsuccessful. If the configuration is not\r
- /// 01b, AES instruction can be mis-configured if a privileged agent\r
- /// unintentionally writes 11b.\r
- ///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;\r
-\r
-\r
-/**\r
- Enable Misc. Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r
- ///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 2-2. Default value is 0.\r
- ///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
- ///\r
- /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
- ///\r
- /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
- /// Table 2-2.\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
- ///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
- ///\r
- /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r
- ///\r
- UINT32 LimitCpuidMaxval:1;\r
- ///\r
- /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r
- ///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
- ///\r
- /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors\r
- /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
- /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
- /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
- /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
- /// the power-on default value is used by BIOS to detect hardware support\r
- /// of turbo mode. If power-on default value is 1, turbo mode is available\r
- /// in the processor. If power-on default value is 0, turbo mode is not\r
- /// available.\r
- ///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Package.\r
-\r
- @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);\r
- AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
-**/\r
-#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bits 23:16] Temperature Target (R) The default thermal throttling or\r
- /// PROCHOT# activation temperature in degree C, The effective temperature\r
- /// for thermal throttling or PROCHOT# activation is "Temperature Target"\r
- /// + "Target Offset".\r
- ///\r
- UINT32 TemperatureTarget:8;\r
- ///\r
- /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to\r
- /// adjust the throttling and PROCHOT# activation temperature from the\r
- /// default target specified in TEMPERATURE_TARGET (bits 23:16).\r
- ///\r
- UINT32 TargetOffset:6;\r
- UINT32 Reserved2:2;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;\r
-\r
-\r
-/**\r
- Miscellaneous Feature Control (R/W).\r
-\r
- @param ECX MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
- /// L2 hardware prefetcher, which fetches additional lines of code or data\r
- /// into the L2 cache.\r
- ///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
- /// the L1 data cache prefetcher, which fetches the next cache line into\r
- /// L1 data cache.\r
- ///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Module. Offcore Response Event Select Register (R/W).\r
-\r
- @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);\r
- AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
-**/\r
-#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6\r
-\r
-\r
-/**\r
- Module. Offcore Response Event Select Register (R/W).\r
-\r
- @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);\r
- AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
-**/\r
-#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode (RW).\r
-\r
- @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);\r
- AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
- /// limit of 1 core active.\r
- ///\r
- UINT32 Maximum1C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
- /// limit of 2 core active.\r
- ///\r
- UINT32 Maximum2C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
- /// limit of 3 core active.\r
- ///\r
- UINT32 Maximum3C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
- /// limit of 4 core active.\r
- ///\r
- UINT32 Maximum4C:8;\r
- ///\r
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
- /// limit of 5 core active.\r
- ///\r
- UINT32 Maximum5C:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
- /// limit of 6 core active.\r
- ///\r
- UINT32 Maximum6C:8;\r
- ///\r
- /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
- /// limit of 7 core active.\r
- ///\r
- UINT32 Maximum7C:8;\r
- ///\r
- /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
- /// limit of 8 core active.\r
- ///\r
- UINT32 Maximum8C:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
- "Filtering of Last Branch Records.".\r
-\r
- @param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_LBR_SELECT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT);\r
- AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
-**/\r
-#define MSR_SILVERMONT_LBR_SELECT 0x000001C8\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] CPL_EQ_0.\r
- ///\r
- UINT32 CPL_EQ_0:1;\r
- ///\r
- /// [Bit 1] CPL_NEQ_0.\r
- ///\r
- UINT32 CPL_NEQ_0:1;\r
- ///\r
- /// [Bit 2] JCC.\r
- ///\r
- UINT32 JCC:1;\r
- ///\r
- /// [Bit 3] NEAR_REL_CALL.\r
- ///\r
- UINT32 NEAR_REL_CALL:1;\r
- ///\r
- /// [Bit 4] NEAR_IND_CALL.\r
- ///\r
- UINT32 NEAR_IND_CALL:1;\r
- ///\r
- /// [Bit 5] NEAR_RET.\r
- ///\r
- UINT32 NEAR_RET:1;\r
- ///\r
- /// [Bit 6] NEAR_IND_JMP.\r
- ///\r
- UINT32 NEAR_IND_JMP:1;\r
- ///\r
- /// [Bit 7] NEAR_REL_JMP.\r
- ///\r
- UINT32 NEAR_REL_JMP:1;\r
- ///\r
- /// [Bit 8] FAR_BRANCH.\r
- ///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_LBR_SELECT_REGISTER;\r
-\r
-\r
-/**\r
- Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that\r
- points to the MSR containing the most recent branch record. See\r
- MSR_LASTBRANCH_0_FROM_IP.\r
-\r
- @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Core. Last Exception Record From Linear IP (R) Contains a pointer to the\r
- last branch instruction that the processor executed prior to the last\r
- exception that was generated or the last interrupt that was handled.\r
-\r
- @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);\r
- @endcode\r
- @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
-**/\r
-#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD\r
-\r
-\r
-/**\r
- Core. Last Exception Record To Linear IP (R) This area contains a pointer\r
- to the target of the last branch instruction that the processor executed\r
- prior to the last exception that was generated or the last interrupt that\r
- was handled.\r
-\r
- @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);\r
- @endcode\r
- @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
-**/\r
-#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE\r
-\r
-\r
-/**\r
- Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
- (PEBS).".\r
-\r
- @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
-**/\r
-#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).\r
- ///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_PEBS_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
- Residency Counter. (R/O) Value since last reset that this package is in\r
- processor-specific C6 states. Counts at the TSC Frequency.\r
-\r
- @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA\r
-\r
-\r
-/**\r
- Core. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
- Residency Counter. (R/O) Value since last reset that this core is in\r
- processor-specific C6 states. Counts at the TSC Frequency.\r
-\r
- @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r
-\r
-\r
-/**\r
- Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
-\r
- @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);\r
- @endcode\r
- @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
-**/\r
-#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
-\r
-\r
-/**\r
- Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r
- 2-2.\r
-\r
- @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);\r
- @endcode\r
- @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
-**/\r
-#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491\r
-\r
-\r
-/**\r
- Core. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1\r
- Residency Counter. (R/O) Value since last reset that this core is in\r
- processor-specific C1 states. Counts at the TSC frequency.\r
-\r
- @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);\r
- AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660\r
-\r
-\r
-/**\r
- Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
- "RAPL Interfaces.".\r
-\r
- @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);\r
- @endcode\r
- @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
-**/\r
-#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Power Units. Power related information (in milliWatts) is\r
- /// based on the multiplier, 2^PU; where PU is an unsigned integer\r
- /// represented by bits 3:0. Default value is 0101b, indicating power unit\r
- /// is in 32 milliWatts increment.\r
- ///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 12:8] Energy Status Units. Energy related information (in\r
- /// microJoules) is based on the multiplier, 2^ESU; where ESU is an\r
- /// unsigned integer represented by bits 12:8. Default value is 00101b,\r
- /// indicating energy unit is in 32 microJoules increment.\r
- ///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in\r
- /// one second.\r
- ///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. PKG RAPL Power Limit Control (R/W).\r
-\r
- @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package\r
- /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.\r
- ///\r
- UINT32 Limit:15;\r
- ///\r
- /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package\r
- /// RAPL Domain.".\r
- ///\r
- UINT32 Enable:1;\r
- ///\r
- /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,\r
- /// "Package RAPL Domain.".\r
- ///\r
- UINT32 ClampingLimit:1;\r
- ///\r
- /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.\r
- /// If 0 is specified in bits [23:17], defaults to 1 second window.\r
- ///\r
- UINT32 Time:7;\r
- UINT32 Reserved1:8;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."\r
- and MSR_RAPL_POWER_UNIT in Table 2-8.\r
-\r
- @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611\r
-\r
-\r
-/**\r
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."\r
- and MSR_RAPL_POWER_UNIT in Table 2-8.\r
-\r
- @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639\r
-\r
-\r
-/**\r
- Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion\r
- policy. Writing a value of 0 disables core level HW demotion policy.\r
-\r
- @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);\r
- AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.\r
-**/\r
-#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668\r
-\r
-\r
-/**\r
- Package. Module C6 demotion policy config MSR. Controls module (i.e. two\r
- cores sharing the second-level cache) C6 demotion policy. Writing a value of\r
- 0 disables module level HW demotion policy.\r
-\r
- @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);\r
- AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);\r
- @endcode\r
- @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.\r
-**/\r
-#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669\r
-\r
-\r
-/**\r
- Module. Module C6 Residency Counter (R/0) Note: C-state values are processor\r
- specific C-state code names, unrelated to MWAIT extension C-state parameters\r
- or ACPI CStates. Time that this module is in module-specific C6 states since\r
- last reset. Counts at 1 Mhz frequency.\r
-\r
- @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);\r
- @endcode\r
- @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.\r
-**/\r
-#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664\r
-\r
-\r
-/**\r
- Package. PKG RAPL Parameter (R/0).\r
-\r
- @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);\r
- @endcode\r
- @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
-**/\r
-#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is\r
- /// the equivalent of thermal specification power of the package domain.\r
- /// The unit of this field is specified by the "Power Units" field of\r
- /// MSR_RAPL_POWER_UNIT.\r
- ///\r
- UINT32 ThermalSpecPower:15;\r
- UINT32 Reserved1:17;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Package. PP0 RAPL Power Limit Control (R/W).\r
-\r
- @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);\r
- @endcode\r
- @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
- /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.\r
- ///\r
- UINT32 Limit:15;\r
- ///\r
- /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
- /// RAPL Domains.".\r
- ///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time\r
- /// duration over which the average power must remain below\r
- /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time\r
- /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time\r
- /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.\r
- /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35\r
- /// second time duration. 0x8: 40 second time duration. 0x9: 45 second\r
- /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.\r
- ///\r
- UINT32 Time:7;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Defintions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __SKYLAKE_MSR_H__\r
-#define __SKYLAKE_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel processors based on the Skylake microarchitecture?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x4E || \\r
- DisplayModel == 0x5E || \\r
- DisplayModel == 0x55 || \\r
- DisplayModel == 0x8E || \\r
- DisplayModel == 0x9E || \\r
- DisplayModel == 0x66 \\r
- ) \\r
- )\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);\r
- @endcode\r
- @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
- /// limit of 1 core active.\r
- ///\r
- UINT32 Maximum1C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
- /// limit of 2 core active.\r
- ///\r
- UINT32 Maximum2C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
- /// limit of 3 core active.\r
- ///\r
- UINT32 Maximum3C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
- /// limit of 4 core active.\r
- ///\r
- UINT32 Maximum4C:8;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)\r
- that points to the MSR containing the most recent branch record.\r
-\r
- @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Core. Power Control Register See http://biosbits.org.\r
-\r
- @param ECX MSR_SKYLAKE_POWER_CTL (0x000001FC)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_POWER_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);\r
- AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_POWER_CTL 0x000001FC\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU\r
- /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating\r
- /// point when all execution cores enter MWAIT (C1).\r
- ///\r
- UINT32 C1EEnable:1;\r
- UINT32 Reserved2:17;\r
- ///\r
- /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit\r
- /// disables the Race to Halt optimization and avoids this optimization\r
- /// limitation to execute below the most efficient frequency ratio.\r
- /// Default value is 0 for processors that support Race to Halt\r
- /// optimization. Default value is 1 for processors that do not support\r
- /// Race to Halt optimization.\r
- ///\r
- UINT32 Fix_Me_1:1;\r
- ///\r
- /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit\r
- /// disables the P-States energy efficiency optimization. Default value is\r
- /// 0. Disable/enable the energy efficiency optimization in P-State legacy\r
- /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the\r
- /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP\r
- /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS\r
- /// desired or OS maximize to the OS minimize performance setting.\r
- ///\r
- UINT32 DisableEnergyEfficiencyOptimization:1;\r
- UINT32 Reserved3:11;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_POWER_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
- CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
- the package. Lower 64 bits of an 128-bit external entropy value for key\r
- derivation of an enclave.\r
-\r
- @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = 0;\r
- AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300\r
-\r
-//\r
-// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.\r
-//\r
-#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0\r
-/**\r
- Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
- CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
- the package. Upper 64 bits of an 128-bit external entropy value for key\r
- derivation of an enclave.\r
-\r
- @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = 0;\r
- AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301\r
-\r
-//\r
-// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.\r
-//\r
-#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1\r
-\r
-\r
-/**\r
- See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
- Version 4.".\r
-\r
- @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Thread. Ovf_PMC0.\r
- ///\r
- UINT32 Ovf_PMC0:1;\r
- ///\r
- /// [Bit 1] Thread. Ovf_PMC1.\r
- ///\r
- UINT32 Ovf_PMC1:1;\r
- ///\r
- /// [Bit 2] Thread. Ovf_PMC2.\r
- ///\r
- UINT32 Ovf_PMC2:1;\r
- ///\r
- /// [Bit 3] Thread. Ovf_PMC3.\r
- ///\r
- UINT32 Ovf_PMC3:1;\r
- ///\r
- /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
- ///\r
- UINT32 Ovf_PMC4:1;\r
- ///\r
- /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
- ///\r
- UINT32 Ovf_PMC5:1;\r
- ///\r
- /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
- ///\r
- UINT32 Ovf_PMC6:1;\r
- ///\r
- /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
- ///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
- ///\r
- /// [Bit 32] Thread. Ovf_FixedCtr0.\r
- ///\r
- UINT32 Ovf_FixedCtr0:1;\r
- ///\r
- /// [Bit 33] Thread. Ovf_FixedCtr1.\r
- ///\r
- UINT32 Ovf_FixedCtr1:1;\r
- ///\r
- /// [Bit 34] Thread. Ovf_FixedCtr2.\r
- ///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
- ///\r
- /// [Bit 55] Thread. Trace_ToPA_PMI.\r
- ///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 58] Thread. LBR_Frz.\r
- ///\r
- UINT32 LBR_Frz:1;\r
- ///\r
- /// [Bit 59] Thread. CTR_Frz.\r
- ///\r
- UINT32 CTR_Frz:1;\r
- ///\r
- /// [Bit 60] Thread. ASCI.\r
- ///\r
- UINT32 ASCI:1;\r
- ///\r
- /// [Bit 61] Thread. Ovf_Uncore.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Thread. Ovf_BufDSSAVE.\r
- ///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- ///\r
- /// [Bit 63] Thread. CondChgd.\r
- ///\r
- UINT32 CondChgd:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
- Version 4.".\r
-\r
- @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);\r
- AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
-**/\r
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
- ///\r
- UINT32 Ovf_PMC0:1;\r
- ///\r
- /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
- ///\r
- UINT32 Ovf_PMC1:1;\r
- ///\r
- /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
- ///\r
- UINT32 Ovf_PMC2:1;\r
- ///\r
- /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
- ///\r
- UINT32 Ovf_PMC3:1;\r
- ///\r
- /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
- ///\r
- UINT32 Ovf_PMC4:1;\r
- ///\r
- /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
- ///\r
- UINT32 Ovf_PMC5:1;\r
- ///\r
- /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
- ///\r
- UINT32 Ovf_PMC6:1;\r
- ///\r
- /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
- ///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
- ///\r
- /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
- ///\r
- UINT32 Ovf_FixedCtr0:1;\r
- ///\r
- /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
- ///\r
- UINT32 Ovf_FixedCtr1:1;\r
- ///\r
- /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
- ///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
- ///\r
- /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.\r
- ///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 58] Thread. Set 1 to clear LBR_Frz.\r
- ///\r
- UINT32 LBR_Frz:1;\r
- ///\r
- /// [Bit 59] Thread. Set 1 to clear CTR_Frz.\r
- ///\r
- UINT32 CTR_Frz:1;\r
- ///\r
- /// [Bit 60] Thread. Set 1 to clear ASCI.\r
- ///\r
- UINT32 ASCI:1;\r
- ///\r
- /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
- ///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- ///\r
- /// [Bit 63] Thread. Set 1 to clear CondChgd.\r
- ///\r
- UINT32 CondChgd:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
-\r
-\r
-/**\r
- See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
- Version 4.".\r
-\r
- @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);\r
- AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
-**/\r
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.\r
- ///\r
- UINT32 Ovf_PMC0:1;\r
- ///\r
- /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.\r
- ///\r
- UINT32 Ovf_PMC1:1;\r
- ///\r
- /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.\r
- ///\r
- UINT32 Ovf_PMC2:1;\r
- ///\r
- /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.\r
- ///\r
- UINT32 Ovf_PMC3:1;\r
- ///\r
- /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).\r
- ///\r
- UINT32 Ovf_PMC4:1;\r
- ///\r
- /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).\r
- ///\r
- UINT32 Ovf_PMC5:1;\r
- ///\r
- /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).\r
- ///\r
- UINT32 Ovf_PMC6:1;\r
- ///\r
- /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).\r
- ///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
- ///\r
- /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.\r
- ///\r
- UINT32 Ovf_FixedCtr0:1;\r
- ///\r
- /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.\r
- ///\r
- UINT32 Ovf_FixedCtr1:1;\r
- ///\r
- /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.\r
- ///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
- ///\r
- /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.\r
- ///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.\r
- ///\r
- UINT32 LBR_Frz:1;\r
- ///\r
- /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.\r
- ///\r
- UINT32 CTR_Frz:1;\r
- ///\r
- /// [Bit 60] Thread. Set 1 to cause ASCI = 1.\r
- ///\r
- UINT32 ASCI:1;\r
- ///\r
- /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.\r
- ///\r
- UINT32 Ovf_Uncore:1;\r
- ///\r
- /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.\r
- ///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- UINT32 Reserved4:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
-\r
-\r
-/**\r
- Thread. FrontEnd Precise Event Condition Select (R/W).\r
-\r
- @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);\r
- AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.\r
-**/\r
-#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Event Code Select.\r
- ///\r
- UINT32 EventCodeSelect:3;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 4] Event Code Select High.\r
- ///\r
- UINT32 EventCodeSelectHigh:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bits 19:8] IDQ_Bubble_Length Specifier.\r
- ///\r
- UINT32 IDQ_Bubble_Length:12;\r
- ///\r
- /// [Bits 22:20] IDQ_Bubble_Width Specifier.\r
- ///\r
- UINT32 IDQ_Bubble_Width:3;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;\r
-\r
-\r
-/**\r
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
-\r
-\r
-/**\r
- Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both\r
- platform vendor hardware implementation and BIOS enablement support it. This\r
- MSR will read 0 if not valid.\r
-\r
- @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);\r
- @endcode\r
- @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.\r
-**/\r
-#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Total energy consumed by all devices in the platform that\r
- /// receive power from integrated power delivery mechanism, Included\r
- /// platform devices are processor cores, SOC, memory, add-on or\r
- /// peripheral devices that get powered directly from the platform power\r
- /// delivery means. The energy units are specified in the\r
- /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.\r
- ///\r
- UINT32 TotalEnergy:32;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Productive Performance Count. (R/O). Hardware's view of workload\r
- scalability. See Section 14.4.5.1.\r
-\r
- @param ECX MSR_SKYLAKE_PPERF (0x0000064E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);\r
- @endcode\r
- @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.\r
-**/\r
-#define MSR_SKYLAKE_PPERF 0x0000064E\r
-\r
-\r
-/**\r
- Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
- refers to processor core frequency).\r
-\r
- @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);\r
- AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
-**/\r
-#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to assertion of external PROCHOT.\r
- ///\r
- UINT32 PROCHOT_Status:1;\r
- ///\r
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to a thermal event.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to residency state\r
- /// regulation limit.\r
- ///\r
- UINT32 ResidencyStateRegulationStatus:1;\r
- ///\r
- /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
- /// is reduced below the operating system request due to Running Average\r
- /// Thermal Limit (RATL).\r
- ///\r
- UINT32 RunningAverageThermalLimitStatus:1;\r
- ///\r
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to a thermal alert from a\r
- /// processor Voltage Regulator (VR).\r
- ///\r
- UINT32 VRThermAlertStatus:1;\r
- ///\r
- /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to VR thermal design\r
- /// current limit.\r
- ///\r
- UINT32 VRThermDesignCurrentStatus:1;\r
- ///\r
- /// [Bit 8] Other Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to electrical or other constraints.\r
- ///\r
- UINT32 OtherStatus:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
- /// set, frequency is reduced below the operating system request due to\r
- /// package/platform-level power limiting PL1.\r
- ///\r
- UINT32 PL1Status:1;\r
- ///\r
- /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
- /// set, frequency is reduced below the operating system request due to\r
- /// package/platform-level power limiting PL2/PL3.\r
- ///\r
- UINT32 PL2Status:1;\r
- ///\r
- /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to multi-core turbo limits.\r
- ///\r
- UINT32 MaxTurboLimitStatus:1;\r
- ///\r
- /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
- /// is reduced below the operating system request due to Turbo transition\r
- /// attenuation. This prevents performance degradation due to frequent\r
- /// operating ratio changes.\r
- ///\r
- UINT32 TurboTransitionAttenuationStatus:1;\r
- UINT32 Reserved3:2;\r
- ///\r
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PROCHOT_Log:1;\r
- ///\r
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:2;\r
- ///\r
- /// [Bit 20] Residency State Regulation Log When set, indicates that the\r
- /// Residency State Regulation Status bit has asserted since the log bit\r
- /// was last cleared. This log bit will remain set until cleared by\r
- /// software writing 0.\r
- ///\r
- UINT32 ResidencyStateRegulationLog:1;\r
- ///\r
- /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
- /// the RATL Status bit has asserted since the log bit was last cleared.\r
- /// This log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 RunningAverageThermalLimitLog:1;\r
- ///\r
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
- /// Alert Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 VRThermAlertLog:1;\r
- ///\r
- /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
- /// VR TDC Status bit has asserted since the log bit was last cleared.\r
- /// This log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 VRThermalDesignCurrentLog:1;\r
- ///\r
- /// [Bit 24] Other Log When set, indicates that the Other Status bit has\r
- /// asserted since the log bit was last cleared. This log bit will remain\r
- /// set until cleared by software writing 0.\r
- ///\r
- UINT32 OtherLog:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
- /// indicates that the Package or Platform Level PL1 Power Limiting Status\r
- /// bit has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PL1Log:1;\r
- ///\r
- /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
- /// indicates that the Package or Platform Level PL2/PL3 Power Limiting\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PL2Log:1;\r
- ///\r
- /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
- /// Limit Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 MaxTurboLimitLog:1;\r
- ///\r
- /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
- /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
- /// was last cleared. This log bit will remain set until cleared by\r
- /// software writing 0.\r
- ///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved6:2;\r
- UINT32 Reserved7:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;\r
-\r
-\r
-/**\r
- Package. HDC Configuration (R/W)..\r
-\r
- @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);\r
- AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.\r
-**/\r
-#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for\r
- /// MSR_PKG_HDC_DEEP_RESIDENCY.\r
- ///\r
- UINT32 PKG_Cx_Monitor:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;\r
-\r
-\r
-/**\r
- Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.\r
-\r
- @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);\r
- @endcode\r
- @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653\r
-\r
-\r
-/**\r
- Package. Accumulate the cycles the package was in C2 state and at least one\r
- logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.\r
-\r
- @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);\r
- @endcode\r
- @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655\r
-\r
-\r
-/**\r
- Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.\r
-\r
- @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);\r
- @endcode\r
- @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.\r
-**/\r
-#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656\r
-\r
-\r
-/**\r
- Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate\r
- as the TSC. The increment each cycle is weighted by the number of processor\r
- cores in the package that reside in C0. If N cores are simultaneously in C0,\r
- then each cycle the counter increments by N.\r
-\r
- @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);\r
- @endcode\r
- @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658\r
-\r
-\r
-/**\r
- Package. Any Core C0 Residency. (R/O). Increment at the same rate as the\r
- TSC. The increment each cycle is one if any processor core in the package is\r
- in C0.\r
-\r
- @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);\r
- @endcode\r
- @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659\r
-\r
-\r
-/**\r
- Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate\r
- as the TSC. The increment each cycle is one if any processor graphic\r
- device's compute engines are in C0.\r
-\r
- @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);\r
- @endcode\r
- @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A\r
-\r
-\r
-/**\r
- Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment\r
- at the same rate as the TSC. The increment each cycle is one if at least one\r
- compute engine of the processor graphics is in C0 and at least one processor\r
- core in the package is also in C0.\r
-\r
- @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);\r
- @endcode\r
- @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B\r
-\r
-\r
-/**\r
- Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to\r
- limit power consumption of the platform devices to the specified values. The\r
- Long Duration power consumption is specified via Platform_Power_Limit_1 and\r
- Platform_Power_Limit_1_Time. The Short Duration power consumption limit is\r
- specified via the Platform_Power_Limit_2 with duration chosen by the\r
- processor. The processor implements an exponential-weighted algorithm in the\r
- placement of the time windows.\r
-\r
- @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which\r
- /// the platform must not exceed over a time window as specified by\r
- /// Power_Limit_1_TIME field. The default value is the Thermal Design\r
- /// Power (TDP) and varies with product skus. The unit is specified in\r
- /// MSR_RAPLPOWER_UNIT.\r
- ///\r
- UINT32 PlatformPowerLimit1:15;\r
- ///\r
- /// [Bit 15] Enable Platform Power Limit #1. When set, enables the\r
- /// processor to apply control policy such that the platform power does\r
- /// not exceed Platform Power limit #1 over the time window specified by\r
- /// Power Limit #1 Time Window.\r
- ///\r
- UINT32 EnablePlatformPowerLimit1:1;\r
- ///\r
- /// [Bit 16] Platform Clamping Limitation #1. When set, allows the\r
- /// processor to go below the OS requested P states in order to maintain\r
- /// the power below specified Platform Power Limit #1 value. This bit is\r
- /// writeable only when CPUID (EAX=6):EAX[4] is set.\r
- ///\r
- UINT32 PlatformClampingLimitation1:1;\r
- ///\r
- /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the\r
- /// duration of the time window over which Platform Power Limit 1 value\r
- /// should be maintained for sustained long duration. This field is made\r
- /// up of two numbers from the following equation: Time Window = (float)\r
- /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =\r
- /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is\r
- /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,\r
- /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].\r
- ///\r
- UINT32 Time:7;\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which\r
- /// the platform must not exceed over the Short Duration time window\r
- /// chosen by the processor. The recommended default value is 1.25 times\r
- /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).\r
- ///\r
- UINT32 PlatformPowerLimit2:15;\r
- ///\r
- /// [Bit 47] Enable Platform Power Limit #2. When set, enables the\r
- /// processor to apply control policy such that the platform power does\r
- /// not exceed Platform Power limit #2 over the Short Duration time window.\r
- ///\r
- UINT32 EnablePlatformPowerLimit2:1;\r
- ///\r
- /// [Bit 48] Platform Clamping Limitation #2. When set, allows the\r
- /// processor to go below the OS requested P states in order to maintain\r
- /// the power below specified Platform Power Limit #2 value.\r
- ///\r
- UINT32 PlatformClampingLimitation2:1;\r
- UINT32 Reserved2:14;\r
- ///\r
- /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR\r
- /// until system RESET.\r
- ///\r
- UINT32 Lock:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last\r
- branch record registers on the last branch record stack. This part of the\r
- stack contains pointers to the source instruction. See also: - Last Branch\r
- Record Stack TOS at 1C9H - Section 17.10.\r
-\r
- @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);\r
- AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690\r
-#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691\r
-#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692\r
-#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693\r
-#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694\r
-#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695\r
-#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696\r
-#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697\r
-#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698\r
-#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699\r
-#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A\r
-#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B\r
-#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C\r
-#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D\r
-#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E\r
-#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
- (frequency refers to processor graphics frequency).\r
-\r
- @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);\r
- AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r
-**/\r
-#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
- /// assertion of external PROCHOT.\r
- ///\r
- UINT32 PROCHOT_Status:1;\r
- ///\r
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
- /// thermal event.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:3;\r
- ///\r
- /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
- /// is reduced due to running average thermal limit.\r
- ///\r
- UINT32 RunningAverageThermalLimitStatus:1;\r
- ///\r
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
- /// to a thermal alert from a processor Voltage Regulator.\r
- ///\r
- UINT32 VRThermAlertStatus:1;\r
- ///\r
- /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
- /// reduced due to VR TDC limit.\r
- ///\r
- UINT32 VRThermalDesignCurrentStatus:1;\r
- ///\r
- /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
- /// electrical or other constraints.\r
- ///\r
- UINT32 OtherStatus:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
- /// set, frequency is reduced due to package/platform-level power limiting\r
- /// PL1.\r
- ///\r
- UINT32 PL1Status:1;\r
- ///\r
- /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
- /// set, frequency is reduced due to package/platform-level power limiting\r
- /// PL2/PL3.\r
- ///\r
- UINT32 PL2Status:1;\r
- ///\r
- /// [Bit 12] Inefficient Operation Status (R0) When set, processor\r
- /// graphics frequency is operating below target frequency.\r
- ///\r
- UINT32 InefficientOperationStatus:1;\r
- UINT32 Reserved3:3;\r
- ///\r
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PROCHOT_Log:1;\r
- ///\r
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:3;\r
- ///\r
- /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
- /// the RATL Status bit has asserted since the log bit was last cleared.\r
- /// This log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 RunningAverageThermalLimitLog:1;\r
- ///\r
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
- /// Alert Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 VRThermAlertLog:1;\r
- ///\r
- /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
- /// VR Therm Alert Status bit has asserted since the log bit was last\r
- /// cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 VRThermalDesignCurrentLog:1;\r
- ///\r
- /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
- /// asserted since the log bit was last cleared. This log bit will remain\r
- /// set until cleared by software writing 0.\r
- ///\r
- UINT32 OtherLog:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
- /// indicates that the Package/Platform Level PL1 Power Limiting Status\r
- /// bit has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PL1Log:1;\r
- ///\r
- /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
- /// indicates that the Package/Platform Level PL2 Power Limiting Status\r
- /// bit has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PL2Log:1;\r
- ///\r
- /// [Bit 28] Inefficient Operation Log When set, indicates that the\r
- /// Inefficient Operation Status bit has asserted since the log bit was\r
- /// last cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 InefficientOperationLog:1;\r
- UINT32 Reserved6:3;\r
- UINT32 Reserved7:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
-\r
-\r
-/**\r
- Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
- (frequency refers to ring interconnect in the uncore).\r
-\r
- @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);\r
- AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
-**/\r
-#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
- /// assertion of external PROCHOT.\r
- ///\r
- UINT32 PROCHOT_Status:1;\r
- ///\r
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
- /// thermal event.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:3;\r
- ///\r
- /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
- /// is reduced due to running average thermal limit.\r
- ///\r
- UINT32 RunningAverageThermalLimitStatus:1;\r
- ///\r
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
- /// to a thermal alert from a processor Voltage Regulator.\r
- ///\r
- UINT32 VRThermAlertStatus:1;\r
- ///\r
- /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
- /// reduced due to VR TDC limit.\r
- ///\r
- UINT32 VRThermalDesignCurrentStatus:1;\r
- ///\r
- /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
- /// electrical or other constraints.\r
- ///\r
- UINT32 OtherStatus:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
- /// set, frequency is reduced due to package/Platform-level power limiting\r
- /// PL1.\r
- ///\r
- UINT32 PL1Status:1;\r
- ///\r
- /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
- /// set, frequency is reduced due to package/Platform-level power limiting\r
- /// PL2/PL3.\r
- ///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved3:4;\r
- ///\r
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PROCHOT_Log:1;\r
- ///\r
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:3;\r
- ///\r
- /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
- /// the RATL Status bit has asserted since the log bit was last cleared.\r
- /// This log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 RunningAverageThermalLimitLog:1;\r
- ///\r
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
- /// Alert Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 VRThermAlertLog:1;\r
- ///\r
- /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
- /// VR Therm Alert Status bit has asserted since the log bit was last\r
- /// cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 VRThermalDesignCurrentLog:1;\r
- ///\r
- /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
- /// asserted since the log bit was last cleared. This log bit will remain\r
- /// set until cleared by software writing 0.\r
- ///\r
- UINT32 OtherLog:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
- /// indicates that the Package/Platform Level PL1 Power Limiting Status\r
- /// bit has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PL1Log:1;\r
- ///\r
- /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
- /// indicates that the Package/Platform Level PL2 Power Limiting Status\r
- /// bit has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PL2Log:1;\r
- UINT32 Reserved6:4;\r
- UINT32 Reserved7:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction. See also: - Last Branch\r
- Record Stack TOS at 1C9H - Section 17.10.\r
-\r
- @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);\r
- AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.\r
- MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
- @{\r
-**/\r
-#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0\r
-#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1\r
-#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2\r
-#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3\r
-#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4\r
-#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5\r
-#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6\r
-#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7\r
-#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8\r
-#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9\r
-#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA\r
-#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB\r
-#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC\r
-#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD\r
-#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE\r
-#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF\r
-/// @}\r
-\r
-\r
-/**\r
- Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet\r
- of last branch record registers on the last branch record stack. This part\r
- of the stack contains flag, TSX-related and elapsed cycle information. See\r
- also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR\r
- Stack.".\r
-\r
- @param ECX MSR_SKYLAKE_LBR_INFO_n\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.\r
- MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.\r
- @{\r
-**/\r
-#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0\r
-#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1\r
-#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2\r
-#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3\r
-#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4\r
-#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5\r
-#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6\r
-#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7\r
-#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8\r
-#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9\r
-#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA\r
-#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB\r
-#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC\r
-#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD\r
-#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE\r
-#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF\r
-#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0\r
-#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1\r
-#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2\r
-#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3\r
-#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4\r
-#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5\r
-#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6\r
-#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7\r
-#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8\r
-#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9\r
-#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA\r
-#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB\r
-#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC\r
-#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD\r
-#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE\r
-#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore fixed counter control (R/W).\r
-\r
- @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:20;\r
- ///\r
- /// [Bit 20] Enable overflow propagation.\r
- ///\r
- UINT32 EnableOverflow:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 22] Enable counting.\r
- ///\r
- UINT32 EnableCounting:1;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore fixed counter.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Current count.\r
- ///\r
- UINT32 CurrentCount:32;\r
- ///\r
- /// [Bits 43:32] Current count.\r
- ///\r
- UINT32 CurrentCountHi:12;\r
- UINT32 Reserved:20;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore C-Box configuration information (R/O).\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Specifies the number of C-Box units with programmable\r
- /// counters (including processor cores and processor graphics),.\r
- ///\r
- UINT32 CBox:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, performance counter 0.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, performance counter 1.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, counter 0 event select MSR.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
-\r
-\r
-/**\r
- Package. Uncore Arb unit, counter 1 event select MSR.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, counter 0 event select MSR.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, counter 1 event select MSR.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, performance counter 0.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 0, performance counter 1.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, counter 0 event select MSR.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, counter 1 event select MSR.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, performance counter 0.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 1, performance counter 1.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, counter 0 event select MSR.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, counter 1 event select MSR.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, performance counter 0.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 2, performance counter 1.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 3, counter 0 event select MSR.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 3, counter 1 event select MSR.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 3, performance counter 0.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736\r
-\r
-\r
-/**\r
- Package. Uncore C-Box 3, performance counter 1.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737\r
-\r
-\r
-/**\r
- Package. Uncore PMU global control.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Slice 0 select.\r
- ///\r
- UINT32 PMI_Sel_Slice0:1;\r
- ///\r
- /// [Bit 1] Slice 1 select.\r
- ///\r
- UINT32 PMI_Sel_Slice1:1;\r
- ///\r
- /// [Bit 2] Slice 2 select.\r
- ///\r
- UINT32 PMI_Sel_Slice2:1;\r
- ///\r
- /// [Bit 3] Slice 3 select.\r
- ///\r
- UINT32 PMI_Sel_Slice3:1;\r
- ///\r
- /// [Bit 4] Slice 4select.\r
- ///\r
- UINT32 PMI_Sel_Slice4:1;\r
- UINT32 Reserved1:14;\r
- UINT32 Reserved2:10;\r
- ///\r
- /// [Bit 29] Enable all uncore counters.\r
- ///\r
- UINT32 EN:1;\r
- ///\r
- /// [Bit 30] Enable wake on PMI.\r
- ///\r
- UINT32 WakePMI:1;\r
- ///\r
- /// [Bit 31] Enable Freezing counter when overflow.\r
- ///\r
- UINT32 FREEZE:1;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Uncore PMU main status.\r
-\r
- @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
- @endcode\r
- @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
-**/\r
-#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Fixed counter overflowed.\r
- ///\r
- UINT32 Fixed:1;\r
- ///\r
- /// [Bit 1] An ARB counter overflowed.\r
- ///\r
- UINT32 ARB:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 3] A CBox counter overflowed (on any slice).\r
- ///\r
- UINT32 CBox:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Package. NPK Address Used by AET Messages (R/W).\r
-\r
- @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);\r
- AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080\r
-\r
-/**\r
- MSR information returned for MSR index\r
- #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock\r
- /// bit has to be set in order for the AET packets to be directed to NPK\r
- /// MMIO.\r
- ///\r
- UINT32 Fix_Me_1:1;\r
- UINT32 Reserved:17;\r
- ///\r
- /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
- ///\r
- UINT32 ACPIBAR_BASE_ADDRESS:14;\r
- ///\r
- /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
- ///\r
- UINT32 Fix_Me_2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;\r
-\r
-\r
-/**\r
- Core. Processor Reserved Memory Range Register - Physical Base Control\r
- Register (R/W).\r
-\r
- @param ECX MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);\r
- AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] MemType PRMRR BASE MemType.\r
- ///\r
- UINT32 MemTypePRMRRBASEMemType:3;\r
- UINT32 Reserved1:9;\r
- ///\r
- /// [Bits 31:12] Base PRMRR Base Address.\r
- ///\r
- UINT32 BasePRMRRBaseAddress:20;\r
- ///\r
- /// [Bits 45:32] Base PRMRR Base Address.\r
- ///\r
- UINT32 Fix_Me_1:14;\r
- UINT32 Reserved2:18;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;\r
-\r
-\r
-/**\r
- Core. Processor Reserved Memory Range Register - Physical Mask Control\r
- Register (R/W).\r
-\r
- @param ECX MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);\r
- AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:10;\r
- ///\r
- /// [Bit 10] Lock Lock bit for the PRMRR.\r
- ///\r
- UINT32 Fix_Me_1:1;\r
- ///\r
- /// [Bit 11] VLD Enable bit for the PRMRR.\r
- ///\r
- UINT32 VLD:1;\r
- ///\r
- /// [Bits 31:12] Mask PRMRR MASK bits.\r
- ///\r
- UINT32 Fix_Me_2:20;\r
- ///\r
- /// [Bits 45:32] Mask PRMRR MASK bits.\r
- ///\r
- UINT32 Fix_Me_3:14;\r
- UINT32 Reserved2:18;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;\r
-\r
-\r
-/**\r
- Core. Valid PRMRR Configurations (R/W).\r
-\r
- @param ECX MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);\r
- AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] 1M supported MEE size.\r
- ///\r
- UINT32 Fix_Me_1:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bit 5] 32M supported MEE size.\r
- ///\r
- UINT32 Fix_Me_2:1;\r
- ///\r
- /// [Bit 6] 64M supported MEE size.\r
- ///\r
- UINT32 Fix_Me_3:1;\r
- ///\r
- /// [Bit 7] 128M supported MEE size.\r
- ///\r
- UINT32 Fix_Me_4:1;\r
- UINT32 Reserved2:24;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;\r
-\r
-\r
-/**\r
- Package. (R/W) The PRMRR range is used to protect Xucode memory from\r
- unauthorized reads and writes. Any IO access to this range is aborted. This\r
- register controls the location of the PRMRR range by indicating its starting\r
- address. It functions in tandem with the PRMRR mask register.\r
-\r
- @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:12;\r
- ///\r
- /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the\r
- /// base address memory range which is allocated to PRMRR memory.\r
- ///\r
- UINT32 Fix_Me_1:20;\r
- ///\r
- /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the\r
- /// base address memory range which is allocated to PRMRR memory.\r
- ///\r
- UINT32 Fix_Me_2:7;\r
- UINT32 Reserved2:25;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;\r
-\r
-\r
-/**\r
- Package. (R/W) This register controls the size of the PRMRR range by\r
- indicating which address bits must match the PRMRR base register value.\r
-\r
- @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);\r
- AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:10;\r
- ///\r
- /// [Bit 10] Lock Setting this bit locks all writeable settings in this\r
- /// register, including itself.\r
- ///\r
- UINT32 Fix_Me_1:1;\r
- ///\r
- /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and\r
- /// valid.\r
- ///\r
- UINT32 Fix_Me_2:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;\r
-\r
-/**\r
- Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits\r
- for the LLC and Ring.\r
-\r
- @param ECX MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);\r
- AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the\r
- /// LLC/Ring.\r
- ///\r
- UINT32 Fix_Me_1:7;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum\r
- /// possible ratio of the LLC/Ring.\r
- ///\r
- UINT32 Fix_Me_2:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Branch Monitoring Global Control (R/W).\r
-\r
- @param ECX MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);\r
- AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] EnMonitoring Global enable for branch monitoring.\r
- ///\r
- UINT32 EnMonitoring:1;\r
- ///\r
- /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold\r
- /// trip. The branch monitoring event handler is signaled via the existing\r
- /// PMI signaling mechanism as programmed from the corresponding local\r
- /// APIC LVT entry.\r
- ///\r
- UINT32 EnExcept:1;\r
- ///\r
- /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause\r
- /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a\r
- /// triggering condition occurs and this bit is enabled.\r
- ///\r
- UINT32 EnLBRFrz:1;\r
- ///\r
- /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event\r
- /// triggering and LBR freeze actions are disabled when operating at VMX\r
- /// non-root operation.\r
- ///\r
- UINT32 DisableInGuest:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -\r
- /// 1023 are supported. Once the Window counter reaches the WindowSize\r
- /// count both the Window Counter and all Branch Monitoring Counters are\r
- /// cleared.\r
- ///\r
- UINT32 WindowSize:10;\r
- UINT32 Reserved2:6;\r
- ///\r
- /// [Bits 25:24] WindowCntSel Window event count select: '00 =\r
- /// Instructions retired. '01 = Branch instructions retired '10 = Return\r
- /// instructions retired. '11 = Indirect branch instructions retired.\r
- ///\r
- UINT32 WindowCntSel:2;\r
- ///\r
- /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring\r
- /// event triggering condition is true only if all enabled counters'\r
- /// threshold conditions are true. When '0', the threshold tripping\r
- /// condition is true if any enabled counters' threshold is true.\r
- ///\r
- UINT32 CntAndMode:1;\r
- UINT32 Reserved3:5;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;\r
-\r
-/**\r
- Branch Monitoring Global Status (R/W).\r
-\r
- @param ECX MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);\r
- AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch\r
- /// Monitoring event signaling is blocked until this bit is cleared by\r
- /// software.\r
- ///\r
- UINT32 BranchMonitoringEventSignaled:1;\r
- ///\r
- /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is\r
- /// considered valid for sampling by branch monitoring software.\r
- ///\r
- UINT32 LBRsValid:1;\r
- UINT32 Reserved1:6;\r
- ///\r
- /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This\r
- /// status bit is sticky and once set requires clearing by software.\r
- /// Counter operation continues independent of the state of the bit.\r
- ///\r
- UINT32 CntrHit0:1;\r
- ///\r
- /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This\r
- /// status bit is sticky and once set requires clearing by software.\r
- /// Counter operation continues independent of the state of the bit.\r
- ///\r
- UINT32 CntrHit1:1;\r
- UINT32 Reserved2:6;\r
- ///\r
- /// [Bits 25:16] CountWindow The current value of the window counter. The\r
- /// count value is frozen on a valid branch monitoring triggering\r
- /// condition. This is a 10-bit unsigned value.\r
- ///\r
- UINT32 CountWindow:10;\r
- UINT32 Reserved3:6;\r
- ///\r
- /// [Bits 39:32] Count0 The current value of counter 0 updated after each\r
- /// occurrence of the event being counted. The count value is frozen on a\r
- /// valid branch monitoring triggering condition (in which case CntrHit0\r
- /// will also be set). This is an 8-bit signed value (2's complement).\r
- /// Heuristic events which only increment will saturate and freeze at\r
- /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
- /// value 0x7F (+127) and minimum value 0x80 (-128).\r
- ///\r
- UINT32 Count0:8;\r
- ///\r
- /// [Bits 47:40] Count1 The current value of counter 1 updated after each\r
- /// occurrence of the event being counted. The count value is frozen on a\r
- /// valid branch monitoring triggering condition (in which case CntrHit1\r
- /// will also be set). This is an 8-bit signed value (2's complement).\r
- /// Heuristic events which only increment will saturate and freeze at\r
- /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
- /// value 0x7F (+127) and minimum value 0x80 (-128).\r
- ///\r
- UINT32 Count1:8;\r
- UINT32 Reserved4:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Package. Package C3 Residency Counter (R/O). Note: C-state values are\r
- processor specific C-state code names, unrelated to MWAIT extension C-state\r
- parameters or ACPI C-states.\r
-\r
- @param ECX MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8\r
-\r
-\r
-/**\r
- Core. Core C1 Residency Counter (R/O). Value since last reset for the Core\r
- C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC).\r
- This counter counts in case both of the core's threads are in an idle state\r
- and at least one of the core's thread residency is in a C1 state or in one\r
- of its sub states. The counter is updated only after a core C state exit.\r
- Note: Always reads 0 if core C1 is unsupported. A value of zero indicates\r
- that this processor does not support core C1 or never entered core C1 level\r
- state.\r
-\r
- @param ECX MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660\r
-\r
-\r
-/**\r
- Core. Core C3 Residency Counter (R/O). Will always return 0.\r
-\r
- @param ECX MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662\r
-\r
-\r
-/**\r
- Package. Protected Processor Inventory Number Enable Control (R/W).\r
-\r
- @param ECX MSR_SKYLAKE_PPIN_CTL (0x0000004E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_PPIN_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);\r
- AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_PPIN_CTL 0x0000004E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] LockOut (R/WO) See Table 2-25.\r
- ///\r
- UINT32 LockOut:1;\r
- ///\r
- /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
- ///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_PPIN_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Protected Processor Inventory Number (R/O). Protected Processor\r
- Inventory Number (R/O) See Table 2-25.\r
-\r
- @param ECX MSR_SKYLAKE_PPIN (0x0000004F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_PPIN 0x0000004F\r
-\r
-\r
-/**\r
- Package. Platform Information Contains power management and other model\r
- specific features enumeration. See http://biosbits.org.\r
-\r
- @param ECX MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_PLATFORM_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);\r
- AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
- ///\r
- UINT32 MaximumNon_TurboRatio:8;\r
- UINT32 Reserved2:7;\r
- ///\r
- /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
- ///\r
- UINT32 PPIN_CAP:1;\r
- UINT32 Reserved3:4;\r
- ///\r
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
- /// Table 2-25.\r
- ///\r
- UINT32 ProgrammableRatioLimit:1;\r
- ///\r
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
- /// Table 2-25.\r
- ///\r
- UINT32 ProgrammableTDPLimit:1;\r
- ///\r
- /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
- ///\r
- UINT32 ProgrammableTJOFFSET:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
- ///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved6:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_PLATFORM_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
- specific C-state code names, unrelated to MWAIT extension C-state parameters\r
- or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__.\r
-\r
- @param ECX MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
- /// processor-specific C-state code name (consuming the least power) for\r
- /// the package. The default is set as factory-configured package Cstate\r
- /// limit. The following C-state code name encodings are supported: 000b:\r
- /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
- /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
- /// supported by the processor are available.\r
- ///\r
- UINT32 C_StateLimit:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
- ///\r
- UINT32 MWAITRedirectionEnable:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO).\r
- ///\r
- UINT32 CFGLock:1;\r
- ///\r
- /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
- /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
- ///\r
- UINT32 AutomaticC_StateConversionEnable:1;\r
- UINT32 Reserved3:8;\r
- ///\r
- /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
- ///\r
- UINT32 C3StateAutoDemotionEnable:1;\r
- ///\r
- /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
- ///\r
- UINT32 C1StateAutoDemotionEnable:1;\r
- ///\r
- /// [Bit 27] Enable C3 Undemotion (R/W).\r
- ///\r
- UINT32 EnableC3Undemotion:1;\r
- ///\r
- /// [Bit 28] Enable C1 Undemotion (R/W).\r
- ///\r
- UINT32 EnableC1Undemotion:1;\r
- ///\r
- /// [Bit 29] Package C State Demotion Enable (R/W).\r
- ///\r
- UINT32 CStateDemotionEnable:1;\r
- ///\r
- /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
- ///\r
- UINT32 CStateUnDemotionEnable:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Global Machine Check Capability (R/O).\r
-\r
- @param ECX MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Count.\r
- ///\r
- UINT32 Count:8;\r
- ///\r
- /// [Bit 8] MCG_CTL_P.\r
- ///\r
- UINT32 MCG_CTL_P:1;\r
- ///\r
- /// [Bit 9] MCG_EXT_P.\r
- ///\r
- UINT32 MCG_EXT_P:1;\r
- ///\r
- /// [Bit 10] MCP_CMCI_P.\r
- ///\r
- UINT32 MCP_CMCI_P:1;\r
- ///\r
- /// [Bit 11] MCG_TES_P.\r
- ///\r
- UINT32 MCG_TES_P:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 23:16] MCG_EXT_CNT.\r
- ///\r
- UINT32 MCG_EXT_CNT:8;\r
- ///\r
- /// [Bit 24] MCG_SER_P.\r
- ///\r
- UINT32 MCG_SER_P:1;\r
- ///\r
- /// [Bit 25] MCG_EM_P.\r
- ///\r
- UINT32 MCG_EM_P:1;\r
- ///\r
- /// [Bit 26] MCG_ELOG_P.\r
- ///\r
- UINT32 MCG_ELOG_P:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;\r
-\r
-\r
-/**\r
- THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
- Enhancement. Accessible only while in SMM.\r
-\r
- @param ECX MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);\r
- AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
- ///\r
- /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
- /// SMM code access restriction is supported and a host-space interface is\r
- /// available to SMM handler.\r
- ///\r
- UINT32 SMM_Code_Access_Chk:1;\r
- ///\r
- /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
- /// SMM long flow indicator is supported and a host-space interface is\r
- /// available to SMM handler.\r
- ///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;\r
-\r
-\r
-/**\r
- Package. Temperature Target.\r
-\r
- @param ECX MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);\r
- AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
- ///\r
- UINT32 TemperatureTarget:8;\r
- ///\r
- /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
- ///\r
- UINT32 TCCActivationOffset:4;\r
- UINT32 Reserved2:4;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;\r
-\r
-/**\r
- Package. This register defines the active core ranges for each frequency\r
- point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must\r
- be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored.\r
- The last valid entry must have NUMCORE >= the number of cores in the SKU. If\r
- any of the rules above are broken, the configuration is silently rejected.\r
-\r
- @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);\r
- AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency\r
- /// point.\r
- ///\r
- UINT32 NUMCORE_0:8;\r
- ///\r
- /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each\r
- /// frequency point.\r
- ///\r
- UINT32 NUMCORE_1:8;\r
- ///\r
- /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each\r
- /// frequency point.\r
- ///\r
- UINT32 NUMCORE_2:8;\r
- ///\r
- /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each\r
- /// frequency point.\r
- ///\r
- UINT32 NUMCORE_3:8;\r
- ///\r
- /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each\r
- /// frequency point.\r
- ///\r
- UINT32 NUMCORE_4:8;\r
- ///\r
- /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each\r
- /// frequency point.\r
- ///\r
- UINT32 NUMCORE_5:8;\r
- ///\r
- /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each\r
- /// frequency point.\r
- ///\r
- UINT32 NUMCORE_6:8;\r
- ///\r
- /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each\r
- /// frequency point.\r
- ///\r
- UINT32 NUMCORE_7:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;\r
-\r
-\r
-/**\r
- Package. Unit Multipliers Used in RAPL Interfaces (R/O).\r
-\r
- @param ECX MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
- ///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 12:8] Package. Energy Status Units Energy related information\r
- /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
- /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
- /// micro-joules).\r
- ///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
- /// Interfaces.".\r
- ///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
- Domain.".\r
-\r
- @param ECX MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618\r
-\r
-\r
-/**\r
- Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
-\r
- @param ECX MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
- /// to enable DRAM RAPL mode 0 (Direct VR).\r
- ///\r
- UINT32 Energy:32;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);\r
- AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C\r
-\r
-\r
-/**\r
- Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
- fields represent the widest possible range of uncore frequencies. Writing to\r
- these fields allows software to control the minimum and the maximum\r
- frequency that hardware will select.\r
-\r
- @param ECX MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);\r
- AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
- /// LLC/Ring.\r
- ///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
- /// possible ratio of the LLC/Ring.\r
- ///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Reserved (R/O) Reads return 0.\r
-\r
- @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
-\r
-\r
-/**\r
- THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,\r
- ECX=0):EBX.RDT-M[bit 12] = 1.\r
-\r
- @param ECX MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);\r
- AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3\r
- /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:\r
- /// Local memory bandwidth monitoring. All other encoding reserved.\r
- ///\r
- UINT32 EventID:8;\r
- UINT32 Reserved1:24;\r
- ///\r
- /// [Bits 41:32] RMID (RW).\r
- ///\r
- UINT32 RMID:10;\r
- UINT32 Reserved2:22;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;\r
-\r
-\r
-/**\r
- THREAD. Resource Association Register (R/W).\r
-\r
- @param ECX MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);\r
- AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] RMID.\r
- ///\r
- UINT32 RMID:10;\r
- UINT32 Reserved1:22;\r
- ///\r
- /// [Bits 51:32] COS (R/W).\r
- ///\r
- UINT32 COS:20;\r
- UINT32 Reserved2:12;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;\r
-\r
-\r
-/**\r
- Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,\r
- ECX=1):EDX.COS_MAX[15:0] >=0.\r
-\r
- @param ECX MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);\r
- AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.\r
- ///\r
- UINT32 CBM:20;\r
- UINT32 Reserved2:12;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;\r
-\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __XEON_5600_MSR_H__\r
-#define __XEON_5600_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel(R) Xeon(R) Processor Series 5600?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x25 || \\r
- DisplayModel == 0x2C \\r
- ) \\r
- )\r
-\r
-/**\r
- Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
- handler to handle unsuccessful read of this MSR.\r
-\r
- @param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);\r
- AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
-**/\r
-#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
- /// MSR, the configuration of AES instruction set availability is as\r
- /// follows: 11b: AES instructions are not available until next RESET.\r
- /// otherwise, AES instructions are available. Note, AES instruction set\r
- /// is not available if read is unsuccessful. If the configuration is not\r
- /// 01b, AES instruction can be mis-configured if a privileged agent\r
- /// unintentionally writes 11b.\r
- ///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Offcore Response Event Select Register (R/W).\r
-\r
- @param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);\r
- AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);\r
- @endcode\r
- @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
-**/\r
-#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);\r
- @endcode\r
- @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
- /// limit of 1 core active.\r
- ///\r
- UINT32 Maximum1C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
- /// limit of 2 core active.\r
- ///\r
- UINT32 Maximum2C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
- /// limit of 3 core active.\r
- ///\r
- UINT32 Maximum3C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
- /// limit of 4 core active.\r
- ///\r
- UINT32 Maximum4C:8;\r
- ///\r
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
- /// limit of 5 core active.\r
- ///\r
- UINT32 Maximum5C:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
- /// limit of 6 core active.\r
- ///\r
- UINT32 Maximum6C:8;\r
- UINT32 Reserved:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. See Table 2-2.\r
-\r
- @param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);\r
- AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);\r
- @endcode\r
- @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
-**/\r
-#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel(R) Xeon(R) Processor D product Family.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __XEON_D_MSR_H__\r
-#define __XEON_D_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel(R) Xeon(R) Processor D product Family?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x4F || \\r
- DisplayModel == 0x56 \\r
- ) \\r
- )\r
-\r
-/**\r
- Package. Protected Processor Inventory Number Enable Control (R/W).\r
-\r
- @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_PPIN_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);\r
- AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
-**/\r
-#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] LockOut (R/WO) See Table 2-25.\r
- ///\r
- UINT32 LockOut:1;\r
- ///\r
- /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
- ///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_PPIN_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Protected Processor Inventory Number (R/O). Protected Processor\r
- Inventory Number (R/O) See Table 2-25.\r
-\r
- @param ECX MSR_XEON_D_PPIN (0x0000004F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);\r
- @endcode\r
- @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.\r
-**/\r
-#define MSR_XEON_D_PPIN 0x0000004F\r
-\r
-\r
-/**\r
- Package. See http://biosbits.org.\r
-\r
- @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);\r
- AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
-**/\r
-#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
- ///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:7;\r
- ///\r
- /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
- ///\r
- UINT32 PPIN_CAP:1;\r
- UINT32 Reserved3:4;\r
- ///\r
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
- /// Table 2-25.\r
- ///\r
- UINT32 RatioLimit:1;\r
- ///\r
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
- /// Table 2-25.\r
- ///\r
- UINT32 TDPLimit:1;\r
- ///\r
- /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
- ///\r
- UINT32 TJOFFSET:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
- ///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved6:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_PLATFORM_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
- specific C-state code names, unrelated to MWAIT extension C-state parameters\r
- or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
-\r
- @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
-**/\r
-#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
- /// processor-specific C-state code name (consuming the least power) for\r
- /// the package. The default is set as factory-configured package C-state\r
- /// limit. The following C-state code name encodings are supported: 000b:\r
- /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
- /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
- /// supported by the processor are available.\r
- ///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
- ///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO).\r
- ///\r
- UINT32 CFGLock:1;\r
- ///\r
- /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
- /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
- ///\r
- UINT32 CStateConversion:1;\r
- UINT32 Reserved3:8;\r
- ///\r
- /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
- ///\r
- UINT32 C3AutoDemotion:1;\r
- ///\r
- /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
- ///\r
- UINT32 C1AutoDemotion:1;\r
- ///\r
- /// [Bit 27] Enable C3 Undemotion (R/W).\r
- ///\r
- UINT32 C3Undemotion:1;\r
- ///\r
- /// [Bit 28] Enable C1 Undemotion (R/W).\r
- ///\r
- UINT32 C1Undemotion:1;\r
- ///\r
- /// [Bit 29] Package C State Demotion Enable (R/W).\r
- ///\r
- UINT32 CStateDemotion:1;\r
- ///\r
- /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
- ///\r
- UINT32 CStateUndemotion:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Global Machine Check Capability (R/O).\r
-\r
- @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);\r
- @endcode\r
- @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
-**/\r
-#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Count.\r
- ///\r
- UINT32 Count:8;\r
- ///\r
- /// [Bit 8] MCG_CTL_P.\r
- ///\r
- UINT32 MCG_CTL_P:1;\r
- ///\r
- /// [Bit 9] MCG_EXT_P.\r
- ///\r
- UINT32 MCG_EXT_P:1;\r
- ///\r
- /// [Bit 10] MCP_CMCI_P.\r
- ///\r
- UINT32 MCP_CMCI_P:1;\r
- ///\r
- /// [Bit 11] MCG_TES_P.\r
- ///\r
- UINT32 MCG_TES_P:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 23:16] MCG_EXT_CNT.\r
- ///\r
- UINT32 MCG_EXT_CNT:8;\r
- ///\r
- /// [Bit 24] MCG_SER_P.\r
- ///\r
- UINT32 MCG_SER_P:1;\r
- ///\r
- /// [Bit 25] MCG_EM_P.\r
- ///\r
- UINT32 MCG_EM_P:1;\r
- ///\r
- /// [Bit 26] MCG_ELOG_P.\r
- ///\r
- UINT32 MCG_ELOG_P:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_IA32_MCG_CAP_REGISTER;\r
-\r
-\r
-/**\r
- THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
- Enhancement. Accessible only while in SMM.\r
-\r
- @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);\r
- AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
-**/\r
-#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
- ///\r
- /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
- /// SMM code access restriction is supported and a host-space interface\r
- /// available to SMM handler.\r
- ///\r
- UINT32 SMM_Code_Access_Chk:1;\r
- ///\r
- /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
- /// SMM long flow indicator is supported and a host-space interface\r
- /// available to SMM handler.\r
- ///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_SMM_MCA_CAP_REGISTER;\r
-\r
-\r
-/**\r
- Package.\r
-\r
- @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);\r
- AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
-**/\r
-#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
- ///\r
- UINT32 TemperatureTarget:8;\r
- ///\r
- /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
- ///\r
- UINT32 TCCActivationOffset:4;\r
- UINT32 Reserved2:4;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);\r
- @endcode\r
- @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.\r
- ///\r
- UINT32 Maximum1C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.\r
- ///\r
- UINT32 Maximum2C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.\r
- ///\r
- UINT32 Maximum3C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.\r
- ///\r
- UINT32 Maximum4C:8;\r
- ///\r
- /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.\r
- ///\r
- UINT32 Maximum5C:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.\r
- ///\r
- UINT32 Maximum6C:8;\r
- ///\r
- /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.\r
- ///\r
- UINT32 Maximum7C:8;\r
- ///\r
- /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.\r
- ///\r
- UINT32 Maximum8C:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);\r
- @endcode\r
- @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
-**/\r
-#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.\r
- ///\r
- UINT32 Maximum9C:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.\r
- ///\r
- UINT32 Maximum10C:8;\r
- ///\r
- /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.\r
- ///\r
- UINT32 Maximum11C:8;\r
- ///\r
- /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.\r
- ///\r
- UINT32 Maximum12C:8;\r
- ///\r
- /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.\r
- ///\r
- UINT32 Maximum13C:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.\r
- ///\r
- UINT32 Maximum14C:8;\r
- ///\r
- /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.\r
- ///\r
- UINT32 Maximum15C:8;\r
- ///\r
- /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.\r
- ///\r
- UINT32 Maximum16C:8;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;\r
-\r
-\r
-/**\r
- Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
-\r
- @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);\r
- @endcode\r
- @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
-**/\r
-#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
- ///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 12:8] Package. Energy Status Units Energy related information\r
- /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
- /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
- /// micro-joules).\r
- ///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
- /// Interfaces.".\r
- ///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
- Domain.".\r
-\r
- @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
-\r
-\r
-/**\r
- Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
-\r
- @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
- /// to enable DRAM RAPL mode 0 (Direct VR).\r
- ///\r
- UINT32 Energy:32;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;\r
-\r
-\r
-/**\r
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);\r
- @endcode\r
- @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);\r
- AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);\r
- @endcode\r
- @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
-**/\r
-#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
-\r
-\r
-/**\r
- Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
- fields represent the widest possible range of uncore frequencies. Writing to\r
- these fields allows software to control the minimum and the maximum\r
- frequency that hardware will select.\r
-\r
- @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);\r
- AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
- /// LLC/Ring.\r
- ///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
- /// possible ratio of the LLC/Ring.\r
- ///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
-\r
-/**\r
- Package. Reserved (R/O) Reads return 0.\r
-\r
- @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
-\r
-\r
-/**\r
- Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
- refers to processor core frequency).\r
-\r
- @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);\r
- AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
-**/\r
-#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
- /// reduced below the operating system request due to assertion of\r
- /// external PROCHOT.\r
- ///\r
- UINT32 PROCHOT_Status:1;\r
- ///\r
- /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
- /// operating system request due to a thermal event.\r
- ///\r
- UINT32 ThermalStatus:1;\r
- ///\r
- /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to PBM limit.\r
- ///\r
- UINT32 PowerBudgetManagementStatus:1;\r
- ///\r
- /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
- /// frequency is reduced below the operating system request due to PCS\r
- /// limit.\r
- ///\r
- UINT32 PlatformConfigurationServicesStatus:1;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
- /// When set, frequency is reduced below the operating system request\r
- /// because the processor has detected that utilization is low.\r
- ///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
- ///\r
- /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to a thermal alert from the\r
- /// Voltage Regulator.\r
- ///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
- /// reduced below the operating system request due to electrical design\r
- /// point constraints (e.g. maximum electrical current consumption).\r
- ///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:1;\r
- ///\r
- /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
- /// below the operating system request due to Multi-Core Turbo limits.\r
- ///\r
- UINT32 MultiCoreTurboStatus:1;\r
- UINT32 Reserved4:2;\r
- ///\r
- /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
- /// below max non-turbo P1.\r
- ///\r
- UINT32 FrequencyP1Status:1;\r
- ///\r
- /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
- /// set, frequency is reduced below max n-core turbo frequency.\r
- ///\r
- UINT32 TurboFrequencyLimitingStatus:1;\r
- ///\r
- /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
- /// reduced below the operating system request.\r
- ///\r
- UINT32 FrequencyLimitingStatus:1;\r
- ///\r
- /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PROCHOT_Log:1;\r
- ///\r
- /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ThermalLog:1;\r
- ///\r
- /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PowerBudgetManagementLog:1;\r
- ///\r
- /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
- /// the PCS Status bit has asserted since the log bit was last cleared.\r
- /// This log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 PlatformConfigurationServicesLog:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
- /// indicates that the AUBFC Status bit has asserted since the log bit was\r
- /// last cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
- ///\r
- /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
- /// Alert Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
- /// Status bit has asserted since the log bit was last cleared. This log\r
- /// bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 ElectricalDesignPointLog:1;\r
- UINT32 Reserved7:1;\r
- ///\r
- /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
- /// Turbo Status bit has asserted since the log bit was last cleared. This\r
- /// log bit will remain set until cleared by software writing 0.\r
- ///\r
- UINT32 MultiCoreTurboLog:1;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
- /// Frequency P1 Status bit has asserted since the log bit was last\r
- /// cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 CoreFrequencyP1Log:1;\r
- ///\r
- /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
- /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
- /// has asserted since the log bit was last cleared. This log bit will\r
- /// remain set until cleared by software writing 0.\r
- ///\r
- UINT32 TurboFrequencyLimitingLog:1;\r
- ///\r
- /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
- /// Frequency Limiting Status bit has asserted since the log bit was last\r
- /// cleared. This log bit will remain set until cleared by software\r
- /// writing 0.\r
- ///\r
- UINT32 CoreFrequencyLimitingLog:1;\r
- UINT32 Reserved9:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;\r
-\r
-\r
-/**\r
- THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
- ECX=0):EBX.RDT-M[bit 12] = 1.\r
-\r
- @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);\r
- AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
-**/\r
-#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3\r
- /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:\r
- /// Local memory bandwidth monitoring All other encoding reserved.\r
- ///\r
- UINT32 EventID:8;\r
- UINT32 Reserved1:24;\r
- ///\r
- /// [Bits 41:32] RMID (RW).\r
- ///\r
- UINT32 RMID:10;\r
- UINT32 Reserved2:22;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;\r
-\r
-\r
-/**\r
- THREAD. Resource Association Register (R/W).\r
-\r
- @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);\r
- AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
-**/\r
-#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 9:0] RMID.\r
- ///\r
- UINT32 RMID:10;\r
- UINT32 Reserved1:22;\r
- ///\r
- /// [Bits 51:32] COS (R/W).\r
- ///\r
- UINT32 COS:20;\r
- UINT32 Reserved2:12;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;\r
-\r
-\r
-/**\r
- Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
- ECX=1):EDX.COS_MAX[15:0] >= n.\r
-\r
- @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);\r
- AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM.\r
- MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
-/// @}\r
-\r
-/**\r
- MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0\r
- to #MSR_XEON_D_IA32_L3_QOS_MASK_15.\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.\r
- ///\r
- UINT32 CBM:20;\r
- UINT32 Reserved2:12;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;\r
-\r
-\r
-/**\r
- Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
- RW if MSR_PLATFORM_INFO.[28] = 1.\r
-\r
- @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);\r
- @endcode\r
- @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.\r
-**/\r
-#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:31;\r
- ///\r
- /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
- /// the processor uses override configuration specified in\r
- /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
- /// uses factory-set configuration (Default).\r
- ///\r
- UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
-\r
-\r
-/**\r
- Package. Cache Allocation Technology Configuration (R/W).\r
-\r
- @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);\r
- AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
-**/\r
-#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.\r
- ///\r
- UINT32 CAT:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __XEON_E7_MSR_H__\r
-#define __XEON_E7_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel(R) Xeon(R) Processor E7 Family?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x2F \\r
- ) \\r
- )\r
-\r
-/**\r
- Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
- handler to handle unsuccessful read of this MSR.\r
-\r
- @param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);\r
- AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
-**/\r
-#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
- /// MSR, the configuration of AES instruction set availability is as\r
- /// follows: 11b: AES instructions are not available until next RESET.\r
- /// otherwise, AES instructions are available. Note, AES instruction set\r
- /// is not available if read is unsuccessful. If the configuration is not\r
- /// 01b, AES instruction can be mis-configured if a privileged agent\r
- /// unintentionally writes 11b.\r
- ///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Offcore Response Event Select Register (R/W).\r
-\r
- @param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);\r
- AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
-**/\r
-#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7\r
-\r
-\r
-/**\r
- Package. Reserved Attempt to read/write will cause #UD.\r
-\r
- @param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r
- AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon local box control MSR.\r
-\r
- @param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon local box status MSR.\r
-\r
- @param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon event select MSR.\r
-\r
- @param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.\r
- MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.\r
- MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.\r
- MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.\r
- MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.\r
- MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-box 8 perfmon counter MSR.\r
-\r
- @param ECX MSR_XEON_E7_C8_PMON_CTRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
- MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
- MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
- MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
- MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.\r
- MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51\r
-#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53\r
-#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55\r
-#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57\r
-#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59\r
-#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon local box control MSR.\r
-\r
- @param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r
- AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r
-**/\r
-#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon local box status MSR.\r
-\r
- @param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r
- AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon local box overflow control MSR.\r
-\r
- @param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r
- AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r
-**/\r
-#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon event select MSR.\r
-\r
- @param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r
- AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.\r
- MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.\r
- MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.\r
- MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.\r
- MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.\r
- MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA\r
-/// @}\r
-\r
-\r
-/**\r
- Package. Uncore C-box 9 perfmon counter MSR.\r
-\r
- @param ECX MSR_XEON_E7_C9_PMON_CTRn\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r
- AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r
- @endcode\r
- @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
- MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
- MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
- MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
- MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.\r
- MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r
- @{\r
-**/\r
-#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1\r
-#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3\r
-#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5\r
-#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7\r
-#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9\r
-#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB\r
-/// @}\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.\r
-\r
- Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
- are provided for MSRs that contain one or more bit fields. If the MSR value\r
- returned is a single 32-bit or 64-bit value, then a data structure is not\r
- provided for that MSR.\r
-\r
- Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
- May 2018, Volume 4: Model-Specific-Registers (MSR)\r
-\r
-**/\r
-\r
-#ifndef __XEON_PHI_MSR_H__\r
-#define __XEON_PHI_MSR_H__\r
-\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-/**\r
- Is Intel(R) Xeon(R) Phi(TM) processor Family?\r
-\r
- @param DisplayFamily Display Family ID\r
- @param DisplayModel Display Model ID\r
-\r
- @retval TRUE Yes, it is.\r
- @retval FALSE No, it isn't.\r
-**/\r
-#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \\r
- (DisplayFamily == 0x06 && \\r
- ( \\r
- DisplayModel == 0x57 || \\r
- DisplayModel == 0x85 \\r
- ) \\r
- )\r
-\r
-/**\r
- Thread. SMI Counter (R/O).\r
-\r
- @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);\r
- @endcode\r
- @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
-**/\r
-#define MSR_XEON_PHI_SMI_COUNT 0x00000034\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] SMI Count (R/O).\r
- ///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_SMI_COUNT_REGISTER;\r
-\r
-/**\r
- Package. Protected Processor Inventory Number Enable Control (R/W).\r
-\r
- @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_PPIN_CTL 0x0000004E\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to\r
- /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if\r
- /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an\r
- /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a\r
- /// privileged inventory initialization agent to access MSR_PPIN. After\r
- /// reading MSR_PPIN, the privileged inventory initialization agent should\r
- /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
- /// prevent unauthorized modification to MSR_PPIN_CTL.\r
- ///\r
- UINT32 LockOut:1;\r
- ///\r
- /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
- /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]\r
- /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.\r
- /// Default is 0.\r
- ///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_PPIN_CTL_REGISTER;\r
-\r
-\r
-/**\r
- Package. Protected Processor Inventory Number (R/O). Protected Processor\r
- Inventory Number (R/O) A unique value within a given CPUID\r
- family/model/stepping signature that a privileged inventory initialization\r
- agent can access to identify each physical processor, when access to\r
- MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r
- MSR_PPIN_CTL[bits 1:0] = '10b'.\r
-\r
- @param ECX MSR_XEON_PHI_PPIN (0x0000004F)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_PPIN 0x0000004F\r
-\r
-/**\r
- Package. Platform Information Contains power management and other model\r
- specific features enumeration. See http://biosbits.org.\r
-\r
- @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:8;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
- /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
- /// MHz.\r
- ///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
- ///\r
- /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
- /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
- /// Turbo mode is disabled.\r
- ///\r
- UINT32 RatioLimit:1;\r
- ///\r
- /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
- /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
- /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
- /// programmable.\r
- ///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
- UINT32 Reserved4:8;\r
- ///\r
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
- /// minimum ratio (maximum efficiency) that the processor can operates, in\r
- /// units of 100MHz.\r
- ///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;\r
-\r
-\r
-/**\r
- Module. C-State Configuration Control (R/W).\r
-\r
- @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code\r
- /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No\r
- /// Retention 011b: C6 Retention 111b: No limit.\r
- ///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
- ///\r
- /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
- ///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
- ///\r
- /// [Bit 15] CFG Lock (R/WO).\r
- ///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved5:10;\r
- ///\r
- /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor\r
- /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
- /// auto-demote information.\r
- ///\r
- UINT32 C1StateAutoDemotionEnable:1;\r
- UINT32 Reserved6:1;\r
- ///\r
- /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables\r
- /// Undemotion from Demoted C1.\r
- ///\r
- UINT32 C1StateAutoUndemotionEnable:1;\r
- ///\r
- /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables\r
- /// Package C state demotion.\r
- ///\r
- UINT32 PKGC_StateAutoDemotionEnable:1;\r
- UINT32 Reserved7:2;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Module. Power Management IO Redirection in C-state (R/W).\r
-\r
- @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 15:0] LVL_2 Base Address (R/W).\r
- ///\r
- UINT32 Lvl2Base:16;\r
- ///\r
- /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which\r
- /// IO-redirection will be executed (0-127). Should be programmed based on\r
- /// the number of LVLx registers existing in the chipset.\r
- ///\r
- UINT32 CStateRange:7;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;\r
-\r
-\r
-/**\r
- Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
- handler to handle unsuccessful read of this MSR.\r
-\r
- @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);\r
- AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
-**/\r
-#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
- /// MSR, the configuration of AES instruction set availability is as\r
- /// follows: 11b: AES instructions are not available until next RESET.\r
- /// otherwise, AES instructions are available. Note, AES instruction set\r
- /// is not available if read is unsuccessful. If the configuration is not\r
- /// 01b, AES instruction can be mis-configured if a privileged agent\r
- /// unintentionally writes 11b.\r
- ///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r
-\r
-\r
-/**\r
- Thread. MISC_FEATURE_ENABLES.\r
-\r
- @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and\r
- /// MWAIT instructions do not cause invalid-opcode exceptions when\r
- /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed\r
- /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state\r
- /// other than C0 or C1, the instruction operates as if EAX indicated the\r
- /// C-state C1.\r
- ///\r
- UINT32 UserModeMonitorAndMwait:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;\r
-\r
-/**\r
- THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
- Enhancement. Accessible only while in SMM.\r
-\r
- @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);\r
- AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
-**/\r
-#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is\r
- /// set, that bank supports Enhanced MCA (Default all 0; does not support\r
- /// EMCA).\r
- ///\r
- UINT32 BankSupport:32;\r
- UINT32 Reserved4:24;\r
- ///\r
- /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.\r
- ///\r
- UINT32 TargetedSMI:1;\r
- ///\r
- /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature\r
- /// is supported.\r
- ///\r
- UINT32 SMM_CPU_SVRSTR:1;\r
- ///\r
- /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
- /// SMM code access restriction is supported and a host-space interface\r
- /// available to SMM handler.\r
- ///\r
- UINT32 SMM_Code_Access_Chk:1;\r
- ///\r
- /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
- /// SMM long flow indicator is supported and a host-space interface\r
- /// available to SMM handler.\r
- ///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
- functions to be enabled and disabled.\r
-\r
- @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);\r
- AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
-**/\r
-#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Fast-Strings Enable.\r
- ///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
- ///\r
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value\r
- /// is 1.\r
- ///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bit 7] Performance Monitoring Available (R).\r
- ///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
- ///\r
- /// [Bit 11] Branch Trace Storage Unavailable (RO).\r
- ///\r
- UINT32 BTS:1;\r
- ///\r
- /// [Bit 12] Processor Event Based Sampling Unavailable (RO).\r
- ///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
- ///\r
- /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).\r
- ///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
- ///\r
- /// [Bit 18] ENABLE MONITOR FSM (R/W).\r
- ///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
- ///\r
- /// [Bit 22] Limit CPUID Maxval (R/W).\r
- ///\r
- UINT32 LimitCpuidMaxval:1;\r
- ///\r
- /// [Bit 23] xTPR Message Disable (R/W).\r
- ///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
- ///\r
- /// [Bit 34] XD Bit Disable (R/W).\r
- ///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
- ///\r
- /// [Bit 38] Turbo Mode Disable (R/W).\r
- ///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;\r
-\r
-\r
-/**\r
- Package.\r
-\r
- @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);\r
- AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
-**/\r
-#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved1:16;\r
- ///\r
- /// [Bits 23:16] Temperature Target (R).\r
- ///\r
- UINT32 TemperatureTarget:8;\r
- ///\r
- /// [Bits 29:24] Target Offset (R/W).\r
- ///\r
- UINT32 TargetOffset:6;\r
- UINT32 Reserved2:2;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r
-\r
-\r
-/**\r
- Miscellaneous Feature Control (R/W).\r
-\r
- @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the\r
- /// L1 data cache prefetcher.\r
- ///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
- ///\r
- /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
- /// L2 hardware prefetcher.\r
- ///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;\r
-\r
-\r
-/**\r
- Shared. Offcore Response Event Select Register (R/W).\r
-\r
- @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);\r
- AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
-**/\r
-#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r
-\r
-\r
-/**\r
- Shared. Offcore Response Event Select Register (R/W).\r
-\r
- @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);\r
- AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
-**/\r
-#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r
-\r
-\r
-/**\r
- Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).\r
-\r
- @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);\r
- AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
-**/\r
-#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- UINT32 Reserved:1;\r
- ///\r
- /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active\r
- /// processor cores which operates under the maximum ratio limit for group\r
- /// 0.\r
- ///\r
- UINT32 MaxCoresGroup0:7;\r
- ///\r
- /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo\r
- /// ratio limit when the number of active cores are not more than the\r
- /// group 0 maximum core count.\r
- ///\r
- UINT32 MaxRatioLimitGroup0:8;\r
- ///\r
- /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1\r
- /// Group 1, which includes the specified number of additional cores plus\r
- /// the cores in group 0, operates under the group 1 turbo max ratio limit\r
- /// = "group 0 Max ratio limit" - "group ratio delta for group 1".\r
- ///\r
- UINT32 MaxIncrementalCoresGroup1:5;\r
- ///\r
- /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned\r
- /// integer specifying the ratio decrement relative to the Max ratio limit\r
- /// to Group 0.\r
- ///\r
- UINT32 DeltaRatioGroup1:3;\r
- ///\r
- /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2\r
- /// Group 2, which includes the specified number of additional cores plus\r
- /// all the cores in group 1, operates under the group 2 turbo max ratio\r
- /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".\r
- ///\r
- UINT32 MaxIncrementalCoresGroup2:5;\r
- ///\r
- /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned\r
- /// integer specifying the ratio decrement relative to the Max ratio limit\r
- /// for Group 1.\r
- ///\r
- UINT32 DeltaRatioGroup2:3;\r
- ///\r
- /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3\r
- /// Group 3, which includes the specified number of additional cores plus\r
- /// all the cores in group 2, operates under the group 3 turbo max ratio\r
- /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".\r
- ///\r
- UINT32 MaxIncrementalCoresGroup3:5;\r
- ///\r
- /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned\r
- /// integer specifying the ratio decrement relative to the Max ratio limit\r
- /// for Group 2.\r
- ///\r
- UINT32 DeltaRatioGroup3:3;\r
- ///\r
- /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4\r
- /// Group 4, which includes the specified number of additional cores plus\r
- /// all the cores in group 3, operates under the group 4 turbo max ratio\r
- /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".\r
- ///\r
- UINT32 MaxIncrementalCoresGroup4:5;\r
- ///\r
- /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned\r
- /// integer specifying the ratio decrement relative to the Max ratio limit\r
- /// for Group 3.\r
- ///\r
- UINT32 DeltaRatioGroup4:3;\r
- ///\r
- /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5\r
- /// Group 5, which includes the specified number of additional cores plus\r
- /// all the cores in group 4, operates under the group 5 turbo max ratio\r
- /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".\r
- ///\r
- UINT32 MaxIncrementalCoresGroup5:5;\r
- ///\r
- /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned\r
- /// integer specifying the ratio decrement relative to the Max ratio limit\r
- /// for Group 4.\r
- ///\r
- UINT32 DeltaRatioGroup5:3;\r
- ///\r
- /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6\r
- /// Group 6, which includes the specified number of additional cores plus\r
- /// all the cores in group 5, operates under the group 6 turbo max ratio\r
- /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".\r
- ///\r
- UINT32 MaxIncrementalCoresGroup6:5;\r
- ///\r
- /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned\r
- /// integer specifying the ratio decrement relative to the Max ratio limit\r
- /// for Group 5.\r
- ///\r
- UINT32 DeltaRatioGroup6:3;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Thread. Last Branch Record Filtering Select Register (R/W).\r
-\r
- @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);\r
- AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
-**/\r
-#define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r
-\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] CPL_EQ_0.\r
- ///\r
- UINT32 CPL_EQ_0:1;\r
- ///\r
- /// [Bit 1] CPL_NEQ_0.\r
- ///\r
- UINT32 CPL_NEQ_0:1;\r
- ///\r
- /// [Bit 2] JCC.\r
- ///\r
- UINT32 JCC:1;\r
- ///\r
- /// [Bit 3] NEAR_REL_CALL.\r
- ///\r
- UINT32 NEAR_REL_CALL:1;\r
- ///\r
- /// [Bit 4] NEAR_IND_CALL.\r
- ///\r
- UINT32 NEAR_IND_CALL:1;\r
- ///\r
- /// [Bit 5] NEAR_RET.\r
- ///\r
- UINT32 NEAR_RET:1;\r
- ///\r
- /// [Bit 6] NEAR_IND_JMP.\r
- ///\r
- UINT32 NEAR_IND_JMP:1;\r
- ///\r
- /// [Bit 7] NEAR_REL_JMP.\r
- ///\r
- UINT32 NEAR_REL_JMP:1;\r
- ///\r
- /// [Bit 8] FAR_BRANCH.\r
- ///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_LBR_SELECT_REGISTER;\r
-\r
-/**\r
- Thread. Last Branch Record Stack TOS (R/W).\r
-\r
- @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);\r
- AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r
-\r
-\r
-/**\r
- Thread. Last Exception Record From Linear IP (R).\r
-\r
- @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);\r
- @endcode\r
- @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
-**/\r
-#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r
-\r
-\r
-/**\r
- Thread. Last Exception Record To Linear IP (R).\r
-\r
- @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);\r
- @endcode\r
- @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
-**/\r
-#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r
-\r
-\r
-/**\r
- Thread. See Table 2-2.\r
-\r
- @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3\r
- Residency Counter. (R/O).\r
-\r
- @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r
-\r
-\r
-/**\r
- Package. Package C6 Residency Counter. (R/O).\r
-\r
- @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r
-\r
-\r
-/**\r
- Package. Package C7 Residency Counter. (R/O).\r
-\r
- @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r
-\r
-\r
-/**\r
- Module. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0\r
- Residency Counter. (R/O).\r
-\r
- @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r
-\r
-\r
-/**\r
- Module. Module C6 Residency Counter. (R/O).\r
-\r
- @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r
-\r
-\r
-/**\r
- Core. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6\r
- Residency Counter. (R/O).\r
-\r
- @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r
-\r
-\r
-/**\r
- Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
-\r
- @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);\r
- @endcode\r
- @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
-**/\r
-#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
-\r
-\r
-/**\r
- Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r
- 2-2.\r
-\r
- @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);\r
- @endcode\r
- @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
-**/\r
-#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r
-\r
-\r
-/**\r
- Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
-\r
- @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);\r
- @endcode\r
- @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
-**/\r
-#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
- ///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bits 12:8] Package. Energy Status Units Energy related information\r
- /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
- /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
- /// micro-joules).\r
- ///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
- ///\r
- /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
- /// Interfaces.".\r
- ///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. Note: C-state values are processor specific C-state code names,\r
- unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2\r
- Residency Counter. (R/O).\r
-\r
- @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r
-\r
-\r
-/**\r
- Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r
-\r
-\r
-/**\r
- Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
-\r
- @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r
-\r
-\r
-/**\r
- Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
-\r
- @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);\r
- @endcode\r
- @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r
-\r
-\r
-/**\r
- Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
- Domain.".\r
-\r
- @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
- Domain.".\r
-\r
- @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r
-\r
-\r
-/**\r
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r
-\r
-\r
-/**\r
- Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
- RAPL Domain.".\r
-\r
- @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);\r
- @endcode\r
- @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r
-\r
-\r
-/**\r
- Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
-\r
- @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);\r
- AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
-**/\r
-#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r
-\r
-\r
-/**\r
- Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
- fields represent the widest possible range of uncore frequencies. Writing to\r
- these fields allows software to control the minimum and the maximum\r
- frequency that hardware will select.\r
-\r
- @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);\r
- AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
- @endcode\r
-**/\r
-#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
- /// LLC/Ring.\r
- ///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
- ///\r
- /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
- /// possible ratio of the LLC/Ring.\r
- ///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
-\r
-\r
-/**\r
- Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
- RAPL Domains.".\r
-\r
- @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);\r
- AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r
-\r
-\r
-/**\r
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
- Domains.".\r
-\r
- @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);\r
- @endcode\r
- @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r
-\r
-\r
-/**\r
- Package. Base TDP Ratio (R/O) See Table 2-24.\r
-\r
- @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);\r
- @endcode\r
- @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
-**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r
-\r
-\r
-/**\r
- Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.\r
-\r
- @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);\r
- @endcode\r
- @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
-**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r
-\r
-\r
-/**\r
- Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.\r
-\r
- @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);\r
- @endcode\r
- @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
-**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r
-\r
-\r
-/**\r
- Package. ConfigTDP Control (R/W) See Table 2-24.\r
-\r
- @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);\r
- AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
-**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r
-\r
-\r
-/**\r
- Package. ConfigTDP Control (R/W) See Table 2-24.\r
-\r
- @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);\r
- AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);\r
- @endcode\r
- @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
-**/\r
-#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r
-\r
-\r
-/**\r
- Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
- refers to processor core frequency).\r
-\r
- @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)\r
- @param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r
- @param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r
-\r
- <b>Example usage</b>\r
- @code\r
- MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
-\r
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);\r
- AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
- @endcode\r
- @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
-**/\r
-#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r
-\r
-/**\r
- MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS\r
-**/\r
-typedef union {\r
- ///\r
- /// Individual bit fields\r
- ///\r
- struct {\r
- ///\r
- /// [Bit 0] PROCHOT Status (R0).\r
- ///\r
- UINT32 PROCHOT_Status:1;\r
- ///\r
- /// [Bit 1] Thermal Status (R0).\r
- ///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:4;\r
- ///\r
- /// [Bit 6] VR Therm Alert Status (R0).\r
- ///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
- ///\r
- /// [Bit 8] Electrical Design Point Status (R0).\r
- ///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:23;\r
- UINT32 Reserved4:32;\r
- } Bits;\r
- ///\r
- /// All bit fields as a 32-bit value\r
- ///\r
- UINT32 Uint32;\r
- ///\r
- /// All bit fields as a 64-bit value\r
- ///\r
- UINT64 Uint64;\r
-} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;\r
-\r
-#endif\r
/** @file\r
-SMRAM Save State Map Definitions.\r
-\r
-SMRAM Save State Map definitions based on contents of the\r
-Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- Volume 3C, Section 34.4 SMRAM\r
- Volume 3C, Section 34.5 SMI Handler Execution Environment\r
- Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs\r
-\r
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
+ Wrapper header file to include <Register/Intel/SmramSaveStateMap.h> in MdePkg.\r
\r
+ Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#ifndef __SMRAM_SAVE_STATE_MAP_H__\r
#define __SMRAM_SAVE_STATE_MAP_H__\r
\r
-///\r
-/// Default SMBASE address\r
-///\r
-#define SMM_DEFAULT_SMBASE 0x30000\r
-\r
-///\r
-/// Offset of SMM handler from SMBASE\r
-///\r
-#define SMM_HANDLER_OFFSET 0x8000\r
-\r
-///\r
-/// Offset of SMRAM Save State Map from SMBASE\r
-///\r
-#define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00\r
-\r
-#pragma pack (1)\r
-\r
-///\r
-/// 32-bit SMRAM Save State Map\r
-///\r
-typedef struct {\r
- UINT8 Reserved[0x200]; // 7c00h\r
- // Padded an extra 0x200 bytes so 32-bit and 64-bit\r
- // SMRAM Save State Maps are the same size\r
- UINT8 Reserved1[0xf8]; // 7e00h\r
- UINT32 SMBASE; // 7ef8h\r
- UINT32 SMMRevId; // 7efch\r
- UINT16 IORestart; // 7f00h\r
- UINT16 AutoHALTRestart; // 7f02h\r
- UINT8 Reserved2[0x9C]; // 7f08h\r
- UINT32 IOMemAddr; // 7fa0h\r
- UINT32 IOMisc; // 7fa4h\r
- UINT32 _ES; // 7fa8h\r
- UINT32 _CS; // 7fach\r
- UINT32 _SS; // 7fb0h\r
- UINT32 _DS; // 7fb4h\r
- UINT32 _FS; // 7fb8h\r
- UINT32 _GS; // 7fbch\r
- UINT32 Reserved3; // 7fc0h\r
- UINT32 _TR; // 7fc4h\r
- UINT32 _DR7; // 7fc8h\r
- UINT32 _DR6; // 7fcch\r
- UINT32 _EAX; // 7fd0h\r
- UINT32 _ECX; // 7fd4h\r
- UINT32 _EDX; // 7fd8h\r
- UINT32 _EBX; // 7fdch\r
- UINT32 _ESP; // 7fe0h\r
- UINT32 _EBP; // 7fe4h\r
- UINT32 _ESI; // 7fe8h\r
- UINT32 _EDI; // 7fech\r
- UINT32 _EIP; // 7ff0h\r
- UINT32 _EFLAGS; // 7ff4h\r
- UINT32 _CR3; // 7ff8h\r
- UINT32 _CR0; // 7ffch\r
-} SMRAM_SAVE_STATE_MAP32;\r
-\r
-///\r
-/// 64-bit SMRAM Save State Map\r
-///\r
-typedef struct {\r
- UINT8 Reserved1[0x1d0]; // 7c00h\r
- UINT32 GdtBaseHiDword; // 7dd0h\r
- UINT32 LdtBaseHiDword; // 7dd4h\r
- UINT32 IdtBaseHiDword; // 7dd8h\r
- UINT8 Reserved2[0xc]; // 7ddch\r
- UINT64 IO_EIP; // 7de8h\r
- UINT8 Reserved3[0x50]; // 7df0h\r
- UINT32 _CR4; // 7e40h\r
- UINT8 Reserved4[0x48]; // 7e44h\r
- UINT32 GdtBaseLoDword; // 7e8ch\r
- UINT32 Reserved5; // 7e90h\r
- UINT32 IdtBaseLoDword; // 7e94h\r
- UINT32 Reserved6; // 7e98h\r
- UINT32 LdtBaseLoDword; // 7e9ch\r
- UINT8 Reserved7[0x38]; // 7ea0h\r
- UINT64 EptVmxControl; // 7ed8h\r
- UINT32 EnEptVmxControl; // 7ee0h\r
- UINT8 Reserved8[0x14]; // 7ee4h\r
- UINT32 SMBASE; // 7ef8h\r
- UINT32 SMMRevId; // 7efch\r
- UINT16 IORestart; // 7f00h\r
- UINT16 AutoHALTRestart; // 7f02h\r
- UINT8 Reserved9[0x18]; // 7f04h\r
- UINT64 _R15; // 7f1ch\r
- UINT64 _R14;\r
- UINT64 _R13;\r
- UINT64 _R12;\r
- UINT64 _R11;\r
- UINT64 _R10;\r
- UINT64 _R9;\r
- UINT64 _R8;\r
- UINT64 _RAX; // 7f5ch\r
- UINT64 _RCX;\r
- UINT64 _RDX;\r
- UINT64 _RBX;\r
- UINT64 _RSP;\r
- UINT64 _RBP;\r
- UINT64 _RSI;\r
- UINT64 _RDI;\r
- UINT64 IOMemAddr; // 7f9ch\r
- UINT32 IOMisc; // 7fa4h\r
- UINT32 _ES; // 7fa8h\r
- UINT32 _CS;\r
- UINT32 _SS;\r
- UINT32 _DS;\r
- UINT32 _FS;\r
- UINT32 _GS;\r
- UINT32 _LDTR; // 7fc0h\r
- UINT32 _TR;\r
- UINT64 _DR7; // 7fc8h\r
- UINT64 _DR6;\r
- UINT64 _RIP; // 7fd8h\r
- UINT64 IA32_EFER; // 7fe0h\r
- UINT64 _RFLAGS; // 7fe8h\r
- UINT64 _CR3; // 7ff0h\r
- UINT64 _CR0; // 7ff8h\r
-} SMRAM_SAVE_STATE_MAP64;\r
-\r
-///\r
-/// Union of 32-bit and 64-bit SMRAM Save State Maps\r
-///\r
-typedef union {\r
- SMRAM_SAVE_STATE_MAP32 x86;\r
- SMRAM_SAVE_STATE_MAP64 x64;\r
-} SMRAM_SAVE_STATE_MAP;\r
-\r
-///\r
-/// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map\r
-///\r
-#define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC 0x30004\r
-\r
-///\r
-/// SMRAM Save State Map IOMisc I/O Length Values\r
-///\r
-#define SMM_IO_LENGTH_BYTE 0x01\r
-#define SMM_IO_LENGTH_WORD 0x02\r
-#define SMM_IO_LENGTH_DWORD 0x04\r
-\r
-///\r
-/// SMRAM Save State Map IOMisc I/O Instruction Type Values\r
-///\r
-#define SMM_IO_TYPE_IN_IMMEDIATE 0x9\r
-#define SMM_IO_TYPE_IN_DX 0x1\r
-#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8\r
-#define SMM_IO_TYPE_OUT_DX 0x0\r
-#define SMM_IO_TYPE_INS 0x3\r
-#define SMM_IO_TYPE_OUTS 0x2\r
-#define SMM_IO_TYPE_REP_INS 0x7\r
-#define SMM_IO_TYPE_REP_OUTS 0x6\r
-\r
-///\r
-/// SMRAM Save State Map IOMisc structure\r
-///\r
-typedef union {\r
- struct {\r
- UINT32 SmiFlag:1;\r
- UINT32 Length:3;\r
- UINT32 Type:4;\r
- UINT32 Reserved1:8;\r
- UINT32 Port:16;\r
- } Bits;\r
- UINT32 Uint32;\r
-} SMRAM_SAVE_STATE_IOMISC;\r
-\r
-#pragma pack ()\r
+#include <Register/Intel/SmramSaveStateMap.h>\r
\r
#endif\r
/** @file\r
- STM API definition\r
+ Wrapper header file to include <Register/Intel/StmApi.h> in MdePkg.\r
\r
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- SMI Transfer Monitor (STM) User Guide Revision 1.00\r
-\r
**/\r
\r
#ifndef _STM_API_H_\r
#define _STM_API_H_\r
\r
-#include <Register/StmStatusCode.h>\r
-#include <Register/StmResourceDescriptor.h>\r
-#include <Register/ArchitecturalMsr.h>\r
-\r
-#pragma pack (1)\r
-\r
-/**\r
- STM Header Structures\r
-**/\r
-\r
-typedef struct {\r
- UINT32 Intel64ModeSupported :1; ///> bitfield\r
- UINT32 EptSupported :1; ///> bitfield\r
- UINT32 Reserved :30; ///> must be 0\r
-} STM_FEAT;\r
-\r
-#define STM_SPEC_VERSION_MAJOR 1\r
-#define STM_SPEC_VERSION_MINOR 0\r
-\r
-typedef struct {\r
- UINT8 StmSpecVerMajor;\r
- UINT8 StmSpecVerMinor;\r
- ///\r
- /// Must be zero\r
- ///\r
- UINT16 Reserved;\r
- UINT32 StaticImageSize;\r
- UINT32 PerProcDynamicMemorySize;\r
- UINT32 AdditionalDynamicMemorySize;\r
- STM_FEAT StmFeatures;\r
- UINT32 NumberOfRevIDs;\r
- UINT32 StmSmmRevID[1];\r
- ///\r
- /// The total STM_HEADER should be 4K.\r
- ///\r
-} SOFTWARE_STM_HEADER;\r
-\r
-typedef struct {\r
- MSEG_HEADER HwStmHdr;\r
- SOFTWARE_STM_HEADER SwStmHdr;\r
-} STM_HEADER;\r
-\r
-\r
-/**\r
- VMCALL API Numbers\r
- API number convention: BIOS facing VMCALL interfaces have bit 16 clear\r
-**/\r
-\r
-/**\r
- StmMapAddressRange enables a SMM guest to create a non-1:1 virtual to\r
- physical mapping of an address range into the SMM guest's virtual\r
- memory space.\r
-\r
- @param EAX #STM_API_MAP_ADDRESS_RANGE (0x00000001)\r
- @param EBX Low 32 bits of physical address of caller allocated\r
- STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure.\r
- @param ECX High 32 bits of physical address of caller allocated\r
- STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is\r
- clear (0), ECX must be 0.\r
-\r
- @note All fields of STM_MAP_ADDRESS_RANGE_DESCRIPTOR are inputs only. They\r
- are not modified by StmMapAddressRange.\r
-\r
- @retval CF 0\r
- No error, EAX set to STM_SUCCESS.\r
- The memory range was mapped as requested.\r
- @retval CF 1\r
- An error occurred, EAX holds relevant error value.\r
- @retval EAX #ERROR_STM_SECURITY_VIOLATION\r
- The requested mapping contains a protected resource.\r
- @retval EAX #ERROR_STM_CACHE_TYPE_NOT_SUPPORTED\r
- The requested cache type could not be satisfied.\r
- @retval EAX #ERROR_STM_PAGE_NOT_FOUND\r
- Page count must not be zero.\r
- @retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED\r
- STM supports EPT and has not implemented StmMapAddressRange().\r
- @retval EAX #ERROR_STM_UNSPECIFIED\r
- An unspecified error occurred.\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_MAP_ADDRESS_RANGE 0x00000001\r
-\r
-/**\r
- STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL\r
-**/\r
-typedef struct {\r
- UINT64 PhysicalAddress;\r
- UINT64 VirtualAddress;\r
- UINT32 PageCount;\r
- UINT32 PatCacheType;\r
-} STM_MAP_ADDRESS_RANGE_DESCRIPTOR;\r
-\r
-/**\r
- Define values for PatCacheType field of #STM_MAP_ADDRESS_RANGE_DESCRIPTOR\r
- @{\r
-**/\r
-#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_ST_UC 0x00\r
-#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WC 0x01\r
-#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WT 0x04\r
-#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WP 0x05\r
-#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WB 0x06\r
-#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_UC 0x07\r
-#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_FOLLOW_MTRR 0xFFFFFFFF\r
-/// @}\r
-\r
-/**\r
- StmUnmapAddressRange enables a SMM guest to remove mappings from its page\r
- table.\r
-\r
- If TXT_PROCESSOR_SMM_DESCRIPTOR.EptEnabled bit is set by the STM, BIOS can\r
- control its own page tables. In this case, the STM implementation may\r
- optionally return ERROR_STM_FUNCTION_NOT_SUPPORTED.\r
-\r
- @param EAX #STM_API_UNMAP_ADDRESS_RANGE (0x00000002)\r
- @param EBX Low 32 bits of virtual address of caller allocated\r
- STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure.\r
- @param ECX High 32 bits of virtual address of caller allocated\r
- STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is\r
- clear (0), ECX must be zero.\r
-\r
- @retval CF 0\r
- No error, EAX set to STM_SUCCESS. The memory range was unmapped\r
- as requested.\r
- @retval CF 1\r
- An error occurred, EAX holds relevant error value.\r
- @retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED\r
- STM supports EPT and has not implemented StmUnmapAddressRange().\r
- @retval EAX #ERROR_STM_UNSPECIFIED\r
- An unspecified error occurred.\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002\r
-\r
-/**\r
- STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL\r
-**/\r
-typedef struct {\r
- UINT64 VirtualAddress;\r
- UINT32 Length;\r
-} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;\r
-\r
-\r
-/**\r
- Since the normal OS environment runs with a different set of page tables than\r
- the SMM guest, virtual mappings will certainly be different. In order to do a\r
- guest virtual to host physical translation of an address from the normal OS\r
- code (EIP for example), it is necessary to walk the page tables governing the\r
- OS page mappings. Since the SMM guest has no direct access to the page tables,\r
- it must ask the STM to do this page table walk. This is supported via the\r
- StmAddressLookup VMCALL. All OS page table formats need to be supported,\r
- (e.g. PAE, PSE, Intel64, EPT, etc.)\r
-\r
- StmAddressLookup takes a CR3 value and a virtual address from the interrupted\r
- code as input and returns the corresponding physical address. It also\r
- optionally maps the physical address into the SMM guest's virtual address\r
- space. This new mapping persists ONLY for the duration of the SMI and if\r
- needed in subsequent SMIs it must be remapped. PAT cache types follow the\r
- interrupted environment's page table.\r
-\r
- If EPT is enabled, OS CR3 only provides guest physical address information,\r
- but the SMM guest might also need to know the host physical address. Since\r
- SMM does not have direct access rights to EPT (it is protected by the STM),\r
- SMM can input InterruptedEptp to let STM help to walk through it, and output\r
- the host physical address.\r
-\r
- @param EAX #STM_API_ADDRESS_LOOKUP (0x00000003)\r
- @param EBX Low 32 bits of virtual address of caller allocated\r
- STM_ADDRESS_LOOKUP_DESCRIPTOR structure.\r
- @param ECX High 32 bits of virtual address of caller allocated\r
- STM_ADDRESS_LOOKUP_DESCRIPTOR structure. If Intel64Mode is\r
- clear (0), ECX must be zero.\r
-\r
- @retval CF 0\r
- No error, EAX set to STM_SUCCESS. PhysicalAddress contains the\r
- host physical address determined by walking the interrupted SMM\r
- guest's page tables. SmmGuestVirtualAddress contains the SMM\r
- guest's virtual mapping of the requested address.\r
- @retval CF 1\r
- An error occurred, EAX holds relevant error value.\r
- @retval EAX #ERROR_STM_SECURITY_VIOLATION\r
- The requested page was a protected page.\r
- @retval EAX #ERROR_STM_PAGE_NOT_FOUND\r
- The requested virtual address did not exist in the page given\r
- page table.\r
- @retval EAX #ERROR_STM_BAD_CR3\r
- The CR3 input was invalid. CR3 values must be from one of the\r
- interrupted guest, or from the interrupted guest of another\r
- processor.\r
- @retval EAX #ERROR_STM_PHYSICAL_OVER_4G\r
- The resulting physical address is greater than 4G and no virtual\r
- address was supplied. The STM could not determine what address\r
- within the SMM guest's virtual address space to do the mapping.\r
- STM_ADDRESS_LOOKUP_DESCRIPTOR field PhysicalAddress contains the\r
- physical address determined by walking the interrupted\r
- environment's page tables.\r
- @retval EAX #ERROR_STM_VIRTUAL_SPACE_TOO_SMALL\r
- A specific virtual mapping was requested, but\r
- SmmGuestVirtualAddress + Length exceeds 4G and the SMI handler\r
- is running in 32 bit mode.\r
- @retval EAX #ERROR_STM_UNSPECIFIED\r
- An unspecified error occurred.\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_ADDRESS_LOOKUP 0x00000003\r
-\r
-/**\r
- STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL\r
-**/\r
-typedef struct {\r
- UINT64 InterruptedGuestVirtualAddress;\r
- UINT32 Length;\r
- UINT64 InterruptedCr3;\r
- UINT64 InterruptedEptp;\r
- UINT32 MapToSmmGuest:2;\r
- UINT32 InterruptedCr4Pae:1;\r
- UINT32 InterruptedCr4Pse:1;\r
- UINT32 InterruptedIa32eMode:1;\r
- UINT32 Reserved1:27;\r
- UINT32 Reserved2;\r
- UINT64 PhysicalAddress;\r
- UINT64 SmmGuestVirtualAddress;\r
-} STM_ADDRESS_LOOKUP_DESCRIPTOR;\r
-\r
-/**\r
- Define values for the MapToSmmGuest field of #STM_ADDRESS_LOOKUP_DESCRIPTOR\r
- @{\r
-**/\r
-#define STM_ADDRESS_LOOKUP_DESCRIPTOR_DO_NOT_MAP 0\r
-#define STM_ADDRESS_LOOKUP_DESCRIPTOR_ONE_TO_ONE 1\r
-#define STM_ADDRESS_LOOKUP_DESCRIPTOR_VIRTUAL_ADDRESS_SPECIFIED 3\r
-/// @}\r
-\r
-\r
-/**\r
- When returning from a protection exception (see section 6.2), the SMM guest\r
- can instruct the STM to take one of two paths. It can either request a value\r
- be logged to the TXT.ERRORCODE register and subsequently reset the machine\r
- (indicating it couldn't resolve the problem), or it can request that the STM\r
- resume the SMM guest again with the specified register state.\r
-\r
- Unlike other VMCALL interfaces, StmReturnFromProtectionException behaves more\r
- like a jump or an IRET instruction than a "call". It does not return directly\r
- to the caller, but indirectly to a different location specified on the\r
- caller's stack (see section 6.2) or not at all.\r
-\r
- If the SMM guest STM protection exception handler itself causes a protection\r
- exception (e.g. a single nested exception), or more than 100 un-nested\r
- exceptions occur within the scope of a single SMI event, the STM must write\r
- STM_CRASH_PROTECTION_EXCEPTION_FAILURE to the TXT.ERRORCODE register and\r
- assert TXT.CMD.SYS_RESET. The reason for these restrictions is to simplify\r
- the code requirements while still enabling a reasonable debugging capability.\r
-\r
- @param EAX #STM_API_RETURN_FROM_PROTECTION_EXCEPTION (0x00000004)\r
- @param EBX If 0, resume SMM guest using register state found on exception\r
- stack. If in range 0x01..0x0F, EBX contains a BIOS error code\r
- which the STM must record in the TXT.ERRORCODE register and\r
- subsequently reset the system via TXT.CMD.SYS_RESET. The value\r
- of the TXT.ERRORCODE register is calculated as follows:\r
-\r
- TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC\r
-\r
- Values 0x10..0xFFFFFFFF are reserved, do not use.\r
-\r
-**/\r
-#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004\r
-\r
-\r
-/**\r
- VMCALL API Numbers\r
- API number convention: MLE facing VMCALL interfaces have bit 16 set.\r
-\r
- The STM configuration lifecycle is as follows:\r
- 1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked).\r
- 2. MLE invokes #STM_API_INITIALIZE_PROTECTION VMCALL to prepare STM for\r
- setup of initial protection profile. This is done on a single CPU and\r
- has global effect.\r
- 3. MLE invokes #STM_API_PROTECT_RESOURCE VMCALL to define the initial\r
- protection profile. The protection profile is global across all CPUs.\r
- 4. MLE invokes #STM_API_START VMCALL to enable the STM to begin receiving\r
- SMI events. This must be done on every logical CPU.\r
- 5. MLE may invoke #STM_API_PROTECT_RESOURCE VMCALL or\r
- #STM_API_UNPROTECT_RESOURCE VMCALL during runtime as many times as\r
- necessary.\r
- 6. MLE invokes #STM_API_STOP VMCALL to disable the STM. SMI is again masked\r
- following #STM_API_STOP VMCALL.\r
-**/\r
-\r
-/**\r
- StartStmVmcall() is used to configure an STM that is present in MSEG. SMIs\r
- should remain disabled from the invocation of GETSEC[SENTER] until they are\r
- re-enabled by StartStmVMCALL(). When StartStmVMCALL() returns, SMI is\r
- enabled and the STM has been started and is active. Prior to invoking\r
- StartStmVMCALL(), the MLE root should first invoke\r
- InitializeProtectionVMCALL() followed by as many iterations of\r
- ProtectResourceVMCALL() as necessary to establish the initial protection\r
- profile. StartStmVmcall() must be invoked on all processor threads.\r
-\r
- @param EAX #STM_API_START (0x00010001)\r
- @param EDX STM configuration options. These provide the MLE with the\r
- ability to pass configuration parameters to the STM.\r
-\r
- @retval CF 0\r
- No error, EAX set to STM_SUCCESS. The STM has been configured\r
- and is now active and the guarding all requested resources.\r
- @retval CF 1\r
- An error occurred, EAX holds relevant error value.\r
- @retval EAX #ERROR_STM_ALREADY_STARTED\r
- The STM is already configured and active. STM remains active and\r
- guarding previously enabled resource list.\r
- @retval EAX #ERROR_STM_WITHOUT_SMX_UNSUPPORTED\r
- The StartStmVMCALL() was invoked from VMX root mode, but outside\r
- of SMX. This error code indicates the STM or platform does not\r
- support the STM outside of SMX. The SMI handler remains active\r
- and operates in legacy mode. See Appendix C\r
- @retval EAX #ERROR_STM_UNSUPPORTED_MSR_BIT\r
- The CPU doesn't support the MSR bit. The STM is not active.\r
- @retval EAX #ERROR_STM_UNSPECIFIED\r
- An unspecified error occurred.\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_START (BIT16 | 1)\r
-\r
-/**\r
- Bit values for EDX input parameter to #STM_API_START VMCALL\r
- @{\r
-**/\r
-#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF BIT0\r
-/// @}\r
-\r
-\r
-/**\r
- The StopStmVMCALL() is invoked by the MLE to teardown an active STM. This is\r
- normally done as part of a full teardown of the SMX environment when the\r
- system is being shut down. At the time the call is invoked, SMI is enabled\r
- and the STM is active. When the call returns, the STM has been stopped and\r
- all STM context is discarded and SMI is disabled.\r
-\r
- @param EAX #STM_API_STOP (0x00010002)\r
-\r
- @retval CF 0\r
- No error, EAX set to STM_SUCCESS. The STM has been stopped and\r
- is no longer processing SMI events. SMI is blocked.\r
- @retval CF 1\r
- An error occurred, EAX holds relevant error value.\r
- @retval EAX #ERROR_STM_STOPPED\r
- The STM was not active.\r
- @retval EAX #ERROR_STM_UNSPECIFIED\r
- An unspecified error occurred.\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_STOP (BIT16 | 2)\r
-\r
-\r
-/**\r
- The ProtectResourceVMCALL() is invoked by the MLE root to request protection\r
- of specific resources. The request is defined by a STM_RESOURCE_LIST, which\r
- may contain more than one resource descriptor. Each resource descriptor is\r
- processed separately by the STM. Whether or not protection for any specific\r
- resource is granted is returned by the STM via the ReturnStatus bit in the\r
- associated STM_RSC_DESC_HEADER.\r
-\r
- @param EAX #STM_API_PROTECT_RESOURCE (0x00010003)\r
- @param EBX Low 32 bits of physical address of caller allocated\r
- STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,\r
- making the buffer 4K aligned.\r
- @param ECX High 32 bits of physical address of caller allocated\r
- STM_RESOURCE_LIST.\r
-\r
- @note All fields of STM_RESOURCE_LIST are inputs only, except for the\r
- ReturnStatus bit. On input, the ReturnStatus bit must be clear. On\r
- return, the ReturnStatus bit is set for each resource request granted,\r
- and clear for each resource request denied. There are no other fields\r
- modified by ProtectResourceVMCALL(). The STM_RESOURCE_LIST must be\r
- contained entirely within a single 4K page.\r
-\r
- @retval CF 0\r
- No error, EAX set to STM_SUCCESS. The STM has successfully\r
- merged the entire protection request into the active protection\r
- profile. There is therefore no need to check the ReturnStatus\r
- bits in the STM_RESOURCE_LIST.\r
- @retval CF 1\r
- An error occurred, EAX holds relevant error value.\r
- @retval EAX #ERROR_STM_UNPROTECTABLE_RESOURCE\r
- At least one of the requested resource protections intersects a\r
- BIOS required resource. Therefore, the caller must walk through\r
- the STM_RESOURCE_LIST to determine which of the requested\r
- resources was not granted protection. The entire list must be\r
- traversed since there may be multiple failures.\r
- @retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST\r
- The resource list could not be parsed correctly, or did not\r
- terminate before crossing a 4K page boundary. The caller must\r
- walk through the STM_RESOURCE_LIST to determine which of the\r
- requested resources was not granted protection. The entire list\r
- must be traversed since there may be multiple failures.\r
- @retval EAX #ERROR_STM_OUT_OF_RESOURCES\r
- The STM has encountered an internal error and cannot complete\r
- the request.\r
- @retval EAX #ERROR_STM_UNSPECIFIED\r
- An unspecified error occurred.\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_PROTECT_RESOURCE (BIT16 | 3)\r
-\r
-\r
-/**\r
- The UnProtectResourceVMCALL() is invoked by the MLE root to request that the\r
- STM allow the SMI handler access to the specified resources.\r
-\r
- @param EAX #STM_API_UNPROTECT_RESOURCE (0x00010004)\r
- @param EBX Low 32 bits of physical address of caller allocated\r
- STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,\r
- making the buffer 4K aligned.\r
- @param ECX High 32 bits of physical address of caller allocated\r
- STM_RESOURCE_LIST.\r
-\r
- @note All fields of STM_RESOURCE_LIST are inputs only, except for the\r
- ReturnStatus bit. On input, the ReturnStatus bit must be clear. On\r
- return, the ReturnStatus bit is set for each resource processed. For\r
- a properly formed STM_RESOURCE_LIST, this should be all resources\r
- listed. There are no other fields modified by\r
- UnProtectResourceVMCALL(). The STM_RESOURCE_LIST must be contained\r
- entirely within a single 4K page.\r
-\r
- @retval CF 0\r
- No error, EAX set to STM_SUCCESS. The requested resources are\r
- not being guarded by the STM.\r
- @retval CF 1\r
- An error occurred, EAX holds relevant error value.\r
- @retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST\r
- The resource list could not be parsed correctly, or did not\r
- terminate before crossing a 4K page boundary. The caller must\r
- walk through the STM_RESOURCE_LIST to determine which of the\r
- requested resources were not able to be unprotected. The entire\r
- list must be traversed since there may be multiple failures.\r
- @retval EAX #ERROR_STM_UNSPECIFIED\r
- An unspecified error occurred.\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_UNPROTECT_RESOURCE (BIT16 | 4)\r
-\r
-\r
-/**\r
- The GetBiosResourcesVMCALL() is invoked by the MLE root to request the list\r
- of BIOS required resources from the STM.\r
-\r
- @param EAX #STM_API_GET_BIOS_RESOURCES (0x00010005)\r
- @param EBX Low 32 bits of physical address of caller allocated destination\r
- buffer. Bits 11:0 are ignored and assumed to be zero, making the\r
- buffer 4K aligned.\r
- @param ECX High 32 bits of physical address of caller allocated destination\r
- buffer.\r
- @param EDX Indicates which page of the BIOS resource list to copy into the\r
- destination buffer. The first page is indicated by 0, the second\r
- page by 1, etc.\r
-\r
- @retval CF 0\r
- No error, EAX set to STM_SUCCESS. The destination buffer\r
- contains the BIOS required resources. If the page retrieved is\r
- the last page, EDX will be cleared to 0. If there are more pages\r
- to retrieve, EDX is incremented to the next page index. Calling\r
- software should iterate on GetBiosResourcesVMCALL() until EDX is\r
- returned cleared to 0.\r
- @retval CF 1\r
- An error occurred, EAX holds relevant error value.\r
- @retval EAX #ERROR_STM_PAGE_NOT_FOUND\r
- The page index supplied in EDX input was out of range.\r
- @retval EAX #ERROR_STM_UNSPECIFIED\r
- An unspecified error occurred.\r
- @retval EDX Page index of next page to read. A return of EDX=0 signifies\r
- that the entire list has been read.\r
- @note EDX is both an input and an output register.\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_GET_BIOS_RESOURCES (BIT16 | 5)\r
-\r
-\r
-/**\r
- The ManageVmcsDatabaseVMCALL() is invoked by the MLE root to add or remove an\r
- MLE guest (including the MLE root) from the list of protected domains.\r
-\r
- @param EAX #STM_API_MANAGE_VMCS_DATABASE (0x00010006)\r
- @param EBX Low 32 bits of physical address of caller allocated\r
- STM_VMCS_DATABASE_REQUEST. Bits 11:0 are ignored and assumed to\r
- be zero, making the buffer 4K aligned.\r
- @param ECX High 32 bits of physical address of caller allocated\r
- STM_VMCS_DATABASE_REQUEST.\r
-\r
- @note All fields of STM_VMCS_DATABASE_REQUEST are inputs only. They are not\r
- modified by ManageVmcsDatabaseVMCALL().\r
-\r
- @retval CF 0\r
- No error, EAX set to STM_SUCCESS.\r
- @retval CF 1\r
- An error occurred, EAX holds relevant error value.\r
- @retval EAX #ERROR_STM_INVALID_VMCS\r
- Indicates a request to remove a VMCS from the database was made,\r
- but the referenced VMCS was not found in the database.\r
- @retval EAX #ERROR_STM_VMCS_PRESENT\r
- Indicates a request to add a VMCS to the database was made, but\r
- the referenced VMCS was already present in the database.\r
- @retval EAX #ERROR_INVALID_PARAMETER\r
- Indicates non-zero reserved field.\r
- @retval EAX #ERROR_STM_UNSPECIFIED\r
- An unspecified error occurred\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_MANAGE_VMCS_DATABASE (BIT16 | 6)\r
-\r
-/**\r
- STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL\r
-**/\r
-typedef struct {\r
- ///\r
- /// bits 11:0 are reserved and must be 0\r
- ///\r
- UINT64 VmcsPhysPointer;\r
- UINT32 DomainType :4;\r
- UINT32 XStatePolicy :2;\r
- UINT32 DegradationPolicy :4;\r
- ///\r
- /// Must be 0\r
- ///\r
- UINT32 Reserved1 :22;\r
- UINT32 AddOrRemove;\r
-} STM_VMCS_DATABASE_REQUEST;\r
-\r
-/**\r
- Values for the DomainType field of #STM_VMCS_DATABASE_REQUEST\r
- @{\r
-**/\r
-#define DOMAIN_UNPROTECTED 0\r
-#define DOMAIN_DISALLOWED_IO_OUT BIT0\r
-#define DOMAIN_DISALLOWED_IO_IN BIT1\r
-#define DOMAIN_INTEGRITY BIT2\r
-#define DOMAIN_CONFIDENTIALITY BIT3\r
-#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY)\r
-#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY)\r
-#define DOMAIN_FULLY_PROT (DOMAIN_FULLY_PROT_OUT_IN | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT)\r
-/// @}\r
-\r
-/**\r
- Values for the XStatePolicy field of #STM_VMCS_DATABASE_REQUEST\r
- @{\r
-**/\r
-#define XSTATE_READWRITE 0x00\r
-#define XSTATE_READONLY 0x01\r
-#define XSTATE_SCRUB 0x03\r
-/// @}\r
-\r
-/**\r
- Values for the AddOrRemove field of #STM_VMCS_DATABASE_REQUEST\r
- @{\r
-**/\r
-#define STM_VMCS_DATABASE_REQUEST_ADD 1\r
-#define STM_VMCS_DATABASE_REQUEST_REMOVE 0\r
-/// @}\r
-\r
-\r
-/**\r
- InitializeProtectionVMCALL() prepares the STM for setup of the initial\r
- protection profile which is subsequently communicated via one or more\r
- invocations of ProtectResourceVMCALL(), prior to invoking StartStmVMCALL().\r
- It is only necessary to invoke InitializeProtectionVMCALL() on one processor\r
- thread. InitializeProtectionVMCALL() does not alter whether SMIs are masked\r
- or unmasked. The STM should return back to the MLE with "Blocking by SMI" set\r
- to 1 in the GUEST_INTERRUPTIBILITY field for the VMCS the STM created for the\r
- MLE guest.\r
-\r
- @param EAX #STM_API_INITIALIZE_PROTECTION (0x00010007)\r
-\r
- @retval CF 0\r
- No error, EAX set to STM_SUCCESS, EBX bits set to indicate STM\r
- capabilities as defined below. The STM has set up an empty\r
- protection profile, except for the resources that it sets up to\r
- protect itself. The STM must not allow the SMI handler to map\r
- any pages from the MSEG Base to the top of TSEG. The STM must\r
- also not allow SMI handler access to those MSRs which the STM\r
- requires for its own protection.\r
- @retval CF 1\r
- An error occurred, EAX holds relevant error value.\r
- @retval EAX #ERROR_STM_ALREADY_STARTED\r
- The STM is already configured and active. The STM remains active\r
- and guarding the previously enabled resource list.\r
- @retval EAX #ERROR_STM_UNPROTECTABLE\r
- The STM determines that based on the platform configuration, the\r
- STM is unable to protect itself. For example, the BIOS required\r
- resource list contains memory pages in MSEG.\r
- @retval EAX #ERROR_STM_UNSPECIFIED\r
- An unspecified error occurred.\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_INITIALIZE_PROTECTION (BIT16 | 7)\r
-\r
-/**\r
- Byte granular support bits returned in EBX from #STM_API_INITIALIZE_PROTECTION\r
- @{\r
-**/\r
-#define STM_RSC_BGI BIT1\r
-#define STM_RSC_BGM BIT2\r
-#define STM_RSC_MSR BIT3\r
-/// @}\r
-\r
-\r
-/**\r
- The ManageEventLogVMCALL() is invoked by the MLE root to control the logging\r
- feature. It consists of several sub-functions to facilitate establishment of\r
- the log itself, configuring what events will be logged, and functions to\r
- start, stop, and clear the log.\r
-\r
- @param EAX #STM_API_MANAGE_EVENT_LOG (0x00010008)\r
- @param EBX Low 32 bits of physical address of caller allocated\r
- STM_EVENT_LOG_MANAGEMENT_REQUEST. Bits 11:0 are ignored and\r
- assumed to be zero, making the buffer 4K aligned.\r
- @param ECX High 32 bits of physical address of caller allocated\r
- STM_EVENT_LOG_MANAGEMENT_REQUEST.\r
-\r
- @retval CF=0\r
- No error, EAX set to STM_SUCCESS.\r
- @retval CF=1\r
- An error occurred, EAX holds relevant error value. See subfunction\r
- descriptions below for details.\r
-\r
- @note All other registers unmodified.\r
-**/\r
-#define STM_API_MANAGE_EVENT_LOG (BIT16 | 8)\r
-\r
-///\r
-/// STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL\r
-///\r
-typedef struct {\r
- UINT32 SubFunctionIndex;\r
- union {\r
- struct {\r
- UINT32 PageCount;\r
- //\r
- // number of elements is PageCount\r
- //\r
- UINT64 Pages[];\r
- } LogBuffer;\r
- //\r
- // bitmap of EVENT_TYPE\r
- //\r
- UINT32 EventEnableBitmap;\r
- } Data;\r
-} STM_EVENT_LOG_MANAGEMENT_REQUEST;\r
-\r
-/**\r
- Defines values for the SubFunctionIndex field of\r
- #STM_EVENT_LOG_MANAGEMENT_REQUEST\r
- @{\r
-**/\r
-#define STM_EVENT_LOG_MANAGEMENT_REQUEST_NEW_LOG 1\r
-#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CONFIGURE_LOG 2\r
-#define STM_EVENT_LOG_MANAGEMENT_REQUEST_START_LOG 3\r
-#define STM_EVENT_LOG_MANAGEMENT_REQUEST_STOP_LOG 4\r
-#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CLEAR_LOG 5\r
-#define STM_EVENT_LOG_MANAGEMENT_REQUEST_DELETE_LOG 6\r
-/// @}\r
-\r
-/**\r
- Log Entry Header\r
-**/\r
-typedef struct {\r
- UINT32 EventSerialNumber;\r
- UINT16 Type;\r
- UINT16 Lock :1;\r
- UINT16 Valid :1;\r
- UINT16 ReadByMle :1;\r
- UINT16 Wrapped :1;\r
- UINT16 Reserved :12;\r
-} LOG_ENTRY_HEADER;\r
-\r
-/**\r
- Enum values for the Type field of #LOG_ENTRY_HEADER\r
-**/\r
-typedef enum {\r
- EvtLogStarted,\r
- EvtLogStopped,\r
- EvtLogInvalidParameterDetected,\r
- EvtHandledProtectionException,\r
- ///\r
- /// unhandled protection exceptions result in reset & cannot be logged\r
- ///\r
- EvtBiosAccessToUnclaimedResource,\r
- EvtMleResourceProtectionGranted,\r
- EvtMleResourceProtectionDenied,\r
- EvtMleResourceUnprotect,\r
- EvtMleResourceUnprotectError,\r
- EvtMleDomainTypeDegraded,\r
- ///\r
- /// add more here\r
- ///\r
- EvtMleMax,\r
- ///\r
- /// Not used\r
- ///\r
- EvtInvalid = 0xFFFFFFFF,\r
-} EVENT_TYPE;\r
-\r
-typedef struct {\r
- UINT32 Reserved;\r
-} ENTRY_EVT_LOG_STARTED;\r
-\r
-typedef struct {\r
- UINT32 Reserved;\r
-} ENTRY_EVT_LOG_STOPPED;\r
-\r
-typedef struct {\r
- UINT32 VmcallApiNumber;\r
-} ENTRY_EVT_LOG_INVALID_PARAM;\r
-\r
-typedef struct {\r
- STM_RSC Resource;\r
-} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION;\r
-\r
-typedef struct {\r
- STM_RSC Resource;\r
-} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC;\r
-\r
-typedef struct {\r
- STM_RSC Resource;\r
-} ENTRY_EVT_MLE_RSC_PROT_GRANTED;\r
-\r
-typedef struct {\r
- STM_RSC Resource;\r
-} ENTRY_EVT_MLE_RSC_PROT_DENIED;\r
-\r
-typedef struct {\r
- STM_RSC Resource;\r
-} ENTRY_EVT_MLE_RSC_UNPROT;\r
-\r
-typedef struct {\r
- STM_RSC Resource;\r
-} ENTRY_EVT_MLE_RSC_UNPROT_ERROR;\r
-\r
-typedef struct {\r
- UINT64 VmcsPhysPointer;\r
- UINT8 ExpectedDomainType;\r
- UINT8 DegradedDomainType;\r
-} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED;\r
-\r
-typedef union {\r
- ENTRY_EVT_LOG_STARTED Started;\r
- ENTRY_EVT_LOG_STOPPED Stopped;\r
- ENTRY_EVT_LOG_INVALID_PARAM InvalidParam;\r
- ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException;\r
- ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc;\r
- ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted;\r
- ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied;\r
- ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot;\r
- ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError;\r
- ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded;\r
-} LOG_ENTRY_DATA;\r
-\r
-typedef struct {\r
- LOG_ENTRY_HEADER Hdr;\r
- LOG_ENTRY_DATA Data;\r
-} STM_LOG_ENTRY;\r
-\r
-/**\r
- Maximum STM Log Entry Size\r
-**/\r
-#define STM_LOG_ENTRY_SIZE 256\r
-\r
-\r
-/**\r
- STM Protection Exception Stack Frame Structures\r
-**/\r
-\r
-typedef struct {\r
- UINT32 Rdi;\r
- UINT32 Rsi;\r
- UINT32 Rbp;\r
- UINT32 Rdx;\r
- UINT32 Rcx;\r
- UINT32 Rbx;\r
- UINT32 Rax;\r
- UINT32 Cr3;\r
- UINT32 Cr2;\r
- UINT32 Cr0;\r
- UINT32 VmcsExitInstructionInfo;\r
- UINT32 VmcsExitInstructionLength;\r
- UINT64 VmcsExitQualification;\r
- ///\r
- /// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value\r
- ///\r
- UINT32 ErrorCode;\r
- UINT32 Rip;\r
- UINT32 Cs;\r
- UINT32 Rflags;\r
- UINT32 Rsp;\r
- UINT32 Ss;\r
-} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32;\r
-\r
-typedef struct {\r
- UINT64 R15;\r
- UINT64 R14;\r
- UINT64 R13;\r
- UINT64 R12;\r
- UINT64 R11;\r
- UINT64 R10;\r
- UINT64 R9;\r
- UINT64 R8;\r
- UINT64 Rdi;\r
- UINT64 Rsi;\r
- UINT64 Rbp;\r
- UINT64 Rdx;\r
- UINT64 Rcx;\r
- UINT64 Rbx;\r
- UINT64 Rax;\r
- UINT64 Cr8;\r
- UINT64 Cr3;\r
- UINT64 Cr2;\r
- UINT64 Cr0;\r
- UINT64 VmcsExitInstructionInfo;\r
- UINT64 VmcsExitInstructionLength;\r
- UINT64 VmcsExitQualification;\r
- ///\r
- /// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value\r
- ///\r
- UINT64 ErrorCode;\r
- UINT64 Rip;\r
- UINT64 Cs;\r
- UINT64 Rflags;\r
- UINT64 Rsp;\r
- UINT64 Ss;\r
-} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64;\r
-\r
-typedef union {\r
- STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame;\r
- STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame;\r
-} STM_PROTECTION_EXCEPTION_STACK_FRAME;\r
-\r
-/**\r
- Enum values for the ErrorCode field in\r
- #STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 and\r
- #STM_PROTECTION_EXCEPTION_STACK_FRAME_X64\r
-**/\r
-typedef enum {\r
- TxtSmmPageViolation = 1,\r
- TxtSmmMsrViolation,\r
- TxtSmmRegisterViolation,\r
- TxtSmmIoViolation,\r
- TxtSmmPciViolation\r
-} TXT_SMM_PROTECTION_EXCEPTION_TYPE;\r
-\r
-/**\r
- TXT Pocessor SMM Descriptor (PSD) structures\r
-**/\r
-\r
-typedef struct {\r
- UINT64 SpeRip;\r
- UINT64 SpeRsp;\r
- UINT16 SpeSs;\r
- UINT16 PageViolationException:1;\r
- UINT16 MsrViolationException:1;\r
- UINT16 RegisterViolationException:1;\r
- UINT16 IoViolationException:1;\r
- UINT16 PciViolationException:1;\r
- UINT16 Reserved1:11;\r
- UINT32 Reserved2;\r
-} STM_PROTECTION_EXCEPTION_HANDLER;\r
-\r
-typedef struct {\r
- UINT8 ExecutionDisableOutsideSmrr:1;\r
- UINT8 Intel64Mode:1;\r
- UINT8 Cr4Pae : 1;\r
- UINT8 Cr4Pse : 1;\r
- UINT8 Reserved1 : 4;\r
-} STM_SMM_ENTRY_STATE;\r
-\r
-typedef struct {\r
- UINT8 SmramToVmcsRestoreRequired : 1; ///> BIOS restore hint\r
- UINT8 ReinitializeVmcsRequired : 1; ///> BIOS request\r
- UINT8 Reserved2 : 6;\r
-} STM_SMM_RESUME_STATE;\r
-\r
-typedef struct {\r
- UINT8 DomainType : 4; ///> STM input to BIOS on each SMI\r
- UINT8 XStatePolicy : 2; ///> STM input to BIOS on each SMI\r
- UINT8 EptEnabled : 1;\r
- UINT8 Reserved3 : 1;\r
-} STM_SMM_STATE;\r
-\r
-#define TXT_SMM_PSD_OFFSET 0xfb00\r
-#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE SIGNATURE_64('T', 'X', 'T', 'P', 'S', 'S', 'I', 'G')\r
-#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1\r
-#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0\r
-\r
-typedef struct {\r
- UINT64 Signature;\r
- UINT16 Size;\r
- UINT8 SmmDescriptorVerMajor;\r
- UINT8 SmmDescriptorVerMinor;\r
- UINT32 LocalApicId;\r
- STM_SMM_ENTRY_STATE SmmEntryState;\r
- STM_SMM_RESUME_STATE SmmResumeState;\r
- STM_SMM_STATE StmSmmState;\r
- UINT8 Reserved4;\r
- UINT16 SmmCs;\r
- UINT16 SmmDs;\r
- UINT16 SmmSs;\r
- UINT16 SmmOtherSegment;\r
- UINT16 SmmTr;\r
- UINT16 Reserved5;\r
- UINT64 SmmCr3;\r
- UINT64 SmmStmSetupRip;\r
- UINT64 SmmStmTeardownRip;\r
- UINT64 SmmSmiHandlerRip;\r
- UINT64 SmmSmiHandlerRsp;\r
- UINT64 SmmGdtPtr;\r
- UINT32 SmmGdtSize;\r
- UINT32 RequiredStmSmmRevId;\r
- STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler;\r
- UINT64 Reserved6;\r
- UINT64 BiosHwResourceRequirementsPtr;\r
- // extend area\r
- UINT64 AcpiRsdp;\r
- UINT8 PhysicalAddressBits;\r
-} TXT_PROCESSOR_SMM_DESCRIPTOR;\r
-\r
-#pragma pack ()\r
+#include <Register/Intel/StmApi.h>\r
\r
#endif\r
+++ /dev/null
-/** @file\r
- STM Resource Descriptor\r
-\r
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- SMI Transfer Monitor (STM) User Guide Revision 1.00\r
-\r
-**/\r
-\r
-#ifndef _STM_RESOURCE_DESCRIPTOR_H_\r
-#define _STM_RESOURCE_DESCRIPTOR_H_\r
-\r
-#pragma pack (1)\r
-\r
-/**\r
- STM Resource Descriptor Header\r
-**/\r
-typedef struct {\r
- UINT32 RscType;\r
- UINT16 Length;\r
- UINT16 ReturnStatus:1;\r
- UINT16 Reserved:14;\r
- UINT16 IgnoreResource:1;\r
-} STM_RSC_DESC_HEADER;\r
-\r
-/**\r
- Define values for the RscType field of #STM_RSC_DESC_HEADER\r
- @{\r
-**/\r
-#define END_OF_RESOURCES 0\r
-#define MEM_RANGE 1\r
-#define IO_RANGE 2\r
-#define MMIO_RANGE 3\r
-#define MACHINE_SPECIFIC_REG 4\r
-#define PCI_CFG_RANGE 5\r
-#define TRAPPED_IO_RANGE 6\r
-#define ALL_RESOURCES 7\r
-#define REGISTER_VIOLATION 8\r
-#define MAX_DESC_TYPE 8\r
-/// @}\r
-\r
-/**\r
- STM Resource End Descriptor\r
-**/\r
-typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT64 ResourceListContinuation;\r
-} STM_RSC_END;\r
-\r
-/**\r
- STM Resource Memory Descriptor\r
-**/\r
-typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT64 Base;\r
- UINT64 Length;\r
- UINT32 RWXAttributes:3;\r
- UINT32 Reserved:29;\r
- UINT32 Reserved_2;\r
-} STM_RSC_MEM_DESC;\r
-\r
-/**\r
- Define values for the RWXAttributes field of #STM_RSC_MEM_DESC\r
- @{\r
-**/\r
-#define STM_RSC_MEM_R 0x1\r
-#define STM_RSC_MEM_W 0x2\r
-#define STM_RSC_MEM_X 0x4\r
-/// @}\r
-\r
-/**\r
- STM Resource I/O Descriptor\r
-**/\r
-typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT16 Base;\r
- UINT16 Length;\r
- UINT32 Reserved;\r
-} STM_RSC_IO_DESC;\r
-\r
-/**\r
- STM Resource MMIO Descriptor\r
-**/\r
-typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT64 Base;\r
- UINT64 Length;\r
- UINT32 RWXAttributes:3;\r
- UINT32 Reserved:29;\r
- UINT32 Reserved_2;\r
-} STM_RSC_MMIO_DESC;\r
-\r
-/**\r
- Define values for the RWXAttributes field of #STM_RSC_MMIO_DESC\r
- @{\r
-**/\r
-#define STM_RSC_MMIO_R 0x1\r
-#define STM_RSC_MMIO_W 0x2\r
-#define STM_RSC_MMIO_X 0x4\r
-/// @}\r
-\r
-/**\r
- STM Resource MSR Descriptor\r
-**/\r
-typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT32 MsrIndex;\r
- UINT32 KernelModeProcessing:1;\r
- UINT32 Reserved:31;\r
- UINT64 ReadMask;\r
- UINT64 WriteMask;\r
-} STM_RSC_MSR_DESC;\r
-\r
-/**\r
- STM PCI Device Path node used for the PciDevicePath field of\r
- #STM_RSC_PCI_CFG_DESC\r
-**/\r
-typedef struct {\r
- ///\r
- /// Must be 1, indicating Hardware Device Path\r
- ///\r
- UINT8 Type;\r
- ///\r
- /// Must be 1, indicating PCI\r
- ///\r
- UINT8 Subtype;\r
- ///\r
- /// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6\r
- ///\r
- UINT16 Length;\r
- UINT8 PciFunction;\r
- UINT8 PciDevice;\r
-} STM_PCI_DEVICE_PATH_NODE;\r
-\r
-/**\r
- STM Resource PCI Configuration Descriptor\r
-**/\r
-typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT16 RWAttributes:2;\r
- UINT16 Reserved:14;\r
- UINT16 Base;\r
- UINT16 Length;\r
- UINT8 OriginatingBusNumber;\r
- UINT8 LastNodeIndex;\r
- STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];\r
-//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];\r
-} STM_RSC_PCI_CFG_DESC;\r
-\r
-/**\r
- Define values for the RWAttributes field of #STM_RSC_PCI_CFG_DESC\r
- @{\r
-**/\r
-#define STM_RSC_PCI_CFG_R 0x1\r
-#define STM_RSC_PCI_CFG_W 0x2\r
-/// @}\r
-\r
-/**\r
- STM Resource Trapped I/O Descriptor\r
-**/\r
-typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT16 Base;\r
- UINT16 Length;\r
- UINT16 In:1;\r
- UINT16 Out:1;\r
- UINT16 Api:1;\r
- UINT16 Reserved1:13;\r
- UINT16 Reserved2;\r
-} STM_RSC_TRAPPED_IO_DESC;\r
-\r
-/**\r
- STM Resource All Descriptor\r
-**/\r
-typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
-} STM_RSC_ALL_RESOURCES_DESC;\r
-\r
-/**\r
- STM Register Volation Descriptor\r
-**/\r
-typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT32 RegisterType;\r
- UINT32 Reserved;\r
- UINT64 ReadMask;\r
- UINT64 WriteMask;\r
-} STM_REGISTER_VIOLATION_DESC;\r
-\r
-/**\r
- Enum values for the RWAttributes field of #STM_REGISTER_VIOLATION_DESC\r
-**/\r
-typedef enum {\r
- StmRegisterCr0,\r
- StmRegisterCr2,\r
- StmRegisterCr3,\r
- StmRegisterCr4,\r
- StmRegisterCr8,\r
- StmRegisterMax,\r
-} STM_REGISTER_VIOLATION_TYPE;\r
-\r
-/**\r
- Union of all STM resource types\r
-**/\r
-typedef union {\r
- STM_RSC_DESC_HEADER Header;\r
- STM_RSC_END End;\r
- STM_RSC_MEM_DESC Mem;\r
- STM_RSC_IO_DESC Io;\r
- STM_RSC_MMIO_DESC Mmio;\r
- STM_RSC_MSR_DESC Msr;\r
- STM_RSC_PCI_CFG_DESC PciCfg;\r
- STM_RSC_TRAPPED_IO_DESC TrappedIo;\r
- STM_RSC_ALL_RESOURCES_DESC All;\r
- STM_REGISTER_VIOLATION_DESC RegisterViolation;\r
-} STM_RSC;\r
-\r
-#pragma pack ()\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- STM Status Codes\r
-\r
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
- @par Specification Reference:\r
- SMI Transfer Monitor (STM) User Guide Revision 1.00\r
-\r
-**/\r
-\r
-#ifndef _STM_STATUS_CODE_H_\r
-#define _STM_STATUS_CODE_H_\r
-\r
-/**\r
- STM Status Codes\r
-**/\r
-typedef UINT32 STM_STATUS;\r
-\r
-/**\r
- Success code have BIT31 clear.\r
- All error codes have BIT31 set.\r
- STM errors have BIT16 set.\r
- SMM errors have BIT17 set\r
- Errors that apply to both STM and SMM have bits BIT15, BT16, and BIT17 set.\r
- STM TXT.ERRORCODE codes have BIT30 set.\r
- @{\r
-**/\r
-#define STM_SUCCESS 0x00000000\r
-#define SMM_SUCCESS 0x00000000\r
-#define ERROR_STM_SECURITY_VIOLATION (BIT31 | BIT16 | 0x0001)\r
-#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED (BIT31 | BIT16 | 0x0002)\r
-#define ERROR_STM_PAGE_NOT_FOUND (BIT31 | BIT16 | 0x0003)\r
-#define ERROR_STM_BAD_CR3 (BIT31 | BIT16 | 0x0004)\r
-#define ERROR_STM_PHYSICAL_OVER_4G (BIT31 | BIT16 | 0x0005)\r
-#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL (BIT31 | BIT16 | 0x0006)\r
-#define ERROR_STM_UNPROTECTABLE_RESOURCE (BIT31 | BIT16 | 0x0007)\r
-#define ERROR_STM_ALREADY_STARTED (BIT31 | BIT16 | 0x0008)\r
-#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED (BIT31 | BIT16 | 0x0009)\r
-#define ERROR_STM_STOPPED (BIT31 | BIT16 | 0x000A)\r
-#define ERROR_STM_BUFFER_TOO_SMALL (BIT31 | BIT16 | 0x000B)\r
-#define ERROR_STM_INVALID_VMCS_DATABASE (BIT31 | BIT16 | 0x000C)\r
-#define ERROR_STM_MALFORMED_RESOURCE_LIST (BIT31 | BIT16 | 0x000D)\r
-#define ERROR_STM_INVALID_PAGECOUNT (BIT31 | BIT16 | 0x000E)\r
-#define ERROR_STM_LOG_ALLOCATED (BIT31 | BIT16 | 0x000F)\r
-#define ERROR_STM_LOG_NOT_ALLOCATED (BIT31 | BIT16 | 0x0010)\r
-#define ERROR_STM_LOG_NOT_STOPPED (BIT31 | BIT16 | 0x0011)\r
-#define ERROR_STM_LOG_NOT_STARTED (BIT31 | BIT16 | 0x0012)\r
-#define ERROR_STM_RESERVED_BIT_SET (BIT31 | BIT16 | 0x0013)\r
-#define ERROR_STM_NO_EVENTS_ENABLED (BIT31 | BIT16 | 0x0014)\r
-#define ERROR_STM_OUT_OF_RESOURCES (BIT31 | BIT16 | 0x0015)\r
-#define ERROR_STM_FUNCTION_NOT_SUPPORTED (BIT31 | BIT16 | 0x0016)\r
-#define ERROR_STM_UNPROTECTABLE (BIT31 | BIT16 | 0x0017)\r
-#define ERROR_STM_UNSUPPORTED_MSR_BIT (BIT31 | BIT16 | 0x0018)\r
-#define ERROR_STM_UNSPECIFIED (BIT31 | BIT16 | 0xFFFF)\r
-#define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)\r
-#define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)\r
-#define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)\r
-#define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)\r
-#define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)\r
-#define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)\r
-#define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)\r
-#define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)\r
-#define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)\r
-#define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)\r
-#define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)\r
-#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)\r
-#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)\r
-#define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)\r
-/// @}\r
-\r
-#endif\r
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