UefiCpuPkg/CpuCacheInfoLib: Collect cache associative type

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3265

Support collecting cache associative type in CpuCacheInfoLib.
This prevents the user from using additional code to obtain the
same information.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>

diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
index a7f29b1887750e91140267eb636cc4a8a934121e..a66152bce009e4ecc45b5f2cf222166494ef4830 100644 (file)
--- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
+++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
@@ -1,7 +1,7 @@
 /** @file\r
   Header file for CPU Cache info Library.\r
 \r
-  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -33,7 +33,18 @@ typedef struct {
   // Ways of associativity.\r
   // Value = CPUID.04h:EBX[31:22]\r
   //\r
-  UINT16        CacheWays;\r
+  UINT16        CacheWays : 10;\r
+  //\r
+  // Fully associative cache.\r
+  // Value = CPUID.04h:EAX[09]\r
+  //\r
+  UINT16        FullyAssociativeCache : 1;\r
+  //\r
+  // Direct mapped cache.\r
+  // Value = CPUID.04h:EDX[02]\r
+  //\r
+  UINT16        DirectMappedCache : 1;\r
+  UINT16        Reserved : 4;\r
   //\r
   // Size of single cache that this package's this type of logical processor corresponds to.\r
   // Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) *\r

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
index d46fb04258513960891d4ce2103386bb2afc58ef..126ee0da86fc60f05b1566700b11339a25a7fad3 100644 (file)
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
@@ -1,7 +1,7 @@
 /** @file\r
   Provides cache info for each package, core type, cache level and cache type.\r
 \r
-  Copyright (c) 2020 Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -23,18 +23,18 @@ CpuCacheInfoPrintCpuCacheInfoTable (
 {\r
   UINTN                     Index;\r
 \r
-  DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------------------------------+\n"));\r
-  DEBUG ((DEBUG_INFO, "| Index | Packge  CoreType  CacheLevel  CacheType  CacheWays  CacheSizeinKB  CacheCount |\n"));\r
-  DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------------------------------+\n"));\r
+  DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));\r
+  DEBUG ((DEBUG_INFO, "| Index | Packge  CoreType  CacheLevel  CacheType  CacheWays (FA|DM) CacheSizeinKB  CacheCount |\n"));\r
+  DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));\r
 \r
   for (Index = 0; Index < CpuCacheInfoCount; Index++) {\r
-    DEBUG ((DEBUG_INFO, "| %4x  | %4x       %2x        %2x          %2x       %4x      %8x         %4x     |\n", Index,\r
-        CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel,\r
-        CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].CacheSizeinKB,\r
-        CpuCacheInfo[Index].CacheCount));\r
+    DEBUG ((DEBUG_INFO, "| %4x  | %4x       %2x        %2x          %2x       %4x     ( %x| %x) %8x         %4x     |\n",\r
+        Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel,\r
+        CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].FullyAssociativeCache,\r
+        CpuCacheInfo[Index].DirectMappedCache, CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount));\r
   }\r
 \r
-  DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------------------------------+\n"));\r
+  DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));\r
 }\r
 \r
 /**\r
@@ -160,6 +160,7 @@ CpuCacheInfoCollectCoreAndCacheData (
   CPUID_CACHE_PARAMS_EAX    CacheParamEax;\r
   CPUID_CACHE_PARAMS_EBX    CacheParamEbx;\r
   UINT32                    CacheParamEcx;\r
+  CPUID_CACHE_PARAMS_EDX    CacheParamEdx;\r
   CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX   NativeModelIdAndCoreTypeEax;\r
   COLLECT_CPUID_CACHE_DATA_CONTEXT  *Context;\r
   CPUID_CACHE_DATA          *CacheData;\r
@@ -185,17 +186,19 @@ CpuCacheInfoCollectCoreAndCacheData (
   CacheParamLeafIndex = 0;\r
 \r
   while (CacheParamLeafIndex < MAX_NUM_OF_CACHE_PARAMS_LEAF) {\r
-    AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex, &CacheParamEax.Uint32, &CacheParamEbx.Uint32, &CacheParamEcx, NULL);\r
+    AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex, &CacheParamEax.Uint32, &CacheParamEbx.Uint32, &CacheParamEcx, &CacheParamEdx.Uint32);\r
 \r
     if (CacheParamEax.Bits.CacheType == 0) {\r
       break;\r
     }\r
 \r
-    CacheData[CacheParamLeafIndex].CacheLevel     = (UINT8)CacheParamEax.Bits.CacheLevel;\r
-    CacheData[CacheParamLeafIndex].CacheType      = (UINT8)CacheParamEax.Bits.CacheType;\r
-    CacheData[CacheParamLeafIndex].CacheWays      = (UINT16)CacheParamEbx.Bits.Ways;\r
-    CacheData[CacheParamLeafIndex].CacheShareBits = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;\r
-    CacheData[CacheParamLeafIndex].CacheSizeinKB  = (CacheParamEbx.Bits.Ways + 1) *\r
+    CacheData[CacheParamLeafIndex].CacheLevel            = (UINT8)CacheParamEax.Bits.CacheLevel;\r
+    CacheData[CacheParamLeafIndex].CacheType             = (UINT8)CacheParamEax.Bits.CacheType;\r
+    CacheData[CacheParamLeafIndex].CacheWays             = (UINT16)CacheParamEbx.Bits.Ways;\r
+    CacheData[CacheParamLeafIndex].FullyAssociativeCache = (UINT8)CacheParamEax.Bits.FullyAssociativeCache;\r
+    CacheData[CacheParamLeafIndex].DirectMappedCache     = (UINT8)CacheParamEdx.Bits.ComplexCacheIndexing;\r
+    CacheData[CacheParamLeafIndex].CacheShareBits        = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;\r
+    CacheData[CacheParamLeafIndex].CacheSizeinKB         = (CacheParamEbx.Bits.Ways + 1) *\r
         (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB;\r
 \r
     CacheParamLeafIndex++;\r
@@ -305,13 +308,15 @@ CpuCacheInfoCollectCpuCacheInfoData (
     if (CacheInfoIndex == LocalCacheInfoCount) {\r
       ASSERT (LocalCacheInfoCount < MaxCacheInfoCount);\r
 \r
-      LocalCacheInfo[LocalCacheInfoCount].Package       = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package;\r
-      LocalCacheInfo[LocalCacheInfoCount].CoreType      = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType;\r
-      LocalCacheInfo[LocalCacheInfoCount].CacheLevel    = CacheData[Index].CacheLevel;\r
-      LocalCacheInfo[LocalCacheInfoCount].CacheType     = CacheData[Index].CacheType;\r
-      LocalCacheInfo[LocalCacheInfoCount].CacheWays     = CacheData[Index].CacheWays;\r
-      LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB = CacheData[Index].CacheSizeinKB;\r
-      LocalCacheInfo[LocalCacheInfoCount].CacheCount    = 1;\r
+      LocalCacheInfo[LocalCacheInfoCount].Package               = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package;\r
+      LocalCacheInfo[LocalCacheInfoCount].CoreType              = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType;\r
+      LocalCacheInfo[LocalCacheInfoCount].CacheLevel            = CacheData[Index].CacheLevel;\r
+      LocalCacheInfo[LocalCacheInfoCount].CacheType             = CacheData[Index].CacheType;\r
+      LocalCacheInfo[LocalCacheInfoCount].CacheWays             = CacheData[Index].CacheWays;\r
+      LocalCacheInfo[LocalCacheInfoCount].FullyAssociativeCache = CacheData[Index].FullyAssociativeCache;\r
+      LocalCacheInfo[LocalCacheInfoCount].DirectMappedCache     = CacheData[Index].DirectMappedCache;\r
+      LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB         = CacheData[Index].CacheSizeinKB;\r
+      LocalCacheInfo[LocalCacheInfoCount].CacheCount            = 1;\r
 \r
       LocalCacheInfoCount++;\r
     }\r

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
index de56db9c0cbed792765e2bf52933825bcb5425e1..b6e6ae5bc50a2ae1399b3edbd499001c0fc188e8 100644 (file)
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
@@ -1,7 +1,7 @@
 /** @file\r
   Internal header file for CPU Cache info Library.\r
 \r
-  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -52,7 +52,18 @@ typedef struct {
   // Ways of associativity.\r
   // Value = CPUID.04h:EBX[31:22]\r
   //\r
-  UINT16                    CacheWays;\r
+  UINT16                    CacheWays : 10;\r
+  //\r
+  // Fully associative cache.\r
+  // Value = CPUID.04h:EAX[09]\r
+  //\r
+  UINT16                    FullyAssociativeCache : 1;\r
+  //\r
+  // Direct mapped cache.\r
+  // Value = CPUID.04h:EDX[02]\r
+  //\r
+  UINT16                    DirectMappedCache : 1;\r
+  UINT16                    Reserved : 4;\r
   //\r
   // Cache share bits.\r
   // Value = CPUID.04h:EAX[25:14]\r