Device Tree PCI interrupt flags use the convention described at
linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
The 3rd cell is the flags, encoded as follows:
bits[3:0] trigger type and level flags.
1 = low-to-high edge triggered
2 = high-to-low edge triggered (invalid for SPIs)
4 = active high level-sensitive
8 = active low level-sensitive (invalid for SPIs).
Fix the incorrect code.
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
if ((Index > 0) &&\r
(IrqMapInfo->IntcInterrupt.Interrupt >= 32) &&\r
(IrqMapInfo->IntcInterrupt.Interrupt < 1020) &&\r
- ((IrqMapInfo->IntcInterrupt.Flags & 0x3) != BIT0))\r
+ ((IrqMapInfo->IntcInterrupt.Flags & 0xB) != 0))\r
{\r
Status = EFI_INVALID_PARAMETER;\r
ASSERT_EFI_ERROR (Status);\r
#define SPI_OFFSET (32U)\r
#define DT_PPI_IRQ (1U)\r
#define DT_SPI_IRQ (0U)\r
-#define DT_IRQ_IS_EDGE_TRIGGERED(x) ((((x) & (BIT0 | BIT2)) != 0))\r
+#define DT_IRQ_IS_EDGE_TRIGGERED(x) ((((x) & (BIT0 | BIT1)) != 0))\r
#define DT_IRQ_IS_ACTIVE_LOW(x) ((((x) & (BIT1 | BIT3)) != 0))\r
#define IRQ_TYPE_OFFSET (0U)\r
#define IRQ_NUMBER_OFFSET (1U)\r