projects / mirror_qemu.git / search
| 2020-07-02 | Alistair Francis | hw/riscv: Allow 64 bit access to SiFive CLINT Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...39b444d3a46fe894a7804c.1593547870.git.alistair.francis@wdc.com> |
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| 2020-07-02 | Jessica Clarke | riscv: plic: Add a couple of mising sifive_plic_update... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-07-02 | Jessica Clarke | riscv: plic: Honour source priorities Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_u: Add a dummy DDR memory controller... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_u: Sort the SoC memmap table entries Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_u: Support different boot source per... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive: Change SiFive E/U CPU reset vector... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | target/riscv: Rename IBEX CPU init routine Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_u: Add a new property msel for MSEL... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_u: Rename serial property get/set... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_u: Add reset functionality Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_gpio: Do not blindly trigger output... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_u: Hook a GPIO controller Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_gpio: Add a new 'ngpio' property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_gpio: Clean up the codes Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_u: Generate device tree node for OTP Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_u: Simplify the GEM IRQ connect code... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: opentitan: Remove the riscv_ prefix of the... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | hw/riscv: sifive_e: Remove the riscv_ prefix of the... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | target/riscv: Use a smaller guess size for no-MMU PMP Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | riscv/opentitan: Connect the UART device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | riscv/opentitan: Connect the PLIC device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | hw/intc: Initial commit of lowRISC Ibex PLIC Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | hw/char: Initial commit of Ibex UART Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | riscv/opentitan: Fix the ROM size Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | target/riscv: Implement checks for hfence Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | target/riscv: Move the hfence instructions to the rvh... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | target/riscv: Report errors validating 2nd-stage PTEs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | target/riscv: Set access as data_load when validating... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | riscv: Keep the CPU init routine names consistent Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | riscv: Generalize CPU init routine for the imacu CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | riscv: Generalize CPU init routine for the gcsu CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Bin Meng | riscv: Generalize CPU init routine for the base CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Alistair Francis | sifive_e: Support the revB machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-19 | Ian Jiang | riscv: Add helper to make NaN-boxing for FP register Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | riscv: Initial commit of OpenTitan machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | target/riscv: Add the lowRISC Ibex CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | target/riscv: Don't set PMP feature in the cpu init Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | target/riscv: Disable the MMU correctly Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | target/riscv: Don't overwrite the reset vector Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | riscv/boot: Add a missing header include Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | riscv: sifive_e: Manually define the machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | docs: deprecated: Update the -bios documentation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | target/riscv: Drop support for ISA spec version 1.09.1 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | target/riscv: Remove the deprecated CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Alistair Francis | hw/riscv: spike: Remove deprecated ISA specific machines Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Bin Meng | hw/riscv: virt: Remove the riscv_ prefix of the machine... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Bin Meng | hw/riscv: sifive_u: Remove the riscv_ prefix of the... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Bin Meng | riscv: Change the default behavior if no -bios option... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-06-03 | Bin Meng | riscv: Suppress the error report for QEMU testing with... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-05-27 | Philippe Mathieu... | hw/registerfields: Prefix local variables with underscore... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-05-05 | Joaquin de Andres | hw/core/register: Add register_init_block8 helper. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Anup Patel | hw/riscv/spike: Allow more than one CPUs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Anup Patel | hw/riscv/spike: Allow loading firmware separately using... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Anup Patel | hw/riscv: Add optional symbol callback ptr to riscv_load_fir... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Bin Meng | roms: opensbi: Upgrade from v0.6 to v0.7 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | LIU Zhiwei | linux-user/riscv: fix up struct target_ucontext definition Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Corey Wharton | target/riscv: Add a sifive-e34 cpu type Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Corey Wharton | riscv: sifive_e: Support changing CPU type Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Bin Meng | hw/riscv: Generate correct "mmu-type" for 32-bit machines Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Anup Patel | riscv: Fix Stage2 SV32 page table walk Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Alistair Francis | riscv: AND stage-1 and stage-2 protection flags Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...c464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com ...c464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com> |
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| 2020-04-29 | Alistair Francis | riscv: Don't use stage-2 PTE lookup protection flags Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...b527fd1011197cd28299aa.1585262586.git.alistair.francis@wdc.com ...b527fd1011197cd28299aa.1585262586.git.alistair.francis@wdc.com> |
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| 2020-04-29 | Bin Meng | riscv/sifive_u: Add a serial property to the sifive_u... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Alistair Francis | riscv/sifive_u: Add a serial property to the sifive_u SoC Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-04-29 | Alistair Francis | riscv/sifive_u: Fix up file ordering Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-03-20 | Leonardo Bras | device_tree: Add info message when dumping dtb to file Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-04-09 | Markus Armbruster | device_tree: Fix integer overflowing in load_device_tree() Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-03-27 | Alistair Francis | MAINTAINERS: Update the device tree maintainers Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-09-05 | Igor Mammedov | riscv: remove define cpu_init() Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-09-05 | Alistair Francis | hw/riscv/spike: Set the soc device tree node as a simple-bus Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-09-05 | Alistair Francis | hw/riscv/virtio: Set the soc device tree node as a... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-09-05 | Emilio G. Cota | target/riscv: call gen_goto_tb on DISAS_TOO_MANY Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-09-05 | Emilio G. Cota | target/riscv: optimize indirect branches Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-09-05 | Emilio G. Cota | target/riscv: optimize cross-page direct jumps in softmmu Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-09-04 | Michael Clark | RISC-V: Simplify riscv_cpu_local_irqs_pending Cc: Alistair Francis <Alistair.Francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-09-04 | Michael Clark | RISC-V: Use atomic_cmpxchg to update PLIC bitmaps Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-09-04 | Michael Clark | RISC-V: Improve page table walker spec compliance Cc: Alistair Francis <Alistair.Francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-09-04 | Michael Clark | RISC-V: Update address bits to support sv39 and sv48 Cc: Alistair Francis <Alistair.Francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-19 | Alistair Francis | spike: Fix crash when introspecting the device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-19 | Alistair Francis | riscv_hart: Fix crash when introspecting the device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-19 | Alistair Francis | virt: Fix crash when introspecting the device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-19 | Alistair Francis | sifive_u: Fix crash when introspecting the device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-19 | Alistair Francis | sifive_e: Fix crash when introspecting the device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-05 | Alistair Francis | hw/riscv/sifive_u: Connect the Cadence GEM Ethernet... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-05 | Alistair Francis | hw/riscv/sifive_u: Move the uart device tree node under... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-05 | Alistair Francis | hw/riscv/sifive_u: Set the interrupt controller number... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-05 | Alistair Francis | hw/riscv/sifive_u: Set the soc device tree node as... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-05 | Alistair Francis | hw/riscv/sifive_plic: Use gpios instead of irqs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-05 | Alistair Francis | hw/riscv/sifive_e: Create a SiFive E SoC object Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-07-05 | Alistair Francis | hw/riscv/sifive_u: Create a SiFive U SoC object Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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