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| 2018-10-30 | Palmer Dabbelt | Add Alistair as a RISC-V Maintainer Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-30 | Dayeol Lee | target/riscv/pmp.c: pmpcfg_csr_read returns bogus value... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Don't add NULL bootargs to device-tree Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Add missing free for plic_hart_config Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Update CSR and interrupt definitions Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Move non-ops from op_helper to cpu_helper Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Allow setting and clearing multiple irqs Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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