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update sources to v12.1.1
[ceph.git] / ceph / src / isa-l / igzip / igzip_multibinary.asm
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1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2; Copyright(c) 2011-2016 Intel Corporation All rights reserved.
3;
4; Redistribution and use in source and binary forms, with or without
5; modification, are permitted provided that the following conditions
6; are met:
7; * Redistributions of source code must retain the above copyright
8; notice, this list of conditions and the following disclaimer.
9; * Redistributions in binary form must reproduce the above copyright
10; notice, this list of conditions and the following disclaimer in
11; the documentation and/or other materials provided with the
12; distribution.
13; * Neither the name of Intel Corporation nor the names of its
14; contributors may be used to endorse or promote products derived
15; from this software without specific prior written permission.
16;
17; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
29
30default rel
31[bits 64]
32
33%ifidn __OUTPUT_FORMAT__, elf64
34%define WRT_OPT wrt ..plt
35%else
36%define WRT_OPT
37%endif
38
39%include "reg_sizes.asm"
40
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41extern isal_deflate_body_base
42extern isal_deflate_body_01
224ce89b 43extern isal_deflate_body_02
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44extern isal_deflate_body_04
45extern isal_deflate_finish_base
46extern isal_deflate_finish_01
47
7c673cae 48
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49extern isal_deflate_icf_body_base
50extern isal_deflate_icf_body_01
51extern isal_deflate_icf_body_02
52extern isal_deflate_icf_body_04
53extern isal_deflate_icf_finish_base
54extern isal_deflate_icf_finish_01
7c673cae 55
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56extern isal_update_histogram_base
57extern isal_update_histogram_01
58extern isal_update_histogram_04
7c673cae 59
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60extern encode_deflate_icf_base
61extern encode_deflate_icf_04
7c673cae 62
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63extern crc32_gzip_base
64extern crc32_gzip_01
7c673cae 65
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66section .text
67
68%include "multibinary.asm"
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69
70mbin_interface isal_deflate_body
224ce89b 71mbin_dispatch_init5 isal_deflate_body, isal_deflate_body_base, isal_deflate_body_01, isal_deflate_body_02, isal_deflate_body_04
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72mbin_interface isal_deflate_finish
73mbin_dispatch_init5 isal_deflate_finish, isal_deflate_finish_base, isal_deflate_finish_01, isal_deflate_finish_01, isal_deflate_finish_01
74
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75mbin_interface isal_deflate_icf_body
76mbin_dispatch_init5 isal_deflate_icf_body, isal_deflate_icf_body_base, isal_deflate_icf_body_01, isal_deflate_icf_body_02, isal_deflate_icf_body_04
77mbin_interface isal_deflate_icf_finish
78mbin_dispatch_init5 isal_deflate_icf_finish, isal_deflate_icf_finish_base, isal_deflate_icf_finish_01, isal_deflate_icf_finish_01, isal_deflate_icf_finish_01
79
80mbin_interface isal_update_histogram
81mbin_dispatch_init5 isal_update_histogram, isal_update_histogram_base, isal_update_histogram_01, isal_update_histogram_01, isal_update_histogram_04
82
83mbin_interface encode_deflate_icf
84mbin_dispatch_init5 encode_deflate_icf, encode_deflate_icf_base, encode_deflate_icf_base, encode_deflate_icf_base, encode_deflate_icf_04
85
86mbin_interface crc32_gzip
87mbin_dispatch_init5 crc32_gzip, crc32_gzip_base, crc32_gzip_base, crc32_gzip_01, crc32_gzip_01