[ceph.git] / ceph / src / isa-l / raid / raid_multibinary.asm

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  Copyright(c) 2011-2015 Intel Corporation All rights reserved.
;
;  Redistribution and use in source and binary forms, with or without
;  modification, are permitted provided that the following conditions
;  are met:
;    * Redistributions of source code must retain the above copyright
;      notice, this list of conditions and the following disclaimer.
;    * Redistributions in binary form must reproduce the above copyright
;      notice, this list of conditions and the following disclaimer in
;      the documentation and/or other materials provided with the
;      distribution.
;    * Neither the name of Intel Corporation nor the names of its
;      contributors may be used to endorse or promote products derived
;      from this software without specific prior written permission.
;
;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

%ifidn __OUTPUT_FORMAT__, elf64
%define WRT_OPT         wrt ..plt
%else
%define WRT_OPT
%endif

%include "reg_sizes.asm"
%include "multibinary.asm"

default rel
[bits 64]

extern pq_gen_base
extern pq_gen_sse
extern pq_gen_avx
extern pq_gen_avx2

extern xor_gen_base
extern xor_gen_sse
extern xor_gen_avx

extern pq_check_base
extern pq_check_sse

extern xor_check_base
extern xor_check_sse

%ifdef HAVE_AS_KNOWS_AVX512
 extern xor_gen_avx512
 extern pq_gen_avx512
%endif

mbin_interface xor_gen
mbin_interface pq_gen

%ifdef HAVE_AS_KNOWS_AVX512
 mbin_dispatch_init6 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx, xor_gen_avx512
 mbin_dispatch_init6 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2, pq_gen_avx512
%else
 mbin_dispatch_init5 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx
 mbin_dispatch_init5 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2
%endif

section .data

xor_check_dispatched:
	dq      xor_check_mbinit
pq_check_dispatched:
	dq      pq_check_mbinit

section .text

;;;;
; pq_check multibinary function
;;;;
global pq_check:function
pq_check_mbinit:
	call	pq_check_dispatch_init
pq_check:
	jmp     qword [pq_check_dispatched]

pq_check_dispatch_init:
	push    rax
	push    rbx
	push    rcx
	push    rdx
	push    rsi
	lea     rsi, [pq_check_base WRT_OPT] ; Default

	mov     eax, 1
	cpuid
	test    ecx, FLAG_CPUID1_ECX_SSE4_1
	lea     rbx, [pq_check_sse WRT_OPT]
	cmovne	rsi, rbx

	mov     [pq_check_dispatched], rsi
	pop     rsi
	pop     rdx
	pop     rcx
	pop     rbx
	pop     rax
	ret


;;;;
; xor_check multibinary function
;;;;
global xor_check:function
xor_check_mbinit:
	call    xor_check_dispatch_init
xor_check:
	jmp     qword [xor_check_dispatched]

xor_check_dispatch_init:
	push    rax
	push    rbx
	push    rcx
	push    rdx
	push    rsi
	lea     rsi, [xor_check_base WRT_OPT] ; Default

	mov     eax, 1
	cpuid
	test    ecx, FLAG_CPUID1_ECX_SSE4_1
	lea     rbx, [xor_check_sse WRT_OPT]
	cmovne  rsi, rbx

	mov     [xor_check_dispatched], rsi
	pop     rsi
	pop     rdx
	pop     rcx
	pop     rbx
	pop     rax
	ret

;;;       func          	core, ver, snum
slversion xor_gen,		00,   03,  0126
slversion xor_check,		00,   03,  0127
slversion pq_gen,		00,   03,  0128
slversion pq_check,		00,   03,  0129
Commit	Line	Data
7c673cae FG	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	2	; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
	3	;
	4	; Redistribution and use in source and binary forms, with or without
	5	; modification, are permitted provided that the following conditions
	6	; are met:
	7	; * Redistributions of source code must retain the above copyright
	8	; notice, this list of conditions and the following disclaimer.
	9	; * Redistributions in binary form must reproduce the above copyright
	10	; notice, this list of conditions and the following disclaimer in
	11	; the documentation and/or other materials provided with the
	12	; distribution.
	13	; * Neither the name of Intel Corporation nor the names of its
	14	; contributors may be used to endorse or promote products derived
	15	; from this software without specific prior written permission.
	16	;
	17	; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	18	; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	19	; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	20	; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	21	; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	22	; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	23	; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	24	; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	25	; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	26	; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	27	; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	28	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	29
	30	%ifidn __OUTPUT_FORMAT__, elf64
	31	%define WRT_OPT wrt ..plt
	32	%else
	33	%define WRT_OPT
	34	%endif
	35
	36	%include "reg_sizes.asm"
	37	%include "multibinary.asm"
	38
	39	default rel
	40	[bits 64]
	41
	42	extern pq_gen_base
	43	extern pq_gen_sse
	44	extern pq_gen_avx
	45	extern pq_gen_avx2
	46
	47	extern xor_gen_base
	48	extern xor_gen_sse
	49	extern xor_gen_avx
	50
	51	extern pq_check_base
	52	extern pq_check_sse
	53
	54	extern xor_check_base
	55	extern xor_check_sse
	56
224ce89b WB	57	%ifdef HAVE_AS_KNOWS_AVX512
	58	extern xor_gen_avx512
	59	extern pq_gen_avx512
	60	%endif
	61
7c673cae FG	62	mbin_interface xor_gen
	63	mbin_interface pq_gen
	64
224ce89b WB	65	%ifdef HAVE_AS_KNOWS_AVX512
	66	mbin_dispatch_init6 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx, xor_gen_avx512
	67	mbin_dispatch_init6 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2, pq_gen_avx512
	68	%else
	69	mbin_dispatch_init5 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx
	70	mbin_dispatch_init5 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2
	71	%endif
7c673cae FG	72
	73	section .data
	74
	75	xor_check_dispatched:
	76	dq xor_check_mbinit
	77	pq_check_dispatched:
	78	dq pq_check_mbinit
	79
	80	section .text
	81
	82	;;;;
	83	; pq_check multibinary function
	84	;;;;
	85	global pq_check:function
	86	pq_check_mbinit:
	87	call pq_check_dispatch_init
	88	pq_check:
	89	jmp qword [pq_check_dispatched]
	90
	91	pq_check_dispatch_init:
	92	push rax
	93	push rbx
	94	push rcx
	95	push rdx
	96	push rsi
	97	lea rsi, [pq_check_base WRT_OPT] ; Default
	98
	99	mov eax, 1
	100	cpuid
	101	test ecx, FLAG_CPUID1_ECX_SSE4_1
	102	lea rbx, [pq_check_sse WRT_OPT]
	103	cmovne rsi, rbx
	104
	105	mov [pq_check_dispatched], rsi
	106	pop rsi
	107	pop rdx
	108	pop rcx
	109	pop rbx
	110	pop rax
	111	ret
	112
	113
	114	;;;;
	115	; xor_check multibinary function
	116	;;;;
	117	global xor_check:function
	118	xor_check_mbinit:
	119	call xor_check_dispatch_init
	120	xor_check:
	121	jmp qword [xor_check_dispatched]
	122
	123	xor_check_dispatch_init:
	124	push rax
	125	push rbx
	126	push rcx
	127	push rdx
	128	push rsi
	129	lea rsi, [xor_check_base WRT_OPT] ; Default
	130
	131	mov eax, 1
	132	cpuid
	133	test ecx, FLAG_CPUID1_ECX_SSE4_1
	134	lea rbx, [xor_check_sse WRT_OPT]
	135	cmovne rsi, rbx
136
137	mov [xor_check_dispatched], rsi
138	pop rsi
139	pop rdx
140	pop rcx
141	pop rbx
142	pop rax
143	ret
144
145	;;; func core, ver, snum
146	slversion xor_gen, 00, 03, 0126
147	slversion xor_check, 00, 03, 0127
148	slversion pq_gen, 00, 03, 0128
149	slversion pq_check, 00, 03, 0129