[ceph.git] / ceph / src / spdk / dpdk / drivers / raw / ifpga / base / opae_ifpga_hw_api.h

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2010-2018 Intel Corporation
 */

#ifndef _OPAE_IFPGA_HW_API_H_
#define _OPAE_IFPGA_HW_API_H_

#include "opae_hw_api.h"

/**
 * struct feature_prop - data structure for feature property
 * @feature_id: id of this feature.
 * @prop_id: id of this property under this feature.
 * @data: property value to set/get.
 */
struct feature_prop {
	u64 feature_id;
	u64 prop_id;
	u64 data;
};

#define IFPGA_FIU_ID_FME	0x0
#define IFPGA_FIU_ID_PORT	0x1

#define IFPGA_FME_FEATURE_ID_HEADER		0x0
#define IFPGA_FME_FEATURE_ID_THERMAL_MGMT	0x1
#define IFPGA_FME_FEATURE_ID_POWER_MGMT		0x2
#define IFPGA_FME_FEATURE_ID_GLOBAL_IPERF	0x3
#define IFPGA_FME_FEATURE_ID_GLOBAL_ERR		0x4
#define IFPGA_FME_FEATURE_ID_PR_MGMT		0x5
#define IFPGA_FME_FEATURE_ID_HSSI		0x6
#define IFPGA_FME_FEATURE_ID_GLOBAL_DPERF	0x7

#define IFPGA_PORT_FEATURE_ID_HEADER		0x0
#define IFPGA_PORT_FEATURE_ID_AFU		0xff
#define IFPGA_PORT_FEATURE_ID_ERROR		0x10
#define IFPGA_PORT_FEATURE_ID_UMSG		0x11
#define IFPGA_PORT_FEATURE_ID_UINT		0x12
#define IFPGA_PORT_FEATURE_ID_STP		0x13

/*
 * PROP format (TOP + SUB + ID)
 *
 * (~0x0) means this field is unused.
 */
#define PROP_TOP	GENMASK(31, 24)
#define PROP_TOP_UNUSED	0xff
#define PROP_SUB	GENMASK(23, 16)
#define PROP_SUB_UNUSED	0xff
#define PROP_ID		GENMASK(15, 0)

#define PROP(_top, _sub, _id) \
	(SET_FIELD(PROP_TOP, _top) | SET_FIELD(PROP_SUB, _sub) |\
	 SET_FIELD(PROP_ID, _id))

/* FME head feature's properties*/
#define FME_HDR_PROP_REVISION		0x1	/* RDONLY */
#define FME_HDR_PROP_PORTS_NUM		0x2	/* RDONLY */
#define FME_HDR_PROP_CACHE_SIZE		0x3	/* RDONLY */
#define FME_HDR_PROP_VERSION			0x4	/* RDONLY */
#define FME_HDR_PROP_SOCKET_ID		0x5	/* RDONLY */
#define FME_HDR_PROP_BITSTREAM_ID		0x6	/* RDONLY */
#define FME_HDR_PROP_BITSTREAM_METADATA	0x7	/* RDONLY */

/* FME error reporting feature's properties */
/* FME error reporting properties format */
#define ERR_PROP(_top, _id)		PROP(_top, 0xff, _id)
#define ERR_PROP_TOP_UNUSED		PROP_TOP_UNUSED
#define ERR_PROP_TOP_FME_ERR		0x1
#define ERR_PROP_ROOT(_id)		ERR_PROP(0xff, _id)
#define ERR_PROP_FME_ERR(_id)		ERR_PROP(ERR_PROP_TOP_FME_ERR, _id)

#define FME_ERR_PROP_ERRORS		ERR_PROP_FME_ERR(0x1)
#define FME_ERR_PROP_FIRST_ERROR	ERR_PROP_FME_ERR(0x2)
#define FME_ERR_PROP_NEXT_ERROR		ERR_PROP_FME_ERR(0x3)
#define FME_ERR_PROP_CLEAR		ERR_PROP_FME_ERR(0x4)	/* WO */
#define FME_ERR_PROP_SEU_EMR_LOW        ERR_PROP_FME_ERR(0x5)
#define FME_ERR_PROP_SEU_EMR_HIGH       ERR_PROP_FME_ERR(0x6)
#define FME_ERR_PROP_REVISION		ERR_PROP_ROOT(0x5)
#define FME_ERR_PROP_PCIE0_ERRORS	ERR_PROP_ROOT(0x6)	/* RW */
#define FME_ERR_PROP_PCIE1_ERRORS	ERR_PROP_ROOT(0x7)	/* RW */
#define FME_ERR_PROP_NONFATAL_ERRORS	ERR_PROP_ROOT(0x8)
#define FME_ERR_PROP_CATFATAL_ERRORS	ERR_PROP_ROOT(0x9)
#define FME_ERR_PROP_INJECT_ERRORS	ERR_PROP_ROOT(0xa)	/* RW */

/* FME thermal feature's properties */
#define FME_THERMAL_PROP_THRESHOLD1		0x1	/* RW */
#define FME_THERMAL_PROP_THRESHOLD2		0x2	/* RW */
#define FME_THERMAL_PROP_THRESHOLD_TRIP		0x3	/* RDONLY */
#define FME_THERMAL_PROP_THRESHOLD1_REACHED	0x4	/* RDONLY */
#define FME_THERMAL_PROP_THRESHOLD2_REACHED	0x5	/* RDONLY */
#define FME_THERMAL_PROP_THRESHOLD1_POLICY	0x6	/* RW */
#define FME_THERMAL_PROP_TEMPERATURE		0x7	/* RDONLY */
#define FME_THERMAL_PROP_REVISION		0x8	/* RDONLY */

/* FME power feature's properties */
#define FME_PWR_PROP_CONSUMED			0x1	/* RDONLY */
#define FME_PWR_PROP_THRESHOLD1			0x2	/* RW */
#define FME_PWR_PROP_THRESHOLD2			0x3	/* RW */
#define FME_PWR_PROP_THRESHOLD1_STATUS		0x4	/* RDONLY */
#define FME_PWR_PROP_THRESHOLD2_STATUS		0x5	/* RDONLY */
#define FME_PWR_PROP_RTL			0x6	/* RDONLY */
#define FME_PWR_PROP_XEON_LIMIT			0x7	/* RDONLY */
#define FME_PWR_PROP_FPGA_LIMIT			0x8	/* RDONLY */
#define FME_PWR_PROP_REVISION			0x9	/* RDONLY */

/* FME iperf/dperf PROP format */
#define PERF_PROP_TOP_CACHE			0x1
#define PERF_PROP_TOP_VTD			0x2
#define PERF_PROP_TOP_FAB			0x3
#define PERF_PROP_TOP_UNUSED			PROP_TOP_UNUSED
#define PERF_PROP_SUB_UNUSED			PROP_SUB_UNUSED

#define PERF_PROP_ROOT(_id)		PROP(0xff, 0xff, _id)
#define PERF_PROP_CACHE(_id)		PROP(PERF_PROP_TOP_CACHE, 0xff, _id)
#define PERF_PROP_VTD(_sub, _id)	PROP(PERF_PROP_TOP_VTD, _sub, _id)
#define PERF_PROP_VTD_ROOT(_id)		PROP(PERF_PROP_TOP_VTD, 0xff, _id)
#define PERF_PROP_FAB(_sub, _id)	PROP(PERF_PROP_TOP_FAB, _sub, _id)
#define PERF_PROP_FAB_ROOT(_id)		PROP(PERF_PROP_TOP_FAB, 0xff, _id)

/* FME iperf feature's properties */
#define FME_IPERF_PROP_CLOCK			PERF_PROP_ROOT(0x1)
#define FME_IPERF_PROP_REVISION			PERF_PROP_ROOT(0x2)

/* iperf CACHE properties */
#define FME_IPERF_PROP_CACHE_FREEZE		PERF_PROP_CACHE(0x1) /* RW */
#define FME_IPERF_PROP_CACHE_READ_HIT		PERF_PROP_CACHE(0x2)
#define FME_IPERF_PROP_CACHE_READ_MISS		PERF_PROP_CACHE(0x3)
#define FME_IPERF_PROP_CACHE_WRITE_HIT		PERF_PROP_CACHE(0x4)
#define FME_IPERF_PROP_CACHE_WRITE_MISS		PERF_PROP_CACHE(0x5)
#define FME_IPERF_PROP_CACHE_HOLD_REQUEST	PERF_PROP_CACHE(0x6)
#define FME_IPERF_PROP_CACHE_TX_REQ_STALL	PERF_PROP_CACHE(0x7)
#define FME_IPERF_PROP_CACHE_RX_REQ_STALL	PERF_PROP_CACHE(0x8)
#define FME_IPERF_PROP_CACHE_RX_EVICTION	PERF_PROP_CACHE(0x9)
#define FME_IPERF_PROP_CACHE_DATA_WRITE_PORT_CONTENTION	PERF_PROP_CACHE(0xa)
#define FME_IPERF_PROP_CACHE_TAG_WRITE_PORT_CONTENTION	PERF_PROP_CACHE(0xb)
/* iperf VTD properties */
#define FME_IPERF_PROP_VTD_FREEZE		PERF_PROP_VTD_ROOT(0x1) /* RW */
#define FME_IPERF_PROP_VTD_SIP_IOTLB_4K_HIT	PERF_PROP_VTD_ROOT(0x2)
#define FME_IPERF_PROP_VTD_SIP_IOTLB_2M_HIT	PERF_PROP_VTD_ROOT(0x3)
#define FME_IPERF_PROP_VTD_SIP_IOTLB_1G_HIT	PERF_PROP_VTD_ROOT(0x4)
#define FME_IPERF_PROP_VTD_SIP_SLPWC_L3_HIT	PERF_PROP_VTD_ROOT(0x5)
#define FME_IPERF_PROP_VTD_SIP_SLPWC_L4_HIT	PERF_PROP_VTD_ROOT(0x6)
#define FME_IPERF_PROP_VTD_SIP_RCC_HIT		PERF_PROP_VTD_ROOT(0x7)
#define FME_IPERF_PROP_VTD_SIP_IOTLB_4K_MISS	PERF_PROP_VTD_ROOT(0x8)
#define FME_IPERF_PROP_VTD_SIP_IOTLB_2M_MISS	PERF_PROP_VTD_ROOT(0x9)
#define FME_IPERF_PROP_VTD_SIP_IOTLB_1G_MISS	PERF_PROP_VTD_ROOT(0xa)
#define FME_IPERF_PROP_VTD_SIP_SLPWC_L3_MISS	PERF_PROP_VTD_ROOT(0xb)
#define FME_IPERF_PROP_VTD_SIP_SLPWC_L4_MISS	PERF_PROP_VTD_ROOT(0xc)
#define FME_IPERF_PROP_VTD_SIP_RCC_MISS		PERF_PROP_VTD_ROOT(0xd)
#define FME_IPERF_PROP_VTD_PORT_READ_TRANSACTION(n)	PERF_PROP_VTD(n, 0xe)
#define FME_IPERF_PROP_VTD_PORT_WRITE_TRANSACTION(n)	PERF_PROP_VTD(n, 0xf)
#define FME_IPERF_PROP_VTD_PORT_DEVTLB_READ_HIT(n)	PERF_PROP_VTD(n, 0x10)
#define FME_IPERF_PROP_VTD_PORT_DEVTLB_WRITE_HIT(n)	PERF_PROP_VTD(n, 0x11)
#define FME_IPERF_PROP_VTD_PORT_DEVTLB_4K_FILL(n)	PERF_PROP_VTD(n, 0x12)
#define FME_IPERF_PROP_VTD_PORT_DEVTLB_2M_FILL(n)	PERF_PROP_VTD(n, 0x13)
#define FME_IPERF_PROP_VTD_PORT_DEVTLB_1G_FILL(n)	PERF_PROP_VTD(n, 0x14)
/* iperf FAB properties */
#define FME_IPERF_PROP_FAB_FREEZE		PERF_PROP_FAB_ROOT(0x1) /* RW */
#define FME_IPERF_PROP_FAB_PCIE0_READ		PERF_PROP_FAB_ROOT(0x2)
#define FME_IPERF_PROP_FAB_PORT_PCIE0_READ(n)	PERF_PROP_FAB(n, 0x2)
#define FME_IPERF_PROP_FAB_PCIE0_WRITE		PERF_PROP_FAB_ROOT(0x3)
#define FME_IPERF_PROP_FAB_PORT_PCIE0_WRITE(n)	PERF_PROP_FAB(n, 0x3)
#define FME_IPERF_PROP_FAB_PCIE1_READ		PERF_PROP_FAB_ROOT(0x4)
#define FME_IPERF_PROP_FAB_PORT_PCIE1_READ(n)	PERF_PROP_FAB(n, 0x4)
#define FME_IPERF_PROP_FAB_PCIE1_WRITE		PERF_PROP_FAB_ROOT(0x5)
#define FME_IPERF_PROP_FAB_PORT_PCIE1_WRITE(n)	PERF_PROP_FAB(n, 0x5)
#define FME_IPERF_PROP_FAB_UPI_READ		PERF_PROP_FAB_ROOT(0x6)
#define FME_IPERF_PROP_FAB_PORT_UPI_READ(n)	PERF_PROP_FAB(n, 0x6)
#define FME_IPERF_PROP_FAB_UPI_WRITE		PERF_PROP_FAB_ROOT(0x7)
#define FME_IPERF_PROP_FAB_PORT_UPI_WRITE(n)	PERF_PROP_FAB(n, 0x7)
#define FME_IPERF_PROP_FAB_MMIO_READ		PERF_PROP_FAB_ROOT(0x8)
#define FME_IPERF_PROP_FAB_PORT_MMIO_READ(n)	PERF_PROP_FAB(n, 0x8)
#define FME_IPERF_PROP_FAB_MMIO_WRITE		PERF_PROP_FAB_ROOT(0x9)
#define FME_IPERF_PROP_FAB_PORT_MMIO_WRITE(n)	PERF_PROP_FAB(n, 0x9)
#define FME_IPERF_PROP_FAB_ENABLE		PERF_PROP_FAB_ROOT(0xa) /* RW */
#define FME_IPERF_PROP_FAB_PORT_ENABLE(n)	PERF_PROP_FAB(n, 0xa)   /* RW */

/* FME dperf properties */
#define FME_DPERF_PROP_CLOCK			PERF_PROP_ROOT(0x1)
#define FME_DPERF_PROP_REVISION			PERF_PROP_ROOT(0x2)

/* dperf FAB properties */
#define FME_DPERF_PROP_FAB_FREEZE		PERF_PROP_FAB_ROOT(0x1) /* RW */
#define FME_DPERF_PROP_FAB_PCIE0_READ		PERF_PROP_FAB_ROOT(0x2)
#define FME_DPERF_PROP_FAB_PORT_PCIE0_READ(n)	PERF_PROP_FAB(n, 0x2)
#define FME_DPERF_PROP_FAB_PCIE0_WRITE		PERF_PROP_FAB_ROOT(0x3)
#define FME_DPERF_PROP_FAB_PORT_PCIE0_WRITE(n)	PERF_PROP_FAB(n, 0x3)
#define FME_DPERF_PROP_FAB_MMIO_READ		PERF_PROP_FAB_ROOT(0x4)
#define FME_DPERF_PROP_FAB_PORT_MMIO_READ(n)	PERF_PROP_FAB(n, 0x4)
#define FME_DPERF_PROP_FAB_MMIO_WRITE		PERF_PROP_FAB_ROOT(0x5)
#define FME_DPERF_PROP_FAB_PORT_MMIO_WRITE(n)	PERF_PROP_FAB(n, 0x5)
#define FME_DPERF_PROP_FAB_ENABLE		PERF_PROP_FAB_ROOT(0x6) /* RW */
#define FME_DPERF_PROP_FAB_PORT_ENABLE(n)	PERF_PROP_FAB(n, 0x6)   /* RW */

/*PORT hdr feature's properties*/
#define PORT_HDR_PROP_REVISION			0x1	/* RDONLY */
#define PORT_HDR_PROP_PORTIDX			0x2	/* RDONLY */
#define PORT_HDR_PROP_LATENCY_TOLERANCE		0x3	/* RDONLY */
#define PORT_HDR_PROP_AP1_EVENT			0x4	/* RW */
#define PORT_HDR_PROP_AP2_EVENT			0x5	/* RW */
#define PORT_HDR_PROP_POWER_STATE		0x6	/* RDONLY */
#define PORT_HDR_PROP_USERCLK_FREQCMD		0x7	/* RW */
#define PORT_HDR_PROP_USERCLK_FREQCNTRCMD	0x8	/* RW */
#define PORT_HDR_PROP_USERCLK_FREQSTS		0x9	/* RDONLY */
#define PORT_HDR_PROP_USERCLK_CNTRSTS		0xa	/* RDONLY */

/*PORT error feature's properties*/
#define PORT_ERR_PROP_REVISION			0x1	/* RDONLY */
#define PORT_ERR_PROP_ERRORS			0x2	/* RDONLY */
#define PORT_ERR_PROP_FIRST_ERROR		0x3	/* RDONLY */
#define PORT_ERR_PROP_FIRST_MALFORMED_REQ_LSB	0x4	/* RDONLY */
#define PORT_ERR_PROP_FIRST_MALFORMED_REQ_MSB	0x5	/* RDONLY */
#define PORT_ERR_PROP_CLEAR			0x6	/* WRONLY */

int opae_manager_ifpga_get_prop(struct opae_manager *mgr,
				struct feature_prop *prop);
int opae_manager_ifpga_set_prop(struct opae_manager *mgr,
				struct feature_prop *prop);
int opae_bridge_ifpga_get_prop(struct opae_bridge *br,
			       struct feature_prop *prop);
int opae_bridge_ifpga_set_prop(struct opae_bridge *br,
			       struct feature_prop *prop);

/*
 * Retrieve information about the fpga fme.
 * Driver fills the info in provided struct fpga_fme_info.
 */
struct fpga_fme_info {
	u32 capability;		/* The capability of FME device */
#define FPGA_FME_CAP_ERR_IRQ	(1 << 0) /* Support fme error interrupt */
};

int opae_manager_ifpga_get_info(struct opae_manager *mgr,
				struct fpga_fme_info *fme_info);

/* Set eventfd information for ifpga FME error interrupt */
struct fpga_fme_err_irq_set {
	s32 evtfd;		/* Eventfd handler */
};

int opae_manager_ifpga_set_err_irq(struct opae_manager *mgr,
				   struct fpga_fme_err_irq_set *err_irq_set);

/*
 * Retrieve information about the fpga port.
 * Driver fills the info in provided struct fpga_port_info.
 */
struct fpga_port_info {
	u32 capability;	/* The capability of port device */
#define FPGA_PORT_CAP_ERR_IRQ	(1 << 0) /* Support port error interrupt */
#define FPGA_PORT_CAP_UAFU_IRQ	(1 << 1) /* Support uafu error interrupt */
	u32 num_umsgs;	/* The number of allocated umsgs */
	u32 num_uafu_irqs;	/* The number of uafu interrupts */
};

int opae_bridge_ifpga_get_info(struct opae_bridge *br,
			       struct fpga_port_info *port_info);
/*
 * Retrieve region information about the fpga port.
 * Driver needs to fill the index of struct fpga_port_region_info.
 */
struct fpga_port_region_info {
	u32 index;
#define PORT_REGION_INDEX_STP	(1 << 1)	/* Signal Tap Region */
	u64 size;	/* Region Size */
	u8 *addr;	/* Base address of the region */
};

int opae_bridge_ifpga_get_region_info(struct opae_bridge *br,
				      struct fpga_port_region_info *info);

/* Set eventfd information for ifpga port error interrupt */
struct fpga_port_err_irq_set {
	s32 evtfd;		/* Eventfd handler */
};

int opae_bridge_ifpga_set_err_irq(struct opae_bridge *br,
				  struct fpga_port_err_irq_set *err_irq_set);

#endif /* _OPAE_IFPGA_HW_API_H_ */
Commit	Line	Data
11fdf7f2 TL	1	/* SPDX-License-Identifier: BSD-3-Clause
	2	* Copyright(c) 2010-2018 Intel Corporation
	3	*/
	4
	5	#ifndef _OPAE_IFPGA_HW_API_H_
	6	#define _OPAE_IFPGA_HW_API_H_
	7
	8	#include "opae_hw_api.h"
	9
	10	/**
	11	* struct feature_prop - data structure for feature property
	12	* @feature_id: id of this feature.
	13	* @prop_id: id of this property under this feature.
	14	* @data: property value to set/get.
	15	*/
	16	struct feature_prop {
	17	u64 feature_id;
	18	u64 prop_id;
	19	u64 data;
	20	};
	21
	22	#define IFPGA_FIU_ID_FME 0x0
	23	#define IFPGA_FIU_ID_PORT 0x1
	24
	25	#define IFPGA_FME_FEATURE_ID_HEADER 0x0
	26	#define IFPGA_FME_FEATURE_ID_THERMAL_MGMT 0x1
	27	#define IFPGA_FME_FEATURE_ID_POWER_MGMT 0x2
	28	#define IFPGA_FME_FEATURE_ID_GLOBAL_IPERF 0x3
	29	#define IFPGA_FME_FEATURE_ID_GLOBAL_ERR 0x4
	30	#define IFPGA_FME_FEATURE_ID_PR_MGMT 0x5
	31	#define IFPGA_FME_FEATURE_ID_HSSI 0x6
	32	#define IFPGA_FME_FEATURE_ID_GLOBAL_DPERF 0x7
	33
	34	#define IFPGA_PORT_FEATURE_ID_HEADER 0x0
	35	#define IFPGA_PORT_FEATURE_ID_AFU 0xff
	36	#define IFPGA_PORT_FEATURE_ID_ERROR 0x10
	37	#define IFPGA_PORT_FEATURE_ID_UMSG 0x11
	38	#define IFPGA_PORT_FEATURE_ID_UINT 0x12
	39	#define IFPGA_PORT_FEATURE_ID_STP 0x13
	40
	41	/*
	42	* PROP format (TOP + SUB + ID)
	43	*
	44	* (~0x0) means this field is unused.
	45	*/
	46	#define PROP_TOP GENMASK(31, 24)
	47	#define PROP_TOP_UNUSED 0xff
	48	#define PROP_SUB GENMASK(23, 16)
	49	#define PROP_SUB_UNUSED 0xff
	50	#define PROP_ID GENMASK(15, 0)
	51
	52	#define PROP(_top, _sub, _id) \
	53	(SET_FIELD(PROP_TOP, _top) \| SET_FIELD(PROP_SUB, _sub) \|\
	54	SET_FIELD(PROP_ID, _id))
	55
	56	/* FME head feature's properties*/
	57	#define FME_HDR_PROP_REVISION 0x1 /* RDONLY */
	58	#define FME_HDR_PROP_PORTS_NUM 0x2 /* RDONLY */
	59	#define FME_HDR_PROP_CACHE_SIZE 0x3 /* RDONLY */
	60	#define FME_HDR_PROP_VERSION 0x4 /* RDONLY */
	61	#define FME_HDR_PROP_SOCKET_ID 0x5 /* RDONLY */
	62	#define FME_HDR_PROP_BITSTREAM_ID 0x6 /* RDONLY */
	63	#define FME_HDR_PROP_BITSTREAM_METADATA 0x7 /* RDONLY */
	64
65	/* FME error reporting feature's properties */
66	/* FME error reporting properties format */
67	#define ERR_PROP(_top, _id) PROP(_top, 0xff, _id)
68	#define ERR_PROP_TOP_UNUSED PROP_TOP_UNUSED
69	#define ERR_PROP_TOP_FME_ERR 0x1
70	#define ERR_PROP_ROOT(_id) ERR_PROP(0xff, _id)
71	#define ERR_PROP_FME_ERR(_id) ERR_PROP(ERR_PROP_TOP_FME_ERR, _id)
72
73	#define FME_ERR_PROP_ERRORS ERR_PROP_FME_ERR(0x1)
74	#define FME_ERR_PROP_FIRST_ERROR ERR_PROP_FME_ERR(0x2)
75	#define FME_ERR_PROP_NEXT_ERROR ERR_PROP_FME_ERR(0x3)
76	#define FME_ERR_PROP_CLEAR ERR_PROP_FME_ERR(0x4) /* WO */
f67539c2 TL	77	#define FME_ERR_PROP_SEU_EMR_LOW ERR_PROP_FME_ERR(0x5)
f67539c2 TL	78	#define FME_ERR_PROP_SEU_EMR_HIGH ERR_PROP_FME_ERR(0x6)
11fdf7f2 TL	79	#define FME_ERR_PROP_REVISION ERR_PROP_ROOT(0x5)
	80	#define FME_ERR_PROP_PCIE0_ERRORS ERR_PROP_ROOT(0x6) /* RW */
	81	#define FME_ERR_PROP_PCIE1_ERRORS ERR_PROP_ROOT(0x7) /* RW */
	82	#define FME_ERR_PROP_NONFATAL_ERRORS ERR_PROP_ROOT(0x8)
	83	#define FME_ERR_PROP_CATFATAL_ERRORS ERR_PROP_ROOT(0x9)
	84	#define FME_ERR_PROP_INJECT_ERRORS ERR_PROP_ROOT(0xa) /* RW */
	85
	86	/* FME thermal feature's properties */
	87	#define FME_THERMAL_PROP_THRESHOLD1 0x1 /* RW */
	88	#define FME_THERMAL_PROP_THRESHOLD2 0x2 /* RW */
	89	#define FME_THERMAL_PROP_THRESHOLD_TRIP 0x3 /* RDONLY */
	90	#define FME_THERMAL_PROP_THRESHOLD1_REACHED 0x4 /* RDONLY */
	91	#define FME_THERMAL_PROP_THRESHOLD2_REACHED 0x5 /* RDONLY */
	92	#define FME_THERMAL_PROP_THRESHOLD1_POLICY 0x6 /* RW */
	93	#define FME_THERMAL_PROP_TEMPERATURE 0x7 /* RDONLY */
	94	#define FME_THERMAL_PROP_REVISION 0x8 /* RDONLY */
	95
	96	/* FME power feature's properties */
	97	#define FME_PWR_PROP_CONSUMED 0x1 /* RDONLY */
	98	#define FME_PWR_PROP_THRESHOLD1 0x2 /* RW */
	99	#define FME_PWR_PROP_THRESHOLD2 0x3 /* RW */
	100	#define FME_PWR_PROP_THRESHOLD1_STATUS 0x4 /* RDONLY */
	101	#define FME_PWR_PROP_THRESHOLD2_STATUS 0x5 /* RDONLY */
	102	#define FME_PWR_PROP_RTL 0x6 /* RDONLY */
	103	#define FME_PWR_PROP_XEON_LIMIT 0x7 /* RDONLY */
	104	#define FME_PWR_PROP_FPGA_LIMIT 0x8 /* RDONLY */
	105	#define FME_PWR_PROP_REVISION 0x9 /* RDONLY */
	106
	107	/* FME iperf/dperf PROP format */
	108	#define PERF_PROP_TOP_CACHE 0x1
	109	#define PERF_PROP_TOP_VTD 0x2
	110	#define PERF_PROP_TOP_FAB 0x3
	111	#define PERF_PROP_TOP_UNUSED PROP_TOP_UNUSED
	112	#define PERF_PROP_SUB_UNUSED PROP_SUB_UNUSED
	113
	114	#define PERF_PROP_ROOT(_id) PROP(0xff, 0xff, _id)
	115	#define PERF_PROP_CACHE(_id) PROP(PERF_PROP_TOP_CACHE, 0xff, _id)
	116	#define PERF_PROP_VTD(_sub, _id) PROP(PERF_PROP_TOP_VTD, _sub, _id)
	117	#define PERF_PROP_VTD_ROOT(_id) PROP(PERF_PROP_TOP_VTD, 0xff, _id)
	118	#define PERF_PROP_FAB(_sub, _id) PROP(PERF_PROP_TOP_FAB, _sub, _id)
	119	#define PERF_PROP_FAB_ROOT(_id) PROP(PERF_PROP_TOP_FAB, 0xff, _id)
	120
	121	/* FME iperf feature's properties */
	122	#define FME_IPERF_PROP_CLOCK PERF_PROP_ROOT(0x1)
	123	#define FME_IPERF_PROP_REVISION PERF_PROP_ROOT(0x2)
	124
	125	/* iperf CACHE properties */
	126	#define FME_IPERF_PROP_CACHE_FREEZE PERF_PROP_CACHE(0x1) /* RW */
	127	#define FME_IPERF_PROP_CACHE_READ_HIT PERF_PROP_CACHE(0x2)
	128	#define FME_IPERF_PROP_CACHE_READ_MISS PERF_PROP_CACHE(0x3)
	129	#define FME_IPERF_PROP_CACHE_WRITE_HIT PERF_PROP_CACHE(0x4)
	130	#define FME_IPERF_PROP_CACHE_WRITE_MISS PERF_PROP_CACHE(0x5)
	131	#define FME_IPERF_PROP_CACHE_HOLD_REQUEST PERF_PROP_CACHE(0x6)
	132	#define FME_IPERF_PROP_CACHE_TX_REQ_STALL PERF_PROP_CACHE(0x7)
	133	#define FME_IPERF_PROP_CACHE_RX_REQ_STALL PERF_PROP_CACHE(0x8)
	134	#define FME_IPERF_PROP_CACHE_RX_EVICTION PERF_PROP_CACHE(0x9)
	135	#define FME_IPERF_PROP_CACHE_DATA_WRITE_PORT_CONTENTION PERF_PROP_CACHE(0xa)
	136	#define FME_IPERF_PROP_CACHE_TAG_WRITE_PORT_CONTENTION PERF_PROP_CACHE(0xb)
	137	/* iperf VTD properties */
	138	#define FME_IPERF_PROP_VTD_FREEZE PERF_PROP_VTD_ROOT(0x1) /* RW */
	139	#define FME_IPERF_PROP_VTD_SIP_IOTLB_4K_HIT PERF_PROP_VTD_ROOT(0x2)
	140	#define FME_IPERF_PROP_VTD_SIP_IOTLB_2M_HIT PERF_PROP_VTD_ROOT(0x3)
	141	#define FME_IPERF_PROP_VTD_SIP_IOTLB_1G_HIT PERF_PROP_VTD_ROOT(0x4)
	142	#define FME_IPERF_PROP_VTD_SIP_SLPWC_L3_HIT PERF_PROP_VTD_ROOT(0x5)
143	#define FME_IPERF_PROP_VTD_SIP_SLPWC_L4_HIT PERF_PROP_VTD_ROOT(0x6)
144	#define FME_IPERF_PROP_VTD_SIP_RCC_HIT PERF_PROP_VTD_ROOT(0x7)
145	#define FME_IPERF_PROP_VTD_SIP_IOTLB_4K_MISS PERF_PROP_VTD_ROOT(0x8)
146	#define FME_IPERF_PROP_VTD_SIP_IOTLB_2M_MISS PERF_PROP_VTD_ROOT(0x9)
147	#define FME_IPERF_PROP_VTD_SIP_IOTLB_1G_MISS PERF_PROP_VTD_ROOT(0xa)
148	#define FME_IPERF_PROP_VTD_SIP_SLPWC_L3_MISS PERF_PROP_VTD_ROOT(0xb)
149	#define FME_IPERF_PROP_VTD_SIP_SLPWC_L4_MISS PERF_PROP_VTD_ROOT(0xc)
150	#define FME_IPERF_PROP_VTD_SIP_RCC_MISS PERF_PROP_VTD_ROOT(0xd)
151	#define FME_IPERF_PROP_VTD_PORT_READ_TRANSACTION(n) PERF_PROP_VTD(n, 0xe)
152	#define FME_IPERF_PROP_VTD_PORT_WRITE_TRANSACTION(n) PERF_PROP_VTD(n, 0xf)
153	#define FME_IPERF_PROP_VTD_PORT_DEVTLB_READ_HIT(n) PERF_PROP_VTD(n, 0x10)
154	#define FME_IPERF_PROP_VTD_PORT_DEVTLB_WRITE_HIT(n) PERF_PROP_VTD(n, 0x11)
155	#define FME_IPERF_PROP_VTD_PORT_DEVTLB_4K_FILL(n) PERF_PROP_VTD(n, 0x12)
156	#define FME_IPERF_PROP_VTD_PORT_DEVTLB_2M_FILL(n) PERF_PROP_VTD(n, 0x13)
157	#define FME_IPERF_PROP_VTD_PORT_DEVTLB_1G_FILL(n) PERF_PROP_VTD(n, 0x14)
158	/* iperf FAB properties */
159	#define FME_IPERF_PROP_FAB_FREEZE PERF_PROP_FAB_ROOT(0x1) /* RW */
160	#define FME_IPERF_PROP_FAB_PCIE0_READ PERF_PROP_FAB_ROOT(0x2)
161	#define FME_IPERF_PROP_FAB_PORT_PCIE0_READ(n) PERF_PROP_FAB(n, 0x2)
162	#define FME_IPERF_PROP_FAB_PCIE0_WRITE PERF_PROP_FAB_ROOT(0x3)
163	#define FME_IPERF_PROP_FAB_PORT_PCIE0_WRITE(n) PERF_PROP_FAB(n, 0x3)
164	#define FME_IPERF_PROP_FAB_PCIE1_READ PERF_PROP_FAB_ROOT(0x4)
165	#define FME_IPERF_PROP_FAB_PORT_PCIE1_READ(n) PERF_PROP_FAB(n, 0x4)
166	#define FME_IPERF_PROP_FAB_PCIE1_WRITE PERF_PROP_FAB_ROOT(0x5)
167	#define FME_IPERF_PROP_FAB_PORT_PCIE1_WRITE(n) PERF_PROP_FAB(n, 0x5)
168	#define FME_IPERF_PROP_FAB_UPI_READ PERF_PROP_FAB_ROOT(0x6)
169	#define FME_IPERF_PROP_FAB_PORT_UPI_READ(n) PERF_PROP_FAB(n, 0x6)
170	#define FME_IPERF_PROP_FAB_UPI_WRITE PERF_PROP_FAB_ROOT(0x7)
171	#define FME_IPERF_PROP_FAB_PORT_UPI_WRITE(n) PERF_PROP_FAB(n, 0x7)
172	#define FME_IPERF_PROP_FAB_MMIO_READ PERF_PROP_FAB_ROOT(0x8)
173	#define FME_IPERF_PROP_FAB_PORT_MMIO_READ(n) PERF_PROP_FAB(n, 0x8)
174	#define FME_IPERF_PROP_FAB_MMIO_WRITE PERF_PROP_FAB_ROOT(0x9)
175	#define FME_IPERF_PROP_FAB_PORT_MMIO_WRITE(n) PERF_PROP_FAB(n, 0x9)
176	#define FME_IPERF_PROP_FAB_ENABLE PERF_PROP_FAB_ROOT(0xa) /* RW */
177	#define FME_IPERF_PROP_FAB_PORT_ENABLE(n) PERF_PROP_FAB(n, 0xa) /* RW */
178
179	/* FME dperf properties */
180	#define FME_DPERF_PROP_CLOCK PERF_PROP_ROOT(0x1)
181	#define FME_DPERF_PROP_REVISION PERF_PROP_ROOT(0x2)
182
183	/* dperf FAB properties */
184	#define FME_DPERF_PROP_FAB_FREEZE PERF_PROP_FAB_ROOT(0x1) /* RW */
185	#define FME_DPERF_PROP_FAB_PCIE0_READ PERF_PROP_FAB_ROOT(0x2)
186	#define FME_DPERF_PROP_FAB_PORT_PCIE0_READ(n) PERF_PROP_FAB(n, 0x2)
187	#define FME_DPERF_PROP_FAB_PCIE0_WRITE PERF_PROP_FAB_ROOT(0x3)
188	#define FME_DPERF_PROP_FAB_PORT_PCIE0_WRITE(n) PERF_PROP_FAB(n, 0x3)
189	#define FME_DPERF_PROP_FAB_MMIO_READ PERF_PROP_FAB_ROOT(0x4)
190	#define FME_DPERF_PROP_FAB_PORT_MMIO_READ(n) PERF_PROP_FAB(n, 0x4)
191	#define FME_DPERF_PROP_FAB_MMIO_WRITE PERF_PROP_FAB_ROOT(0x5)
192	#define FME_DPERF_PROP_FAB_PORT_MMIO_WRITE(n) PERF_PROP_FAB(n, 0x5)
193	#define FME_DPERF_PROP_FAB_ENABLE PERF_PROP_FAB_ROOT(0x6) /* RW */
194	#define FME_DPERF_PROP_FAB_PORT_ENABLE(n) PERF_PROP_FAB(n, 0x6) /* RW */
195
196	/PORT hdr feature's properties/
197	#define PORT_HDR_PROP_REVISION 0x1 /* RDONLY */
198	#define PORT_HDR_PROP_PORTIDX 0x2 /* RDONLY */
199	#define PORT_HDR_PROP_LATENCY_TOLERANCE 0x3 /* RDONLY */
200	#define PORT_HDR_PROP_AP1_EVENT 0x4 /* RW */
201	#define PORT_HDR_PROP_AP2_EVENT 0x5 /* RW */
202	#define PORT_HDR_PROP_POWER_STATE 0x6 /* RDONLY */
203	#define PORT_HDR_PROP_USERCLK_FREQCMD 0x7 /* RW */
204	#define PORT_HDR_PROP_USERCLK_FREQCNTRCMD 0x8 /* RW */
205	#define PORT_HDR_PROP_USERCLK_FREQSTS 0x9 /* RDONLY */
206	#define PORT_HDR_PROP_USERCLK_CNTRSTS 0xa /* RDONLY */
207
208	/PORT error feature's properties/
209	#define PORT_ERR_PROP_REVISION 0x1 /* RDONLY */
210	#define PORT_ERR_PROP_ERRORS 0x2 /* RDONLY */
211	#define PORT_ERR_PROP_FIRST_ERROR 0x3 /* RDONLY */
212	#define PORT_ERR_PROP_FIRST_MALFORMED_REQ_LSB 0x4 /* RDONLY */
213	#define PORT_ERR_PROP_FIRST_MALFORMED_REQ_MSB 0x5 /* RDONLY */
214	#define PORT_ERR_PROP_CLEAR 0x6 /* WRONLY */
215
216	int opae_manager_ifpga_get_prop(struct opae_manager *mgr,
217	struct feature_prop *prop);
218	int opae_manager_ifpga_set_prop(struct opae_manager *mgr,
219	struct feature_prop *prop);
220	int opae_bridge_ifpga_get_prop(struct opae_bridge *br,
221	struct feature_prop *prop);
222	int opae_bridge_ifpga_set_prop(struct opae_bridge *br,
223	struct feature_prop *prop);
224
225	/*
226	* Retrieve information about the fpga fme.
227	* Driver fills the info in provided struct fpga_fme_info.
228	*/
229	struct fpga_fme_info {
230	u32 capability; /* The capability of FME device */
231	#define FPGA_FME_CAP_ERR_IRQ (1 << 0) /* Support fme error interrupt */
232	};
233
234	int opae_manager_ifpga_get_info(struct opae_manager *mgr,
235	struct fpga_fme_info *fme_info);
236
237	/* Set eventfd information for ifpga FME error interrupt */
238	struct fpga_fme_err_irq_set {
239	s32 evtfd; /* Eventfd handler */
240	};
241
242	int opae_manager_ifpga_set_err_irq(struct opae_manager *mgr,
243	struct fpga_fme_err_irq_set *err_irq_set);
244
245	/*
246	* Retrieve information about the fpga port.
247	* Driver fills the info in provided struct fpga_port_info.
248	*/
249	struct fpga_port_info {
250	u32 capability; /* The capability of port device */
251	#define FPGA_PORT_CAP_ERR_IRQ (1 << 0) /* Support port error interrupt */
252	#define FPGA_PORT_CAP_UAFU_IRQ (1 << 1) /* Support uafu error interrupt */
253	u32 num_umsgs; /* The number of allocated umsgs */
254	u32 num_uafu_irqs; /* The number of uafu interrupts */
255	};
256
257	int opae_bridge_ifpga_get_info(struct opae_bridge *br,
258	struct fpga_port_info *port_info);
259	/*
260	* Retrieve region information about the fpga port.
261	* Driver needs to fill the index of struct fpga_port_region_info.
262	*/
263	struct fpga_port_region_info {
264	u32 index;
265	#define PORT_REGION_INDEX_STP (1 << 1) /* Signal Tap Region */
266	u64 size; /* Region Size */
267	u8 addr; / Base address of the region */
268	};
269
270	int opae_bridge_ifpga_get_region_info(struct opae_bridge *br,
271	struct fpga_port_region_info *info);
272
273	/* Set eventfd information for ifpga port error interrupt */
274	struct fpga_port_err_irq_set {
275	s32 evtfd; /* Eventfd handler */
276	};
277
278	int opae_bridge_ifpga_set_err_irq(struct opae_bridge *br,
279	struct fpga_port_err_irq_set *err_irq_set);
280
281	#endif /* _OPAE_IFPGA_HW_API_H_ */