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1 | /* SPDX-License-Identifier: BSD-3-Clause |
2 | * Copyright(c) 2018 Intel Corporation | |
3 | */ | |
4 | ||
5 | #ifndef _IFCVF_OSDEP_H_ | |
6 | #define _IFCVF_OSDEP_H_ | |
7 | ||
8 | #include <stdint.h> | |
9 | #include <linux/pci_regs.h> | |
10 | ||
11 | #include <rte_cycles.h> | |
12 | #include <rte_pci.h> | |
13 | #include <rte_bus_pci.h> | |
14 | #include <rte_log.h> | |
15 | #include <rte_io.h> | |
16 | ||
17 | #define DEBUGOUT(S, args...) RTE_LOG(DEBUG, PMD, S, ##args) | |
18 | #define STATIC static | |
19 | ||
9f95a23c | 20 | #define msec_delay(x) rte_delay_us_sleep(1000 * (x)) |
11fdf7f2 TL |
21 | |
22 | #define IFCVF_READ_REG8(reg) rte_read8(reg) | |
23 | #define IFCVF_WRITE_REG8(val, reg) rte_write8((val), (reg)) | |
24 | #define IFCVF_READ_REG16(reg) rte_read16(reg) | |
25 | #define IFCVF_WRITE_REG16(val, reg) rte_write16((val), (reg)) | |
26 | #define IFCVF_READ_REG32(reg) rte_read32(reg) | |
27 | #define IFCVF_WRITE_REG32(val, reg) rte_write32((val), (reg)) | |
28 | ||
29 | typedef struct rte_pci_device PCI_DEV; | |
30 | ||
31 | #define PCI_READ_CONFIG_BYTE(dev, val, where) \ | |
32 | rte_pci_read_config(dev, val, 1, where) | |
33 | ||
34 | #define PCI_READ_CONFIG_DWORD(dev, val, where) \ | |
35 | rte_pci_read_config(dev, val, 4, where) | |
36 | ||
37 | typedef uint8_t u8; | |
38 | typedef int8_t s8; | |
39 | typedef uint16_t u16; | |
40 | typedef int16_t s16; | |
41 | typedef uint32_t u32; | |
42 | typedef int32_t s32; | |
43 | typedef int64_t s64; | |
44 | typedef uint64_t u64; | |
45 | ||
46 | static inline int | |
47 | PCI_READ_CONFIG_RANGE(PCI_DEV *dev, uint32_t *val, int size, int where) | |
48 | { | |
49 | return rte_pci_read_config(dev, val, size, where); | |
50 | } | |
51 | ||
52 | #endif /* _IFCVF_OSDEP_H_ */ |