[ceph.git] / ceph / src / spdk / intel-ipsec-mb / sse / mb_mgr_hmac_flush_sse.asm

;;
;; Copyright (c) 2012-2018, Intel Corporation
;;
;; Redistribution and use in source and binary forms, with or without
;; modification, are permitted provided that the following conditions are met:
;;
;;     * Redistributions of source code must retain the above copyright notice,
;;       this list of conditions and the following disclaimer.
;;     * Redistributions in binary form must reproduce the above copyright
;;       notice, this list of conditions and the following disclaimer in the
;;       documentation and/or other materials provided with the distribution.
;;     * Neither the name of Intel Corporation nor the names of its contributors
;;       may be used to endorse or promote products derived from this software
;;       without specific prior written permission.
;;
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;

%include "include/os.asm"
%include "job_aes_hmac.asm"
%include "mb_mgr_datastruct.asm"
%include "include/reg_sizes.asm"

;%define DO_DBGPRINT
%include "include/dbgprint.asm"

extern sha1_mult_sse

section .data
default rel

align 16
byteswap:	;ddq 0x0c0d0e0f08090a0b0405060700010203
	dq 0x0405060700010203, 0x0c0d0e0f08090a0b
x80:    ;ddq 0x00000000000000000000000000000080
        dq 0x0000000000000080, 0x0000000000000000
x00:    ;ddq 0x00000000000000000000000000000000
        dq 0x0000000000000000, 0x0000000000000000
len_masks:
	;ddq 0x0000000000000000000000000000FFFF
	dq 0x000000000000FFFF, 0x0000000000000000
	;ddq 0x000000000000000000000000FFFF0000
	dq 0x00000000FFFF0000, 0x0000000000000000
	;ddq 0x00000000000000000000FFFF00000000
	dq 0x0000FFFF00000000, 0x0000000000000000
	;ddq 0x0000000000000000FFFF000000000000
	dq 0xFFFF000000000000, 0x0000000000000000
one:	dq  1
two:	dq  2
three:	dq  3

section .text

%if 1
%ifdef LINUX
%define arg1	rdi
%define arg2	rsi
%else
%define arg1	rcx
%define arg2	rdx
%endif

%define state	arg1
%define job	arg2
%define len2	arg2


; idx needs to be in rbx, rbp, r12-r15
%define idx             rbp

%define unused_lanes    rbx
%define lane_data       rbx
%define tmp2		rbx

%define job_rax         rax
%define	tmp1		rax
%define size_offset     rax
%define tmp             rax
%define start_offset    rax

%define tmp3		arg1

%define extra_blocks    arg2
%define p               arg2

%define tmp4		r8

%endif

; This routine clobbers rbx, rbp
struc STACK
_gpr_save:	resq	2
_rsp_save:	resq	1
endstruc

%define APPEND(a,b) a %+ b

; JOB* flush_job_hmac_sse(MB_MGR_HMAC_SHA_1_OOO *state)
; arg 1 : state
MKGLOBAL(flush_job_hmac_sse,function,internal)
flush_job_hmac_sse:

        mov	rax, rsp
        sub	rsp, STACK_size
        and	rsp, -16

	mov	[rsp + _gpr_save + 8*0], rbx
	mov	[rsp + _gpr_save + 8*1], rbp
	mov	[rsp + _rsp_save], rax	; original SP

         DBGPRINTL "enter sha1-sse flush"
	mov	unused_lanes, [state + _unused_lanes]
	bt	unused_lanes, 32+7
	jc	return_null

	; find a lane with a non-null job
	xor	idx, idx
	cmp	qword [state + _ldata + 1 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
	cmovne	idx, [rel one]
	cmp	qword [state + _ldata + 2 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
	cmovne	idx, [rel two]
	cmp	qword [state + _ldata + 3 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
	cmovne	idx, [rel three]
copy_lane_data:
	; copy valid lane (idx) to empty lanes
	movdqa	xmm0, [state + _lens]
	mov	tmp, [state + _args_data_ptr + PTR_SZ*idx]

%assign I 0
%rep 4
	cmp	qword [state + _ldata + I * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
	jne	APPEND(skip_,I)
	mov	[state + _args_data_ptr + PTR_SZ*I], tmp
	por	xmm0, [rel len_masks + 16*I]
APPEND(skip_,I):
%assign I (I+1)
%endrep

	movdqa	[state + _lens], xmm0

	phminposuw	xmm1, xmm0
	pextrw	len2, xmm1, 0	; min value
	pextrw	idx, xmm1, 1	; min index (0...3)
	cmp	len2, 0
	je	len_is_0

	pshuflw	xmm1, xmm1, 0
	psubw	xmm0, xmm1
	movdqa	[state + _lens], xmm0

	; "state" and "args" are the same address, arg1
	; len is arg2
	call	sha1_mult_sse
	; state is intact

len_is_0:
	; process completed job "idx"
	imul	lane_data, idx, _HMAC_SHA1_LANE_DATA_size
	lea	lane_data, [state + _ldata + lane_data]
	mov	DWORD(extra_blocks), [lane_data + _extra_blocks]
	cmp	extra_blocks, 0
	jne	proc_extra_blocks
	cmp	dword [lane_data + _outer_done], 0
	jne	end_loop

proc_outer:
	mov	dword [lane_data + _outer_done], 1
	mov	DWORD(size_offset), [lane_data + _size_offset]
	mov	qword [lane_data + _extra_block + size_offset], 0
	mov	word [state + _lens + 2*idx], 1
	lea	tmp, [lane_data + _outer_block]
	mov	job, [lane_data + _job_in_lane]
	mov	[state + _args_data_ptr + PTR_SZ*idx], tmp

        ;; idx determines which column
        ;; read off from consecutive rows
	movd	xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 0*SHA1_DIGEST_ROW_SIZE]
	pinsrd	xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 1*SHA1_DIGEST_ROW_SIZE], 1
	pinsrd	xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 2*SHA1_DIGEST_ROW_SIZE], 2
	pinsrd	xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 3*SHA1_DIGEST_ROW_SIZE], 3
	pshufb	xmm0, [rel byteswap]
	mov	DWORD(tmp),  [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 4*SHA1_DIGEST_ROW_SIZE]
	bswap	DWORD(tmp)
	movdqa	[lane_data + _outer_block], xmm0
	mov	[lane_data + _outer_block + 4*4], DWORD(tmp)
        DBGPRINTL_XMM "sha1 outer hash input words[0-3]", xmm0
        DBGPRINTL64 "sha1 outer hash input word 4", tmp
	mov	tmp, [job + _auth_key_xor_opad]
	movdqu	xmm0, [tmp]
	mov	DWORD(tmp),  [tmp + 4*4]
	movd	[state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 0*SHA1_DIGEST_ROW_SIZE], xmm0
	pextrd	[state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 1*SHA1_DIGEST_ROW_SIZE], xmm0, 1
	pextrd	[state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 2*SHA1_DIGEST_ROW_SIZE], xmm0, 2
	pextrd	[state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 3*SHA1_DIGEST_ROW_SIZE], xmm0, 3
	mov	[state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 4*SHA1_DIGEST_ROW_SIZE], DWORD(tmp)

	jmp	copy_lane_data

	align	16
proc_extra_blocks:
	mov	DWORD(start_offset), [lane_data + _start_offset]
	mov	[state + _lens + 2*idx], WORD(extra_blocks)
	lea	tmp, [lane_data + _extra_block + start_offset]
	mov	[state + _args_data_ptr + PTR_SZ*idx], tmp
	mov	dword [lane_data + _extra_blocks], 0
	jmp	copy_lane_data

return_null:
	xor	job_rax, job_rax
	jmp	return

	align	16
end_loop:
	mov	job_rax, [lane_data + _job_in_lane]
	mov	qword [lane_data + _job_in_lane], 0
	or	dword [job_rax + _status], STS_COMPLETED_HMAC
	mov	unused_lanes, [state + _unused_lanes]
	shl	unused_lanes, 8
	or	unused_lanes, idx
	mov	[state + _unused_lanes], unused_lanes

	mov	p, [job_rax + _auth_tag_output]

	; copy 12 bytes
	mov	DWORD(tmp2), [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 0*SHA1_DIGEST_ROW_SIZE]
	mov	DWORD(tmp4), [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 1*SHA1_DIGEST_ROW_SIZE]
	bswap	DWORD(tmp2)
	bswap	DWORD(tmp4)
	mov	[p + 0*4], DWORD(tmp2)
	mov	[p + 1*4], DWORD(tmp4)
	mov	DWORD(tmp2), [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 2*SHA1_DIGEST_ROW_SIZE]
	bswap	DWORD(tmp2)
	mov	[p + 2*4], DWORD(tmp2)

        cmp     qword [job_rax + _auth_tag_output_len_in_bytes], 12
        je      clear_ret

        ;; copy remaining 8 bytes to return 20 byte digest
        mov	DWORD(tmp2),  [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 3*SHA1_DIGEST_ROW_SIZE]
        mov	DWORD(tmp4), [state + _args_digest + SHA1_DIGEST_WORD_SIZE*idx + 4*SHA1_DIGEST_ROW_SIZE]
        bswap	DWORD(tmp2)
        bswap	DWORD(tmp4)
        mov	[p + 3*SHA1_DIGEST_WORD_SIZE], DWORD(tmp2)
        mov	[p + 4*SHA1_DIGEST_WORD_SIZE], DWORD(tmp4)

clear_ret:

%ifdef SAFE_DATA
        pxor    xmm0, xmm0

        ;; Clear digest (20B), outer_block (20B) and extra_block (64B)
        ;; of returned job and NULL jobs
%assign I 0
%rep 4
	cmp	qword [state + _ldata + (I*_HMAC_SHA1_LANE_DATA_size) + _job_in_lane], 0
	jne	APPEND(skip_clear_,I)

        ;; Clear digest
        mov     dword [state + _args_digest + SHA1_DIGEST_WORD_SIZE*I + 0*SHA1_DIGEST_ROW_SIZE], 0
        mov     dword [state + _args_digest + SHA1_DIGEST_WORD_SIZE*I + 1*SHA1_DIGEST_ROW_SIZE], 0
        mov     dword [state + _args_digest + SHA1_DIGEST_WORD_SIZE*I + 2*SHA1_DIGEST_ROW_SIZE], 0
        mov     dword [state + _args_digest + SHA1_DIGEST_WORD_SIZE*I + 3*SHA1_DIGEST_ROW_SIZE], 0
        mov     dword [state + _args_digest + SHA1_DIGEST_WORD_SIZE*I + 4*SHA1_DIGEST_ROW_SIZE], 0

        lea     lane_data, [state + _ldata + (I*_HMAC_SHA1_LANE_DATA_size)]
        ;; Clear first 64 bytes of extra_block
%assign offset 0
%rep 4
        movdqa  [lane_data + _extra_block + offset], xmm0
%assign offset (offset + 16)
%endrep

        ;; Clear first 20 bytes of outer_block
        movdqa  [lane_data + _outer_block], xmm0
        mov     dword [lane_data + _outer_block + 16], 0

APPEND(skip_clear_,I):
%assign I (I+1)
%endrep

%endif ;; SAFE_DATA

return:

	mov	rbx, [rsp + _gpr_save + 8*0]
	mov	rbp, [rsp + _gpr_save + 8*1]
	mov	rsp, [rsp + _rsp_save]	; original SP

	ret

%ifdef LINUX
section .note.GNU-stack noalloc noexec nowrite progbits
%endif
Commit	Line	Data
11fdf7f2 TL	1	;;
	2	;; Copyright (c) 2012-2018, Intel Corporation
	3	;;
	4	;; Redistribution and use in source and binary forms, with or without
	5	;; modification, are permitted provided that the following conditions are met:
	6	;;
	7	;; * Redistributions of source code must retain the above copyright notice,
	8	;; this list of conditions and the following disclaimer.
	9	;; * Redistributions in binary form must reproduce the above copyright
	10	;; notice, this list of conditions and the following disclaimer in the
	11	;; documentation and/or other materials provided with the distribution.
	12	;; * Neither the name of Intel Corporation nor the names of its contributors
	13	;; may be used to endorse or promote products derived from this software
	14	;; without specific prior written permission.
	15	;;
	16	;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	19	;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
	20	;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	21	;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	22	;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	23	;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	24	;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	25	;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	;;
	27
f67539c2	28	%include "include/os.asm"
11fdf7f2 TL	29	%include "job_aes_hmac.asm"
11fdf7f2 TL	30	%include "mb_mgr_datastruct.asm"
f67539c2	31	%include "include/reg_sizes.asm"
11fdf7f2 TL	32
11fdf7f2 TL	33	;%define DO_DBGPRINT
f67539c2	34	%include "include/dbgprint.asm"
11fdf7f2 TL	35
	36	extern sha1_mult_sse
	37
	38	section .data
	39	default rel
	40
	41	align 16
	42	byteswap: ;ddq 0x0c0d0e0f08090a0b0405060700010203
	43	dq 0x0405060700010203, 0x0c0d0e0f08090a0b
	44	x80: ;ddq 0x00000000000000000000000000000080
	45	dq 0x0000000000000080, 0x0000000000000000
	46	x00: ;ddq 0x00000000000000000000000000000000
	47	dq 0x0000000000000000, 0x0000000000000000
	48	len_masks:
	49	;ddq 0x0000000000000000000000000000FFFF
	50	dq 0x000000000000FFFF, 0x0000000000000000
	51	;ddq 0x000000000000000000000000FFFF0000
	52	dq 0x00000000FFFF0000, 0x0000000000000000
	53	;ddq 0x00000000000000000000FFFF00000000
	54	dq 0x0000FFFF00000000, 0x0000000000000000
	55	;ddq 0x0000000000000000FFFF000000000000
	56	dq 0xFFFF000000000000, 0x0000000000000000
	57	one: dq 1
	58	two: dq 2
	59	three: dq 3
	60
	61	section .text
	62
	63	%if 1
	64	%ifdef LINUX
	65	%define arg1 rdi
	66	%define arg2 rsi
	67	%else
	68	%define arg1 rcx
	69	%define arg2 rdx
	70	%endif
	71
	72	%define state arg1
	73	%define job arg2
	74	%define len2 arg2
	75
	76
	77	; idx needs to be in rbx, rbp, r12-r15
	78	%define idx rbp
	79
	80	%define unused_lanes rbx
	81	%define lane_data rbx
	82	%define tmp2 rbx
	83
	84	%define job_rax rax
	85	%define tmp1 rax
	86	%define size_offset rax
	87	%define tmp rax
	88	%define start_offset rax
	89
	90	%define tmp3 arg1
	91
	92	%define extra_blocks arg2
	93	%define p arg2
	94
	95	%define tmp4 r8
	96
	97	%endif
	98
99	; This routine clobbers rbx, rbp
100	struc STACK
101	_gpr_save: resq 2
102	_rsp_save: resq 1
103	endstruc
104
105	%define APPEND(a,b) a %+ b
106
107	; JOB* flush_job_hmac_sse(MB_MGR_HMAC_SHA_1_OOO *state)
108	; arg 1 : state
109	MKGLOBAL(flush_job_hmac_sse,function,internal)
110	flush_job_hmac_sse:
111
112	mov rax, rsp
113	sub rsp, STACK_size
114	and rsp, -16
115
116	mov [rsp + _gpr_save + 8*0], rbx
117	mov [rsp + _gpr_save + 8*1], rbp
118	mov [rsp + _rsp_save], rax ; original SP
119
120	DBGPRINTL "enter sha1-sse flush"
121	mov unused_lanes, [state + _unused_lanes]
122	bt unused_lanes, 32+7
123	jc return_null
124
125	; find a lane with a non-null job
126	xor idx, idx
127	cmp qword [state + _ldata + 1 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
128	cmovne idx, [rel one]
129	cmp qword [state + _ldata + 2 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
130	cmovne idx, [rel two]
131	cmp qword [state + _ldata + 3 * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
132	cmovne idx, [rel three]
133	copy_lane_data:
134	; copy valid lane (idx) to empty lanes
135	movdqa xmm0, [state + _lens]
136	mov tmp, [state + _args_data_ptr + PTR_SZ*idx]
137
138	%assign I 0
139	%rep 4
140	cmp qword [state + _ldata + I * _HMAC_SHA1_LANE_DATA_size + _job_in_lane], 0
141	jne APPEND(skip_,I)
142	mov [state + _args_data_ptr + PTR_SZ*I], tmp
143	por xmm0, [rel len_masks + 16*I]
144	APPEND(skip_,I):
145	%assign I (I+1)
146	%endrep
147
148	movdqa [state + _lens], xmm0
149
150	phminposuw xmm1, xmm0
151	pextrw len2, xmm1, 0 ; min value
152	pextrw idx, xmm1, 1 ; min index (0...3)
153	cmp len2, 0
154	je len_is_0
155
156	pshuflw xmm1, xmm1, 0
157	psubw xmm0, xmm1
158	movdqa [state + _lens], xmm0
159
160	; "state" and "args" are the same address, arg1
161	; len is arg2
162	call sha1_mult_sse
163	; state is intact
164
165	len_is_0:
166	; process completed job "idx"
167	imul lane_data, idx, _HMAC_SHA1_LANE_DATA_size
168	lea lane_data, [state + _ldata + lane_data]
169	mov DWORD(extra_blocks), [lane_data + _extra_blocks]
170	cmp extra_blocks, 0
171	jne proc_extra_blocks
172	cmp dword [lane_data + _outer_done], 0
173	jne end_loop
174
175	proc_outer:
176	mov dword [lane_data + _outer_done], 1
177	mov DWORD(size_offset), [lane_data + _size_offset]
178	mov qword [lane_data + _extra_block + size_offset], 0
179	mov word [state + _lens + 2*idx], 1
180	lea tmp, [lane_data + _outer_block]
181	mov job, [lane_data + _job_in_lane]
182	mov [state + _args_data_ptr + PTR_SZ*idx], tmp
183
184	;; idx determines which column
185	;; read off from consecutive rows
186	movd xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 0SHA1_DIGEST_ROW_SIZE]
187	pinsrd xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 1SHA1_DIGEST_ROW_SIZE], 1
188	pinsrd xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 2SHA1_DIGEST_ROW_SIZE], 2
189	pinsrd xmm0, [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 3SHA1_DIGEST_ROW_SIZE], 3
190	pshufb xmm0, [rel byteswap]
191	mov DWORD(tmp), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 4SHA1_DIGEST_ROW_SIZE]
192	bswap DWORD(tmp)
193	movdqa [lane_data + _outer_block], xmm0
194	mov [lane_data + _outer_block + 4*4], DWORD(tmp)
195	DBGPRINTL_XMM "sha1 outer hash input words[0-3]", xmm0
196	DBGPRINTL64 "sha1 outer hash input word 4", tmp
197	mov tmp, [job + _auth_key_xor_opad]
198	movdqu xmm0, [tmp]
199	mov DWORD(tmp), [tmp + 4*4]
200	movd [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 0SHA1_DIGEST_ROW_SIZE], xmm0
201	pextrd [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 1SHA1_DIGEST_ROW_SIZE], xmm0, 1
202	pextrd [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 2SHA1_DIGEST_ROW_SIZE], xmm0, 2
203	pextrd [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 3SHA1_DIGEST_ROW_SIZE], xmm0, 3
204	mov [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 4SHA1_DIGEST_ROW_SIZE], DWORD(tmp)
205
206	jmp copy_lane_data
207
208	align 16
209	proc_extra_blocks:
210	mov DWORD(start_offset), [lane_data + _start_offset]
211	mov [state + _lens + 2*idx], WORD(extra_blocks)
212	lea tmp, [lane_data + _extra_block + start_offset]
213	mov [state + _args_data_ptr + PTR_SZ*idx], tmp
214	mov dword [lane_data + _extra_blocks], 0
215	jmp copy_lane_data
216
217	return_null:
218	xor job_rax, job_rax
219	jmp return
220
221	align 16
222	end_loop:
223	mov job_rax, [lane_data + _job_in_lane]
224	mov qword [lane_data + _job_in_lane], 0
225	or dword [job_rax + _status], STS_COMPLETED_HMAC
226	mov unused_lanes, [state + _unused_lanes]
227	shl unused_lanes, 8
228	or unused_lanes, idx
229	mov [state + _unused_lanes], unused_lanes
230
231	mov p, [job_rax + _auth_tag_output]
232
233	; copy 12 bytes
234	mov DWORD(tmp2), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 0SHA1_DIGEST_ROW_SIZE]
235	mov DWORD(tmp4), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 1SHA1_DIGEST_ROW_SIZE]
11fdf7f2 TL	236	bswap DWORD(tmp2)
11fdf7f2 TL	237	bswap DWORD(tmp4)
11fdf7f2 TL	238	mov [p + 0*4], DWORD(tmp2)
11fdf7f2 TL	239	mov [p + 1*4], DWORD(tmp4)
9f95a23c TL	240	mov DWORD(tmp2), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 2SHA1_DIGEST_ROW_SIZE]
	241	bswap DWORD(tmp2)
	242	mov [p + 2*4], DWORD(tmp2)
	243
	244	cmp qword [job_rax + _auth_tag_output_len_in_bytes], 12
f67539c2	245	je clear_ret
9f95a23c TL	246
	247	;; copy remaining 8 bytes to return 20 byte digest
	248	mov DWORD(tmp2), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 3SHA1_DIGEST_ROW_SIZE]
	249	mov DWORD(tmp4), [state + _args_digest + SHA1_DIGEST_WORD_SIZEidx + 4SHA1_DIGEST_ROW_SIZE]
	250	bswap DWORD(tmp2)
	251	bswap DWORD(tmp4)
	252	mov [p + 3*SHA1_DIGEST_WORD_SIZE], DWORD(tmp2)
	253	mov [p + 4*SHA1_DIGEST_WORD_SIZE], DWORD(tmp4)
11fdf7f2	254
f67539c2 TL	255	clear_ret:
	256
	257	%ifdef SAFE_DATA
	258	pxor xmm0, xmm0
	259
	260	;; Clear digest (20B), outer_block (20B) and extra_block (64B)
	261	;; of returned job and NULL jobs
	262	%assign I 0
	263	%rep 4
	264	cmp qword [state + _ldata + (I*_HMAC_SHA1_LANE_DATA_size) + _job_in_lane], 0
	265	jne APPEND(skip_clear_,I)
	266
	267	;; Clear digest
	268	mov dword [state + _args_digest + SHA1_DIGEST_WORD_SIZEI + 0SHA1_DIGEST_ROW_SIZE], 0
	269	mov dword [state + _args_digest + SHA1_DIGEST_WORD_SIZEI + 1SHA1_DIGEST_ROW_SIZE], 0
	270	mov dword [state + _args_digest + SHA1_DIGEST_WORD_SIZEI + 2SHA1_DIGEST_ROW_SIZE], 0
	271	mov dword [state + _args_digest + SHA1_DIGEST_WORD_SIZEI + 3SHA1_DIGEST_ROW_SIZE], 0
	272	mov dword [state + _args_digest + SHA1_DIGEST_WORD_SIZEI + 4SHA1_DIGEST_ROW_SIZE], 0
	273
	274	lea lane_data, [state + _ldata + (I*_HMAC_SHA1_LANE_DATA_size)]
	275	;; Clear first 64 bytes of extra_block
	276	%assign offset 0
	277	%rep 4
	278	movdqa [lane_data + _extra_block + offset], xmm0
	279	%assign offset (offset + 16)
	280	%endrep
	281
	282	;; Clear first 20 bytes of outer_block
	283	movdqa [lane_data + _outer_block], xmm0
	284	mov dword [lane_data + _outer_block + 16], 0
	285
	286	APPEND(skip_clear_,I):
	287	%assign I (I+1)
	288	%endrep
	289
	290	%endif ;; SAFE_DATA
	291
11fdf7f2 TL	292	return:
	293
	294	mov rbx, [rsp + _gpr_save + 8*0]
	295	mov rbp, [rsp + _gpr_save + 8*1]
	296	mov rsp, [rsp + _rsp_save] ; original SP
	297
	298	ret
	299
	300	%ifdef LINUX
	301	section .note.GNU-stack noalloc noexec nowrite progbits
	302	%endif