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ArmPkg: Added Aarch64 support
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88d4f51d 1/** @file\r
2\r
b1d41be7 3 Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
88d4f51d 4\r
5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include <Base.h>\r
16#include <Library/ArmLib.h>\r
17#include <Library/ArmCpuLib.h>\r
25402f5d 18#include <Library/ArmArchTimerLib.h>\r
88d4f51d 19#include <Library/DebugLib.h>\r
20#include <Library/IoLib.h>\r
21#include <Library/PcdLib.h>\r
22\r
9d59a88b 23#include <Chipset/ArmCortexA15.h>\r
88d4f51d 24\r
88d4f51d 25VOID\r
26ArmCpuSetup (\r
27 IN UINTN MpId\r
28 )\r
29{\r
30 // Check if Architectural Timer frequency is valid number (should not be 0)\r
31 ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));\r
32 ASSERT(ArmIsArchTimerImplemented () != 0);\r
33\r
34 // Enable SWP instructions\r
35 ArmEnableSWPInstruction ();\r
36\r
37 // Enable program flow prediction, if supported.\r
38 ArmEnableBranchPrediction ();\r
39\r
40 // Note: System Counter frequency can only be set in Secure privileged mode,\r
41 // if security extensions are implemented.\r
42 ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));\r
43\r
88d4f51d 44 if (ArmIsMpCore()) {\r
9d59a88b 45 // Turn on SMP coherency\r
46 ArmSetAuxCrBit (A15_FEATURE_SMP);\r
47 }\r
48\r
88d4f51d 49}\r
50\r
51\r
52VOID\r
53ArmCpuSetupSmpNonSecure (\r
54 IN UINTN MpId\r
55 )\r
56{\r
88d4f51d 57 /*// Make the SCU accessible in Non Secure world\r
bebda7ce 58 if (ArmPlatformIsPrimaryCore (MpId)) {\r
88d4f51d 59 ScuBase = ArmGetScuBaseAddress();\r
60\r
61 // Allow NS access to SCU register\r
62 MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);\r
63 // Allow NS access to Private Peripherals\r
64 MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);\r
65 }*/\r
66}\r