projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 88d4f51d | 1 | /** @file\r |
| 2 | \r | |
| b1d41be7 | 3 | Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
| 88d4f51d | 4 | \r |
| 5 | This program and the accompanying materials\r | |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #include <Base.h>\r | |
| 16 | #include <Library/ArmLib.h>\r | |
| 17 | #include <Library/ArmCpuLib.h>\r | |
| 4f6d34b4 | 18 | #include <Library/ArmGenericTimerCounterLib.h>\r |
| 88d4f51d | 19 | #include <Library/DebugLib.h>\r |
| 88d4f51d | 20 | #include <Library/PcdLib.h>\r |
| 21 | \r | |
| 3535213a LL |
22 | #include <Chipset/ArmV7.h>\r |
| 23 | \r | |
| 24 | #define A15_FEATURE_SMP (1<<6)\r | |
| 88d4f51d | 25 | \r |
| 88d4f51d | 26 | VOID\r |
| 27 | ArmCpuSetup (\r | |
| 28 | IN UINTN MpId\r | |
| 29 | )\r | |
| 30 | {\r | |
| 31 | // Check if Architectural Timer frequency is valid number (should not be 0)\r | |
| 32 | ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));\r | |
| 33 | ASSERT(ArmIsArchTimerImplemented () != 0);\r | |
| 34 | \r | |
| 35 | // Enable SWP instructions\r | |
| 36 | ArmEnableSWPInstruction ();\r | |
| 37 | \r | |
| 38 | // Enable program flow prediction, if supported.\r | |
| 39 | ArmEnableBranchPrediction ();\r | |
| 40 | \r | |
| 41 | // Note: System Counter frequency can only be set in Secure privileged mode,\r | |
| 42 | // if security extensions are implemented.\r | |
| 4f6d34b4 | 43 | ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));\r |
| 88d4f51d | 44 | \r |
| 88d4f51d | 45 | if (ArmIsMpCore()) {\r |
| 9d59a88b | 46 | // Turn on SMP coherency\r |
| 47 | ArmSetAuxCrBit (A15_FEATURE_SMP);\r | |
| 48 | }\r | |
| 49 | \r | |
| 88d4f51d | 50 | }\r |
| 51 | \r | |
| 52 | \r | |
| 53 | VOID\r | |
| 54 | ArmCpuSetupSmpNonSecure (\r | |
| 55 | IN UINTN MpId\r | |
| 56 | )\r | |
| 57 | {\r | |
| 88d4f51d | 58 | /*// Make the SCU accessible in Non Secure world\r |
| bebda7ce | 59 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
| 88d4f51d | 60 | ScuBase = ArmGetScuBaseAddress();\r |
| 61 | \r | |
| 62 | // Allow NS access to SCU register\r | |
| 63 | MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);\r | |
| 64 | // Allow NS access to Private Peripherals\r | |
| 65 | MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);\r | |
| 66 | }*/\r | |
| 67 | }\r |