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ArmPkg: Move TimerDxe and ArmArchTimerLib to new ArmGenericTimerCounterLib
[mirror_edk2.git] / ArmPkg / Drivers / ArmCpuLib / ArmCortexA15Lib / ArmCortexA15Lib.c
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88d4f51d 1/** @file\r
2\r
b1d41be7 3 Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
88d4f51d 4\r
5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include <Base.h>\r
16#include <Library/ArmLib.h>\r
17#include <Library/ArmCpuLib.h>\r
4f6d34b4 18#include <Library/ArmGenericTimerCounterLib.h>\r
88d4f51d 19#include <Library/DebugLib.h>\r
88d4f51d 20#include <Library/PcdLib.h>\r
21\r
9d59a88b 22#include <Chipset/ArmCortexA15.h>\r
88d4f51d 23\r
88d4f51d 24VOID\r
25ArmCpuSetup (\r
26 IN UINTN MpId\r
27 )\r
28{\r
29 // Check if Architectural Timer frequency is valid number (should not be 0)\r
30 ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));\r
31 ASSERT(ArmIsArchTimerImplemented () != 0);\r
32\r
33 // Enable SWP instructions\r
34 ArmEnableSWPInstruction ();\r
35\r
36 // Enable program flow prediction, if supported.\r
37 ArmEnableBranchPrediction ();\r
38\r
39 // Note: System Counter frequency can only be set in Secure privileged mode,\r
40 // if security extensions are implemented.\r
4f6d34b4 41 ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));\r
88d4f51d 42\r
88d4f51d 43 if (ArmIsMpCore()) {\r
9d59a88b 44 // Turn on SMP coherency\r
45 ArmSetAuxCrBit (A15_FEATURE_SMP);\r
46 }\r
47\r
88d4f51d 48}\r
49\r
50\r
51VOID\r
52ArmCpuSetupSmpNonSecure (\r
53 IN UINTN MpId\r
54 )\r
55{\r
88d4f51d 56 /*// Make the SCU accessible in Non Secure world\r
bebda7ce 57 if (ArmPlatformIsPrimaryCore (MpId)) {\r
88d4f51d 58 ScuBase = ArmGetScuBaseAddress();\r
59\r
60 // Allow NS access to SCU register\r
61 MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);\r
62 // Allow NS access to Private Peripherals\r
63 MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);\r
64 }*/\r
65}\r