projects / mirror_edk2.git / blame
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|---|---|---|
| 25402f5d HL |
1 | /** @file\r |
| 2 | \r | |
| cf02da52 | 3 | Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
| 25402f5d HL |
4 | \r |
| 5 | This program and the accompanying materials\r | |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #include <Base.h>\r | |
| 16 | #include <Library/ArmLib.h>\r | |
| 17 | #include <Library/ArmCpuLib.h>\r | |
| d4bb43ce | 18 | #include <Library/ArmArchTimer.h>\r |
| 25402f5d HL |
19 | #include <Library/DebugLib.h>\r |
| 20 | #include <Library/IoLib.h>\r | |
| 21 | #include <Library/PcdLib.h>\r | |
| 22 | \r | |
| 23 | #include <Chipset/ArmCortexA5x.h>\r | |
| 24 | \r | |
| 25 | VOID\r | |
| 26 | ArmCpuSetup (\r | |
| 27 | IN UINTN MpId\r | |
| 28 | )\r | |
| 29 | {\r | |
| 30 | // Check if Architectural Timer frequency is valid number (should not be 0)\r | |
| 31 | ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));\r | |
| 32 | ASSERT (ArmIsArchTimerImplemented () != 0);\r | |
| 33 | \r | |
| 34 | // Note: System Counter frequency can only be set in Secure privileged mode,\r | |
| 35 | // if security extensions are implemented.\r | |
| 36 | ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));\r | |
| 37 | \r | |
| 38 | if (ArmIsMpCore ()) {\r | |
| 39 | // Turn on SMP coherency\r | |
| cf02da52 | 40 | ArmSetCpuExCrBit (A5X_FEATURE_SMP);\r |
| 25402f5d HL |
41 | }\r |
| 42 | \r | |
| 44372159 OM |
43 | //\r |
| 44 | // If CPU is CortexA57 r0p0 apply Errata: 806969\r | |
| 45 | //\r | |
| 46 | if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==\r | |
| 47 | ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {\r | |
| 48 | // DisableLoadStoreWB\r | |
| 49 | ArmSetCpuActlrBit (1ULL << 49);\r | |
| 50 | }\r | |
| 25402f5d HL |
51 | }\r |
| 52 | \r | |
| 53 | VOID\r | |
| 54 | ArmCpuSetupSmpNonSecure (\r | |
| 55 | IN UINTN MpId\r | |
| 56 | )\r | |
| 57 | {\r | |
| 58 | }\r | |
| 47d183db OM |
59 | \r |
| 60 | VOID\r | |
| 61 | EFIAPI\r | |
| 62 | ArmSetCpuExCrBit (\r | |
| 63 | IN UINT64 Bits\r | |
| 64 | )\r | |
| 65 | {\r | |
| 66 | UINT64 Value;\r | |
| 67 | Value = ArmReadCpuExCr ();\r | |
| 68 | Value |= Bits;\r | |
| 69 | ArmWriteCpuExCr (Value);\r | |
| 70 | }\r | |
| 71 | \r | |
| 72 | VOID\r | |
| 73 | EFIAPI\r | |
| 74 | ArmUnsetCpuExCrBit (\r | |
| 75 | IN UINT64 Bits\r | |
| 76 | )\r | |
| 77 | {\r | |
| 78 | UINT64 Value;\r | |
| 79 | Value = ArmReadCpuExCr ();\r | |
| 80 | Value &= ~Bits;\r | |
| 81 | ArmWriteCpuExCr (Value);\r | |
| 82 | }\r |