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3127615b | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <Base.h>\r | |
16 | #include <Library/ArmLib.h>\r | |
17 | #include <Library/ArmCpuLib.h>\r | |
18 | #include <Library/DebugLib.h>\r | |
19 | \r | |
20 | #include <Chipset/ArmV7.h>\r | |
21 | \r | |
3127615b | 22 | VOID\r |
23 | ArmCpuSetup (\r | |
24 | IN UINTN MpId\r | |
25 | )\r | |
26 | {\r | |
27 | // Enable SWP instructions\r | |
28 | ArmEnableSWPInstruction ();\r | |
29 | \r | |
30 | // Enable program flow prediction, if supported.\r | |
31 | ArmEnableBranchPrediction ();\r | |
32 | }\r | |
33 | \r | |
34 | VOID\r | |
35 | ArmCpuSetupSmpNonSecure (\r | |
36 | IN UINTN MpId\r | |
37 | )\r | |
38 | {\r | |
39 | // The CortexA8 is a Unicore CPU. We must not initialize SMP for Non Secure Accesses\r | |
40 | ASSERT(0);\r | |
41 | }\r |