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1 | //\r |
| 2 | // Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 3 | //\r |
| 4 | // This program and the accompanying materials\r |
| 5 | // are licensed and made available under the terms and conditions of the BSD License\r |
| 6 | // which accompanies this distribution. The full text of the license may be found at\r |
| 7 | // http://opensource.org/licenses/bsd-license.php\r |
| 8 | //\r |
| 9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 11 | //\r |
| 12 | //\r |
| 13 | \r |
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14 | #include <AsmMacroIoLib.h>\r |
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15 | #include <Library/ArmCpuLib.h>\r |
| 16 | #include <Chipset/ArmCortexA9.h>\r |
| 17 | \r |
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18 | INCLUDE AsmMacroIoLib.inc\r |
| 19 | \r |
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20 | EXPORT ArmCpuSynchronizeWait\r |
| 21 | EXPORT ArmGetScuBaseAddress\r |
| 22 | IMPORT CArmCpuSynchronizeWait\r |
| 23 | \r |
| 24 | PRESERVE8\r |
| 25 | AREA ArmCortexA9Helper, CODE, READONLY\r |
| 26 | \r |
| 27 | // VOID\r |
| 28 | // ArmCpuSynchronizeWait (\r |
| 29 | // IN ARM_CPU_SYNCHRONIZE_EVENT Event\r |
| 30 | // );\r |
| 31 | ArmCpuSynchronizeWait\r |
| 32 | cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r |
| 33 | // The SCU enabled is the event to tell us the Init Boot Memory is initialized\r |
| 34 | beq ArmWaitScuEnabled\r |
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35 | // Case when the stack has been set up\r |
| 36 | push {r1,lr}\r |
| 37 | LoadConstantToReg (CArmCpuSynchronizeWait, r1)\r |
| 38 | blx r1\r |
| 39 | pop {r1,lr}\r |
| 40 | bx lr\r |
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41 | \r |
| 42 | // IN None\r |
| 43 | // OUT r0 = SCU Base Address\r |
| 44 | ArmGetScuBaseAddress\r |
| 45 | // Read Configuration Base Address Register. ArmCBar cannot be called to get\r |
| 46 | // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r |
| 47 | // offset 0x0000 from the Private Memory Region.\r |
| 48 | mrc p15, 4, r0, c15, c0, 0\r |
| 49 | bx lr\r |
| 50 | \r |
| 51 | ArmWaitScuEnabled\r |
| 52 | // Read Configuration Base Address Register. ArmCBar cannot be called to get\r |
| 53 | // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r |
| 54 | // offset 0x0000 from the Private Memory Region.\r |
| 55 | mrc p15, 4, r0, c15, c0, 0\r |
| 56 | add r0, r0, #A9_SCU_CONTROL_OFFSET\r |
| 57 | ldr r0, [r0]\r |
| 58 | cmp r0, #1\r |
| 59 | bne ArmWaitScuEnabled\r |
| 60 | bx lr\r |
| 61 | \r |
| 62 | END\r |
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