projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 5f525769 OM |
1 | /** @file\r |
| 2 | *\r | |
| 3 | * Copyright (c) 2014, ARM Limited. All rights reserved.\r | |
| 4 | *\r | |
| 5 | * This program and the accompanying materials are licensed and made available\r | |
| 6 | * under the terms and conditions of the BSD License which accompanies this\r | |
| 7 | * distribution. The full text of the license may be found at\r | |
| 8 | * http://opensource.org/licenses/bsd-license.php\r | |
| 9 | *\r | |
| 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | *\r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #include <Library/ArmLib.h>\r | |
| 16 | #include <Library/ArmGicLib.h>\r | |
| 17 | \r | |
| 18 | ARM_GIC_ARCH_REVISION\r | |
| 19 | EFIAPI\r | |
| 20 | ArmGicGetSupportedArchRevision (\r | |
| 21 | VOID\r | |
| 22 | )\r | |
| 23 | {\r | |
| eadbec01 AB |
24 | UINT32 IccSre;\r |
| 25 | \r | |
| 5f525769 OM |
26 | // Ideally we would like to use the GICC IIDR Architecture version here, but\r |
| 27 | // this does not seem to be very reliable as the implementation could easily\r | |
| 28 | // get it wrong. It is more reliable to check if the GICv3 System Register\r | |
| 29 | // feature is implemented on the CPU. This is also convenient as our GICv3\r | |
| 30 | // driver requires SRE. If only Memory mapped access is available we try to\r | |
| 31 | // drive the GIC as a v2.\r | |
| 32 | if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {\r | |
| 37ec4d9a AB |
33 | // Make sure System Register access is enabled (SRE). This depends on the\r |
| 34 | // higher privilege level giving us permission, otherwise we will either\r | |
| 35 | // cause an exception here, or the write doesn't stick in which case we need\r | |
| 36 | // to fall back to the GICv2 MMIO interface.\r | |
| 37 | // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r | |
| 38 | // at the same exception level.\r | |
| 39 | // It is the OS responsibility to set this bit.\r | |
| eadbec01 AB |
40 | IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r |
| 41 | if (!(IccSre & ICC_SRE_EL2_SRE)) {\r | |
| 42 | ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);\r | |
| 43 | IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r | |
| 44 | }\r | |
| 45 | if (IccSre & ICC_SRE_EL2_SRE) {\r | |
| 37ec4d9a AB |
46 | return ARM_GIC_ARCH_REVISION_3;\r |
| 47 | }\r | |
| 5f525769 OM |
48 | }\r |
| 49 | \r | |
| 50 | return ARM_GIC_ARCH_REVISION_2;\r | |
| 51 | }\r |