ArmPkg/ArmGic: Introduced support for GicV2 to ArmGicDxe

[mirror_edk2.git] / ArmPkg / Drivers / ArmGic / ArmGicLib.c

/** @file\r
*\r
*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Base.h>\r
#include <Library/ArmGicLib.h>\r
#include <Library/IoLib.h>\r
\r
#include "GicV2/ArmGicV2Lib.h"\r
\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  // Read the GIC Identification Register\r
  return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);\r
}\r
\r
UINTN\r
EFIAPI\r
ArmGicGetMaxNumInterrupts (\r
  IN  INTN          GicDistributorBase\r
  )\r
{\r
  return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicSendSgiTo (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          TargetListFilter,\r
  IN  INTN          CPUTargetList,\r
  IN  INTN          SgiId\r
  )\r
{\r
  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);\r
}\r
\r
UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
  IN  UINTN          GicInterruptInterfaceBase\r
  )\r
{\r
  return ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicEndOfInterrupt (\r
  IN  UINTN                 GicInterruptInterfaceBase,\r
  IN UINTN                  Source\r
  )\r
{\r
  ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterrupt (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  Source\r
  )\r
{\r
  UINT32    RegOffset;\r
  UINTN     RegShift;\r
\r
  // Calculate enable register offset and bit position\r
  RegOffset = Source / 32;\r
  RegShift = Source % 32;\r
\r
  // Write set-enable register\r
  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterrupt (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  Source\r
  )\r
{\r
  UINT32    RegOffset;\r
  UINTN     RegShift;\r
\r
  // Calculate enable register offset and bit position\r
  RegOffset = Source / 32;\r
  RegShift = Source % 32;\r
\r
  // Write clear-enable register\r
  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);\r
}\r
\r
BOOLEAN\r
EFIAPI\r
ArmGicIsInterruptEnabled (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  Source\r
  )\r
{\r
  UINT32    RegOffset;\r
  UINTN     RegShift;\r
\r
  // Calculate enable register offset and bit position\r
  RegOffset = Source / 32;\r
  RegShift = Source % 32;\r
\r
  return ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicDisableDistributor (\r
  IN  INTN          GicDistributorBase\r
  )\r
{\r
  // Disable Gic Distributor\r
  MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);\r
}\r

VOID\r
EFIAPI\r
ArmGicEnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  return ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);\r
}\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  )\r
{\r
  return ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);\r
}\r